KR20020018937A - method of driving a plasma display panel in a selectively turning-off manner - Google Patents

Abstract

PURPOSE: A method for driving plasma display panel in selective erasing driving type is provided to prevent a contrast from being reduced by blocking a light discharge for a reset period. CONSTITUTION: One frame of the input image signal is divided into a plurality of sub fields to drive a plasma display panel(50) having X and Y electrodes(12, 14). Each of the divided sub fields includes a reset period, an address discharge period and a sustain discharge period. A full display cell(36a) is provided with uniform charges for the reset period. The charges are alternatively erased from the turned off display cell for the address discharge period. The display cells, in which the charges are not erased, are subjected to the sustain discharge for the address discharge period which presets each divided sub fields with a particular weighted value, so that the sub fields are all combined to exhibit multiple gray scales. A sustain pulse is alternately applied between the X electrode and the Y electrode for a sustain charge period to discharge the display cells which are not erased for the address discharge period.

Description

Method of driving a plasma display panel in a selectively turning-off manner

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to prevent light emission during a reset period in a selective erasure driving method capable of enlarging the number of subfields per field, thereby reducing contrast. A method of driving a plasma display panel of a selective erase driving method.

Conventionally, examples of the plasma display panel (PDP) are described in US Patent No. 6078139 "Front Panel for Plasma Display", US Patent No. 6075319 "Plasma Display Panel Apparatus and Manufacturing Method thereof (Plasma display) panel device and method for fabricating the same ", US Patent Publication No. 6069446" Plasmadisplay panel with ring-shaped loop electrodes, US Patent Publication No. 6066917 "Plasma Display Panel Plasma display panel, US Patent Publication No. 6034656, "Plasma display panel and method of controlling brightness of the same."

In addition, various driving methods of the PDP are described in US Patent Publication No. 6054970, "Method for driving an AC-driven PDP, US Patent Publication No. 5952986", and a display apparatus (Driving). method of an AC-type PDP and the display device ".

As shown in FIG. 1, a general AC surface discharge plasma display panel 50 includes a combination of a front substrate unit 10 and a rear substrate unit 30 facing each other. The inside is sealed at the outer circumference of the front substrate unit 10 and the rear substrate unit 30 so as to maintain a vacuum, and discharge gas is injected therebetween.

The front substrate unit 10 is, for example, indium tin oxide (ITO) formed in pairs with each other on one surface of the front base plate 11 made of glass and on the rear substrate unit 30 side of the front base plate 11. A combination of the X and Y electrodes 12 and 14 and the front dielectric layer 13 are made of material. In this case, the X and Y electrodes 12 and 14 are spaced apart from each other by a leading end of a stripe shape on one surface of the front base plate 11 facing the rear substrate unit 30 to form a continuous structure in parallel. The dielectric layer 13 has a structure that is coated on one surface of the front base plate 11 so as to cover the front X and Y electrodes 12 and 14. At this time, a protective film layer (not shown), for example, an MgO layer is further disposed on the outermost surface of the front dielectric layer 13, and the protective film layer serves to improve the discharge characteristics of the front dielectric layer 13.

On the other hand, the rear substrate unit 30 corresponding to the front substrate unit 10 is similar to the front substrate 10, for example, the rear base plate 31 of the glass material, and the rear base plate 31 A combination of an address electrode 32 formed to intersect the X and Y electrodes 12 and 14 and a rear dielectric layer 33 coated to cover the address electrode 32 on an upper side of the front base plate 11 of the substrate. The barrier ribs 34 are formed to provide a constant discharge space filled with the discharge gas between the front substrate unit 10 and the R, G, and B phosphor layers 35 are formed between the barrier ribs 34. Is formed. The discharge space where the X and Y electrodes 12 and 14 and the address electrode 32 intersect constitute the display cell 36, and the R, G and B phosphor layers 35 are generated by discharge. By colliding with ultraviolet rays, light of R, G, and B colors is emitted.

The driving method of the plasma display panel 50 having such a structure includes an address / dielectric field separation method (described in Japanese Patent Laid-Open Publication No. Hei 4-195188 (1992)) and an address / dielectric field multiple method (Japanese Patent). No. 2,528,195), but mainly address / dielectric field separation method is applied, and one field (frame) is displayed for gray scale display, for example, the first to eighth subfields. Each subfield includes a reset period, an address discharge period, a sustain discharge period, and each subfield is set with a specific sustain discharge period. The gradation is displayed, and the luminance is determined by the short and long intervals between the sustain discharges, that is, the number of sustain pulses.

On the other hand, the control circuit block 100 of the plasma display panel 50 for the above-described driving method is shown as a detailed block diagram in FIG. In FIG. 2, a clock signal, data, and vertical and horizontal synchronization signals are input to the control circuit block 100, and the voltage waveform described later on the address electrode 32 by the address driver 101 via the display data control unit 105. Is applied to the Y electrode 14 by the Y scan driver 102 via the scan driver control unit 107, the common driver control unit 108, and the Y common driver 104 of the panel drive control unit 106. Voltage waveform pulses to be described later are applied, and voltage pulses described below are applied to the X electrode 12 by the X common driver 103 via the common driver control unit 108.

In addition, the driving method of the plasma display panel 50 includes a selective writing method and a selective erasing method. The selective write method is a driving method in which the charges of all the discharge cells are appropriately controlled in the reset period to form and sustain discharge the electric charges only for the display cells 36 to be turned on in the address discharge period. After the charges are uniformly formed in the display cells 36, the display cells 36 are discharged, the charges are erased, and the sustain discharges are not discharged only for the display cells 36 that do not want to be turned on during the address discharge period.

3 shows a drive waveform diagram of a selective writing method of a typical plasma display panel 50 of the related art. In the reset period of each subfield in Fig. 3, all Y electrodes 14 are first set to 0V level, and at the same time, the front write pulses of high voltage (approximately 350V) are applied to the X electrodes 12 until the time until then. Regardless of the display state, discharge is performed in all display cells 36 in all display lines. At this time, the potential of the address electrode 32 is around 100V. The wall charges are accumulated on the front surface dielectric layer 13 covering the X electrode 12 and the Y electrode 14 by this front surface discharge. That is, -charge is accumulated on the X electrode 12, and + charge is accumulated on the Y electrode 14. Next, the potentials of the X electrode 12 and the address electrode 32 become 0 V, so that the voltage of the wall charge itself exceeds the discharge start voltage in all the display cells 36, and the discharge is started. The discharge ends. So-called self-erasing discharge. By this self-erasing discharge, the state of all the display cells 36 in the panel is brought into a uniform state without wall charges, whereby the next address (write) discharge can be stabilized. In addition, as shown in FIG. 3, a gradually increasing priming erase pulse may be applied to the Y electrode 14. The priming erase pulses further discharge cells in which the wall charges are not completely erased to completely initialize all the display cells 36.

Next, in the address discharge period, address discharge is sequentially performed in order to turn on / off the display cells 36 in accordance with the display data. First, a predetermined voltage (approximately 50 V) is applied to the X electrode 12, and a scan pulse (approximately -150 V) is sequentially applied to the Y electrode 14, while sustain discharge is performed in the address electrode 32. An address pulse (about 50 V) is selectively applied to the display cell 36 to be caused, that is, the address electrode 32 corresponding to the display cell 36 to be turned on, so that the address electrode 32 of the display cells 36 to be turned on and Discharge occurs between the Y electrodes 14, whereby a wall charge of a quantity that can be sustained discharged later is accumulated. In addition, a predetermined voltage (about -50 V) is applied to the Y electrode 14 to which the scan pulse is not applied so that no discharge occurs.

Thereafter, in the sustain discharge period, sustain discharge pulses (approximately 180 V) are applied to the Y electrode 14 and the X electrode 12 alternately to perform sustain discharge, thereby performing image display of one subfield. That is, in the display cell 36 in which wall charges are accumulated in the address discharge period, the discharge occurs because the voltage due to the wall charges overlaps the sustain discharge pulse, but the wall cells do not accumulate in the address discharge period. In (), no discharge occurs even when the sustain discharge pulse is applied, so that image display of one subfield can be performed.

The above-described selective writing method has an advantage over the selective erasing method described later in terms of contrast enhancement, but the address discharge period should be 2 ms (address discharge time is about 0.2 ms and wall charge formation time is about 1.8 ms). The disadvantage is that when the subfield is extended, the data IC is doubled along with the up / down panel driving.

4 illustrates a drive waveform of a selective erasing method of a typical plasma display panel. In the reset period of each subfield in Fig. 4, all Y electrodes 14 are first set to 0V level, and the display until then is applied to the X electrode 12 by applying a high voltage (about 350V) write-in pulse. Regardless of the state, discharge is performed in all display cells 36 of all display lines, and the polarity is inverted again to apply positive sustain pulses to all the Y electrodes 14 to uniformly charge all the display cells 36. After that, as described above only for the display cells 36 that do not want to be lit in the address discharge period, the sustain discharges are discharged and the display cells 36 for which the wall charges are not erased in the sustain discharge period are discharged. The sustain discharge pulse (approximately 180 V) is applied to the X electrode 12 and the Y electrode 14 alternately so as to light it. As the sustain discharge is performed in this manner, image display of one subfield is performed.

This selective erasing method allows the addressing time for erasing wall charges to be 1 ms (wall charge elimination time is about 0.8 ms), which is 1/2 of the above writing method, thus increasing the number of sustain discharges. Although it is effective in improving the brightness, there is a problem that the back contrast is greatly reduced by causing light emission by repeatedly performing the front erase pulse and the polarity inversion sustain pulse to uniformly form the wall charge in the reset period.

Accordingly, an object of the present invention is to solve the above-mentioned conventional problems, and to prevent light emission during a reset period in the selective erasing method by ADS driving which can increase the number of subfields with a small addressing time, thereby reducing contrast. The present invention provides a method of driving a plasma display panel of a selective erasure driving method capable of preventing.

1 is a block diagram illustrating a general plasma display panel;

FIG. 2 is a detailed block diagram illustrating a control circuit and a driving unit of FIG. 1. FIG.

3 is a drive waveform diagram of a selective writing method of a typical representative plasma display panel;

4 is a drive waveform diagram of a selective erasing method of a typical representative plasma display panel;

5 is a driving waveform diagram of a plasma display panel according to an embodiment of the present invention;

FIG. 6 is a (Y-X) waveform diagram showing a change in inclination of the ramp waveform reset pulse of FIG. 5;

FIG. 7 is a diagram illustrating a change in detecting voltage according to a change in slope of the reset pulse of FIG. 6.

8A and 8B are diagrams showing contrast by the write driving method, and FIG. 8C is a diagram showing contrast by the selective erasing method of the present invention;

9 is a time comparison table of main periods of the selective writing method and the selective erasing method;

<Description of the symbols for the main parts of the drawings>

10: front substrate unit 12, 14: X-Y electrode

13: front dielectric layer 30: backplane unit

32: address electrode 33: rear dielectric layer

34: partition 35: R, G, B phosphor layer

36: display cell 50: plasma display panel

101: address driver 102: Y scan driver

103: X common driver 104: Y common driver

105: display data control unit 106: panel drive control unit

107: scan driver control unit 108: common driver control unit

109: control unit

In order to achieve the above object, the present invention provides a plurality of X electrodes and Y electrodes arranged in parallel with one of opposing surfaces of a front base plate and a rear base plate, and a display cell intersecting with the X electrode and Y electrode. One frame of an input image signal is divided into a plurality of subfields to drive a plasma display panel having a plurality of address electrodes arranged on the other side thereof. Each divided subfield includes a reset period, an address discharge period, The sustain discharge period is included, and in the reset period, charges are uniformly formed in all the display cells, and in the display cells that are not lit during the address discharge period, the charges are selectively erased, and each subfield is combined to express multi-gradation. In each of the divided subfields, the display cells whose charges are not erased in a predetermined address discharge period with a specific weight are turned on. A method of driving a plasma display panel of a selective erase driving method for sustain discharge of a battery, the method comprising: initially having a DC component between an X electrode and a Y electrode to uniformly form charge in all display cells during the reset period; From the direct current component, the voltage rises to the discharge voltage for making the wall charges of all the display cells uniform. At that discharge voltage, the wall charges of all the display cells are kept uniform, and a reset pulse gradually descending to 0 volts is applied. By maintaining the wall charge uniformly in all the display cells and preventing light emission due to the strong discharge, and in the sustain discharge period, between the X electrode and the Y electrode to maintain the discharge of the display cells in which the charge is not erased during the address discharge period. It is characterized by applying a sustain pulse alternately.

The reset pulse can be obtained by applying a ramp pulse that is a full-screen write pulse to the Y electrode and applying a pulse having an inverted polarity with the ramp pulse to the X electrode as an initial direct current component, and a ramp pulse applied to the Y electrode. It is preferable that the increase of is terminated before the rising point of the polarity inverted pulse applied to the X electrode, and the rise of the polarity inverted pulse is finished before the falling point of the full-screen write pulse. In addition, the rising time of the full-screen writing pulse is preferably about 300 μs to prevent the decrease in contrast caused by the occurrence of the strong discharge, and the time between the rising end of the polarity-inverted pulse and the end of the falling end of the full-screen writing pulse. In order to prevent the wall charge erasing failure of the display cell caused by the strong discharge and to prevent the lowering of the contrast, it is preferably about 150 μs. In the reset period, the same pulse as that applied to the X electrode is applied to the address electrode.

This configuration of the present invention can complement the disadvantages caused by the lack of the number of subfields in the conventional writing method and the problem of lowering the contrast in the erasing method. That is, while reducing contrast in the selective erasure driving method, the addressing time can be shortened to increase the total number of subfields. As a result, it is easy to apply to highly integrated cells in high-definition TVs and to improve image quality. do.

Hereinafter, a method of driving a plasma display panel of a selective erase driving method according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a driving waveform diagram of the plasma display panel 50 according to an embodiment of the present invention.

The method of driving the plasma display panel of the selective erase driving method according to an exemplary embodiment of the present invention may be applied to the plasma display panel 50 of FIG. 1 and the control circuit block 100 of FIG. 2. The address / dielectric field separation method described above is applied.

That is, as shown in Figure 1, the plasma display panel 50 for applying the present invention, at least, a plurality of parallel arranged on any one surface of the opposing surface of the front base plate 11 and the rear base plate 31 An X electrode 12 and a Y electrode 14, and a plurality of address electrodes 32 disposed on the other surface to intersect the X electrode 12 and the Y electrode 14 to form the display cell 36; It is configured by.

In addition, a selective erase driving method is applied to drive the plasma display panel 50. That is, one frame of the input image signal is divided into a plurality of subfields, and each of the divided subfields includes a reset period, an address discharge period, and a sustain discharge period, and are uniform to all display cells 36 in the reset period. The charge is selectively formed, the charge is selectively erased in the display cells 36 that will not be lit during the address discharge period, and the address discharge is preset with a specific weight for each divided subfield to express the multi-gradation by combining the respective subfields. The image display of one subfield is performed by sustaining discharge for turning on the display cells 36 whose charges have not been erased in the period.

In the driving method of the plasma display panel 50 having such a configuration, in the driving method according to the embodiment of the present invention, first, when the reset period arrives, the common driver control unit 108 of FIG. 5), as shown in FIG. 5, after instantaneous descent from time point T1 to, for example, -180V, -180V is kept constant for the time from time point T1 to time point T3, and at time point T3. During the rise time up to the time point T4, a full-screen write pulse having a form of rising at a first rising rate from -180V to 0V is applied to the X electrode 12 as a polarity inverted pulse. At the same time, the common driver control unit 108 controls the Y common driver 104 to ascend at a second ascent rate from 0 V, for example, 180 V, during the rise time from the time point T1 to the time point T2, and at the time point T2, the time points T3, T4. After 180 V is kept constant for the time until the time T5, the ramp pulse, that is, the full-screen writing pulse, is lowered to the Y electrode during the falling time from the time T5 to the time T6. Is authorized. As a result, all the display cells 36 are turned on during the reset period.

Here, the application of the lamp pulse is to maintain the good initialization state of the display cells by first making the different wall charge amounts of the display cells 36 the same. Second, it is to prevent the light emission generated in the case of the strong discharge in which the voltage across the X and Y electrodes is suddenly increased to 360 V, thereby preventing the contrast from being lowered, thereby achieving the contrast of the display cell 36. Therefore, in this invention, it is preferable to make time from T1 to the time point T2 about 300 microseconds, for example.

On the other hand, if the voltage across the X and Y electrodes drops suddenly at 360V after the time point T3, a strong discharge occurs and the wall charges of the display cell are erased so that the erase operation is not performed at the next address discharge period. Therefore, in order to prevent the occurrence of strong discharge and maintain full screen writing, the voltage of the Y electrode 14 is kept constant at 180V for the time from the time point T3 to the time point T4, and the voltage of the X electrode 12 is kept from -180V to 0V. After raising at a constant first rising rate, maintaining the voltage of the Y electrode 14 at 180V and maintaining the voltage of the X electrode 12 at 0V for a time from the time point T4 to the time point T5, and then the time point at the time point T5. During the time up to T6, the voltage of the Y electrode 14 drops from 180V to 0V at a constant drop rate, and the voltage of the X electrode 12 is maintained at 0V. Accordingly, the wall charge can be kept constant and light emission can be prevented. The time between the time point T3 and the time point T6 is preferably, for example, around 150 s.

In this way, the present invention can improve the image quality by preventing the lowering of the contrast, which is mainly a problem in the conventional selective erase driving method.

Next, when the address discharge period arrives, the scan driver control unit 107 controls the Y scan driver 102 to control the Y electrode 14 corresponding to the first line among the display lines of the PDP 50. The erase pulse between the address dischargers is applied. In addition, the display data control section 105 controls the address driver 101 to display the specific display cells 36, e.g., display cells (e.g., display cells) that need erasing discharge among all the address electrodes 32 located on the first first line. An address pulse of 100 V, for example, is applied to the address electrode 32 corresponding to 36a).

In this case, so-called erase discharge occurs between the Y electrode 14 located on the first line and the specific address electrode 32, and thus, the display cell 36 of the display cell 36 located on the first first line ( The wall charges are eliminated on the surface of 36). This wall charge erasing process is performed according to the sequential method, in which the Y electrode 14 located in the second line and the Y electrode 14 located in the third line. The sequence proceeds in sequence across all display lines.

Therefore, the erase pulses scanned in the selective erase drive method of the present invention have a narrow width of about 1 μs and a voltage of about -60V, for example, whereas the write pulses scanned in the conventional selective write drive methods usually have a long width of 2 μs or more. Therefore, the present invention can considerably shorten the address period per one subfield and increase the number of subfields per one frame, compared to the conventional selective write driving method. Therefore, the present invention can be applied to a high density cell in a high vision TV and can improve image quality.

On the other hand, after the above-described series of wall charge erase processes are performed, when the sustain discharge period arrives, the common driver control unit 108 alternately controls the X common driver 103 and the Y common driver 104, and thus the X electrode. Alternately apply sustain pulses for X and Y to (12) and the Y electrode 14. In this case, each time the voltage is changed between the X electrode 12 and the Y electrode 14, sustain discharge occurs in the display cells 36 in which so-called wall charges are not erased. The B phosphor layer 37 is kept in a light emitting state so that image display of one subfield is performed. Thereafter, for example, a sawtooth erase pulse can be applied to the X electrode 12, and these processes are repeated.

FIG. 6 is a (Y-X) waveform diagram illustrating a change in slope of the ramp waveform reset pulse of FIG. 5, and FIG. 7 is a diagram illustrating a change in the detection voltage according to the change in the slope of the reset pulse of FIG. 6.

In the (YX) waveform diagram of FIG. 6, a DC component is initially included between the X electrode 12 and the Y electrode 14 to uniformly form charge in all the display cells 36 during the reset period. From the direct current component, the wall voltage of all the display cells 36 is increased to a uniform discharge voltage, and the wall charges of all the display cells 36 are kept uniform at the discharge voltage. A reset pulse is applied. By such a reset pulse, as described above with reference to FIG. 5, wall charges are uniformly maintained in all display cells 36 and light emission due to strong discharge can be prevented.

In Fig. 6, the DC component is fixed at 200V in the (YX) waveform, and the height of the voltage from the DC component voltage to the discharge voltage is changed to 160V, 180V, 200V, and the slope to each discharge voltage, that is, the slope As a result of changing the width, the graph of FIG. 7 was obtained by the testing pulse. The right side of the dotted line in Figure 7 can obtain a stable detecting voltage, and showed a difference of 45 to 50 volts with respect to the discharge voltage difference.

As can be seen in Figs. 6 and 7, even when the discharge voltage is changed between 360 and 400V even with the same ramp waveform, the slope width of the lamp is generally stabilized for at least 50 ms or more, and even more than approximately 100 Hz or more. It becomes possible to drive stably. This means that it is possible to drive stably if the rising slope is 4V / kV or less.

8A and 8B show the contrast by the write driving method in a diagram, and FIG. 8C shows the contrast by the selective erasing method of the present invention in a diagram. 8A and 8B and 8C (the upper diagram is an optical signal and the lower diagram is a voltage signal), the light emission is at least larger than that of the write driving method in the reset period according to the erase driving method of the present invention. It is not much, and it can be seen that a large light is not emitted even during the address discharge period, so that the contrast of the light emitted between the sustain discharge batteries is high.

On the other hand, according to FIG. 9, which is a time comparison table of the major writing periods of the selective writing method and the selective erasing method, when one frame is set to 12 subfields, the total time taken is 16.16 ms in total, compared to 18.02 ms in writing driving. It is much smaller, and in the case of write driving, it is impossible to implement 12 subfields because it is larger than 16.7 ms per frame (1/60 second), but in the case of erasing driving, the implementation becomes possible.

As described in detail above, in the driving method of the PDP according to the present invention, a DC component is initially applied between the X electrode 12 and the Y electrode 14 to uniformly form charge in all display cells during the reset period. And a reset pulse which rises from the direct current component to the discharge voltage for making the wall charges of all the display cells uniform, and maintains the wall charges of all the display cells uniform at the discharge voltage, and gradually drops to zero volts again. It is possible to maintain uniform wall charges in all display cells and to prevent light emission due to strong discharge, and to shorten the address discharge period, thereby increasing the total number of subfields. Accordingly, it can be easily applied to high-density cells in high-definition TVs and image quality can be improved. In addition, it is possible to obtain the effect of splitting up and down, so that the address data IC can be reduced from 80 to 40, for example, and the FPCB and address PCB can be reduced to 1/2. .

Accordingly, the present invention can achieve the above-mentioned effect by complementing the problem of the lack of the number of subfields in the conventional write drive and the contrast reduction problem in the erase driving method.

On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (8)

A plurality of X electrodes 12 and Y electrodes 14 arranged in parallel to any one of the opposing surfaces of the front base plate 11 and the rear base plate 31, the X electrode 12 and the Y electrode 14. 1 frame of an image signal input to drive the plasma display panel 50 having a plurality of address electrodes 32 disposed on the other surface to form the display cells 36 in a plurality of subfields. Each divided subfield includes a reset period, an address discharge period, and a sustain discharge period. In the reset period, charges are uniformly formed in all the display cells 36, and display cells (which are not lit in the address discharge period) In FIG. 36, the charges are selectively erased, and each of the subfields is turned on to turn on the display cells 36 whose charges are not erased in a predetermined address discharge period with a specific weight for each divided subfield. for In a method of driving a plasma display panel of a selective erasure driving method for sustaining discharge: It has a DC component initially between the X electrode 12 and the Y electrode 14 to uniformly form charge in all the display cells 36 during the reset period, and all display cells 36 from the DC component. ) To a discharge voltage for uniform wall charge, and rises to a slope of at least 4 V / ㎲ or less, and maintains the wall charges of all display cells 36 to be uniform at that discharge voltage, and then gradually drops to 0 volts. By applying a reset pulse, the wall charges are uniformly maintained in all display cells 36 and light emission due to strong discharge is prevented. In the sustain discharge period, the display cells 36 whose charges are not erased during the address discharge period are prevented. And a sustain pulse is alternately applied between the X electrode (12) and the Y electrode (14) so as to maintain the discharge. The method of claim 1, wherein the reset pulse applies a ramp pulse that is a full-screen write pulse to the Y electrode 14, and at the same time applies a pulse whose polarity and polarity are inverted to the X electrode 12 as an initial direct current component. A method of driving a plasma display panel of a selective erase driving method. The method of claim 2, wherein the rising of the pulse pulse applied to the Y electrode 14 ends before the rising point of the polarity inverted pulse applied to the X electrode 12, the rise of the polarity inverted pulse is A method of driving a plasma display panel of a selective erasure driving method, characterized in that it terminates before the falling point of the full-screen write pulse. 3. The method of driving a plasma display panel according to claim 2, wherein a rise time of the reset pulse is set to about 300 mu s so as to prevent further lowering of contrast due to strong discharge. 3. The method of driving a plasma display panel of claim 2, wherein the voltage applied to the X electrode is maintained at 0V during the address discharge period. 5. The method of claim 3 or 4, wherein the time between the rising edge of the polarity-inverted pulse and the falling end of the full-screen writing pulse prevents wall charge erasing failure of the display cell caused by the strong discharge and prevents the lowering of the contrast. In order to drive the plasma display panel of the selective erasure driving method characterized in that about 150μs. 3. The method of claim 1 or 2, wherein the initial DC component is 150V to 210V. The method of driving a plasma display panel of claim 1 or 2, wherein a voltage equal to an X pulse is applied to the address pulse in the reset period.