KR20020078657A - method of driving a plasma display panel in a selectively turning-off manner - Google Patents

Abstract

PURPOSE: A method for driving a plasma display panel of a selectively erasable driving method is provided, which can increase the number of sub fields by reducing an addressing time and thus can improve a gray scale and can improve a high brightness and a contrast, and can reduce power consumption and can increase a lifetime of a MOSFET, and can increase a brightness by increasing the frequency of a sustain discharge pulse. CONSTITUTION: According to the plasma display panel(50), a number of X electrodes(12) and a number of Y electrodes(14) are arranged on one of a front base plate(11) and a back base plate(31) in parallel, and a number of address electrodes(32) are arranged on another side to form a display cell(36) by crossing with the X electrode and the Y electrode. To drive the plasma display panel, 1 frame of an inputted image signal is divided into a number of sub fields, and each divided sub field includes a reset period and an address discharge period and a sustain discharge period. Charges are formed uniformly in all display cells during the reset period, and charges are erased selectively from the display cells not turned on during the address discharge period. And the display cells are sustain-discharged during the sustain discharge period to turn on the display cells whose charges are not erased during the address discharge period. A reset pulse is applied to the Y electrode during the reset period which increasing from an initial voltage to a discharge voltage with a Ramp waveform during the first time, and the discharge voltage is maintained during the second time. And after the first time, the discharge voltage is dropped to the initial voltage and then is maintained during the third time, and it is dropped to a ground during the fourth time. The X electrode maintains a ground state(0V) during the reset period and the address discharge period. And the address electrode maintains a ground state(0V) during the reset period.

Description

Method of driving a plasma display panel in a selectively turning-off manner

The present invention relates to a method of driving a plasma display panel of a selective erase driving method. More particularly, the number of subfields can be increased by reducing the addressing time through an erase driving waveform, thereby improving gray scale. High brightness, high contrast, low sustain voltage increase switching device utilization, reduce power, and further improve contrast by using lamp-reset waveforms. The addressing voltage can be expected, the wall charge control is easy, and stable discharge is possible, and the time can be reduced by decreasing the slope of the down part of the ramp waveform, thereby selectively erasing to increase the brightness of the sustain discharge pulse to increase the brightness. A driving method of a plasma display panel of a driving method.

As shown in FIG. 1, a general AC surface discharge plasma display panel 50 includes a combination of a front substrate unit 10 and a rear substrate unit 30 facing each other. The inside is sealed at the outer circumference of the front substrate unit 10 and the rear substrate unit 30 so as to maintain a vacuum, and discharge gas is injected therebetween.

The front substrate unit 10 is, for example, indium tin oxide (ITO) formed in pairs with each other on one surface of the front base plate 11 made of glass and on the rear substrate unit 30 side of the front base plate 11. A combination of the X and Y electrodes 12 and 14 and the front dielectric layer 13 are made of material. In this case, the X and Y electrodes 12 and 14 are spaced apart from each other by a leading end of a stripe shape on one surface of the front base plate 11 facing the rear substrate unit 30 to form a continuous structure in parallel. The dielectric layer 13 has a structure that is coated on one surface of the front base plate 11 so as to cover the front X and Y electrodes 12 and 14. At this time, a protective film layer (not shown), for example, an MgO layer is further disposed on the outermost surface of the front dielectric layer 13, which serves to improve the discharge characteristics of the front dielectric layer 13.

On the other hand, the rear substrate unit 30 corresponding to the front substrate unit 10 is similar to the front substrate 10, for example, the rear base plate 31 of the glass material, and the rear base plate 31 A combination of an address electrode 32 formed to intersect the X and Y electrodes 12 and 14 and a rear dielectric layer 33 coated to cover the address electrode 32 on an upper side of the front base plate 11 of the substrate. The barrier ribs 34 are formed to provide a constant discharge space filled with the discharge gas between the front substrate unit 10 and the R, G, and B phosphor layers 35 are formed between the barrier ribs 34. Is formed. The discharge space where the X and Y electrodes 12 and 14 and the address electrode 32 intersect constitute the display cell 36, and the R, G and B phosphor layers 35 are generated by discharge. By colliding with ultraviolet rays, light of R, G, and B colors is emitted.

The driving method of the plasma display panel 50 having such a structure includes an address / dielectric field separation method (described in Japanese Patent Laid-Open Publication No. Hei 4-195188 (1992)) and an address / dielectric field multiple method (Japanese Patent). No. 2,528,195), but mainly address / dielectric field separation method is applied, and one field (frame) is displayed for gray scale display, for example, the first to eighth subfields. Each subfield includes a reset period, an address discharge period, a sustain discharge period, and each subfield is set with a specific sustain discharge period. The gradation is displayed, and the luminance is determined by the short and long intervals between the sustain discharges, that is, the number of sustain pulses.

On the other hand, the control circuit block 100 of the plasma display panel 50 for the above-described driving method is shown as a detailed block diagram in FIG. In FIG. 2, a clock signal, data, and vertical and horizontal synchronization signals are input to the control circuit block 100, and the voltage waveform described later on the address electrode 32 by the address driver 101 via the display data control unit 105. Is applied to the Y electrode 14 by the Y scan driver 102 via the scan driver control unit 107, the common driver control unit 108, and the Y common driver 104 of the panel drive control unit 106. Voltage waveform pulses to be described later are applied, and voltage pulses described below are applied to the X electrode 12 by the X common driver 103 via the common driver control unit 108.

In addition, the driving method of the plasma display panel 50 includes a selective writing method and a selective erasing method. The selective write method is a driving method in which charges of all the discharge cells are set to "0" in the reset period, and then charges are generated and sustained discharged only for the display cells 36 to be turned on in the address discharge period. After the charges are uniformly formed in the entire display cells 36 in the reset period, only the display cells 36 that do not want to be turned on in the address discharge period are erased and sustain discharged.

3 shows a drive waveform diagram of a selective writing method of a conventional plasma display panel 50 which is a Pulse-Reset ADS method of Fujitsu. In the reset period of each subfield in Fig. 3, all Y electrodes 14 are first set to 0V level, and at the same time, the front write pulses of high voltage (approximately 350V) are applied to the X electrodes 12 until the time until then. Regardless of the display state, discharge is performed in all display cells 36 in all display lines. At this time, the potential of the address electrode 32 is around 100V. The wall charges are accumulated on the front surface dielectric layer 13 covering the X electrode 12 and the Y electrode 14 by this front surface discharge. That is, -charge is accumulated on the X electrode 12, and + charge is accumulated on the Y electrode 14. Next, the potentials of the X electrode 12 and the address electrode 32 become 0 V, so that the voltage of the wall charge itself exceeds the discharge start voltage in all the display cells 36, and the discharge is started. The discharge ends. So-called self-erasing discharge. By this self-erasing discharge, the state of all the display cells 36 in the panel is brought into a uniform state without wall charges, whereby the next address (write) discharge can be stabilized. In addition, as shown in FIG. 3, a gradually increasing priming erase pulse may be applied to the Y electrode 14. The priming erase pulses further discharge cells in which the wall charges are not completely erased to completely initialize all the display cells 36.

Next, in the address discharge period, address discharge is sequentially performed in order to turn on / off the display cells 36 in accordance with the display data. First, a predetermined voltage (approximately 50 V) is applied to the X electrode 12, and a scan pulse (approximately -150 V) is sequentially applied to the Y electrode 14, while sustain discharge is performed in the address electrode 32. An address pulse (about 50 V) is selectively applied to the display cell 36 to be caused, that is, the address electrode 32 corresponding to the display cell 36 to be turned on, so that the address electrode 32 of the display cells 36 to be turned on and Discharge occurs between the Y electrodes 14, whereby a wall charge of a quantity that can be sustained discharged later is accumulated. In addition, a predetermined voltage (about -50 V) is applied to the Y electrode 14 to which the scan pulse is not applied so that discharge does not occur.

Thereafter, in the sustain discharge period, sustain discharge pulses (approximately 180 V) are applied to the Y electrode 14 and the X electrode 12 alternately to perform sustain discharge, thereby performing image display of one subfield. That is, in the display cell 36 in which wall charges are accumulated in the address discharge period, the discharge occurs because the voltage due to the wall charges overlaps the sustain discharge pulse, but the wall cells do not accumulate in the address discharge period. In (), no discharge occurs even when the sustain discharge pulse is applied, so that image display of one subfield can be performed. In addition, a predetermined voltage (about 65 V) is applied to the address electrode in order to avoid discharge between the address electrode 32 and the X electrode 12 or the Y electrode 14.

The above-described pulse-reset ADS method of Fujitsu Corp. has a problem in that stable discharge of the display cell 36 is difficult due to contrast drop, charge control problem, and large change in Y-level voltage. That is, due to the strong discharge of the pulse reset waveform, the light is large, which may cause contrast degradation, and the reset period may not be properly erased, resulting in discharge instability between address dischargers. Discharge occurs in the select display cell 36, which causes driving problems.

4 shows a drive waveform diagram of the selective writing method of the conventional plasma display panel 50 which is Matsushita's Ramp-Reset ADS method. In Fig. 4, the Matsushita ramp-reset drive waveform has a problem that the sustain frequency is limited because the reset period is considerably long, and the power consumption is high because the sustain voltage is high. In addition, although the charge control is stable, stable discharge of the display cell 36 is possible, but since the reset period is included in each subfield, there is a problem that it is difficult to form several subfields.

Accordingly, the present invention is to solve this problem, it is possible to increase the number of subfields by reducing the addressing time through the erase drive waveform, thereby improving the gray scale, and to achieve high brightness and contrast enhancement Low sustain voltage increases switching device utilization, reduces power, increases MOSFET lifespan, and further improves contrast and lower addressing voltage by using ramp-reset waveforms. It is possible to expect stable, stable discharge because wall charge control is easy, and time can be reduced by decreasing slope of down part of lamp waveform, and selective erasure driving method that can increase brightness by increasing frequency of sustain discharge pulse. To provide a method of driving a plasma display panel of All.

1 is a block diagram illustrating a general plasma display panel;

FIG. 2 is a detailed block diagram illustrating a control circuit and a driving unit of FIG. 1. FIG.

3 is a drive waveform diagram of a selective writing method of a typical representative plasma display panel;

4 is a drive waveform diagram of a selective write method of another exemplary plasma display panel according to the related art;

5 is a driving waveform diagram of a selective erasing method of a plasma display panel according to an embodiment of the present invention;

6 is a driving waveform diagram of a selective erasing method of a plasma display panel according to another exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: front substrate unit 12, 14: X, Y electrode

13: front dielectric layer 30: back substrate unit

32: address electrode 33: rear dielectric layer

34: partition 35: R, G, B phosphor layer

36: display cell 50: plasma display panel

101: address driver 102: Y scan driver

103: X common driver 104: Y common driver

105: display data control unit 106: panel drive control unit

107: scan driver control unit 108: common driver control unit

109: control unit

In order to achieve the above object, a method of driving a plasma display panel of a selective erase driving method according to an exemplary embodiment of the present invention includes a plurality of X electrodes disposed in parallel with one surface of an opposite surface of a front base plate and a rear base plate; One frame of an input image signal for driving a plasma display panel having a Y electrode and a plurality of address electrodes arranged on the other surface to form a display cell intersecting the X electrode and the Y electrode is divided into a plurality of subfields. Each divided subfield includes a reset period, an address discharge period, and a sustain discharge period. In the reset period, charges are uniformly formed in all the display cells, and selectively in the display cells that are not lit during the address discharge period. Specific weights for each divided subfield to eliminate charge and combine each subfield to represent multi-gradation A method of driving a plasma display panel of a selective erase driving method for sustaining and discharging the display cells for which charges are not erased in a predetermined address discharge period, wherein: in the reset period, the Y electrodes are uniformly applied to all display cells. In order to form a charge, the ramp voltage gradually rises from the initial voltage to the discharge voltage for uniformizing the wall charges of all the display cells for a first time, and the wall charges of all the display cells accumulate in a self-erasing state at the discharge voltage. Hold for a second time, and after the first time, step down from the discharge voltage to before and after the initial voltage, hold for a third time, and then apply a reset pulse which gradually ramps down to the ground in a ramp waveform for a fourth time; An X electrode is held in a ground state during the reset period and the address discharge period; The address electrode is maintained in the ground state in the reset period.

In this case, a voltage of about 150V is first applied to the X electrode in the sustain discharge period, and then the sustain voltage is maintained at a voltage of about 150 or 180V after the sustain discharge is stabilized, and the initial voltage of the reset pulse is around 150V. The voltage is set, the discharge voltage is preferably set to a voltage around 400V, and the first, second, third and fourth hours are around 70 Hz, 20 Hz, 10 Hz and 50 Hz, respectively. It is set to the time of.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a driving waveform diagram of a selective erasing method of a plasma display panel according to an embodiment of the present invention.

As shown in FIG. 1, the plasma display panel 50 to which the driving waveforms of FIG. 5 are applied includes a plurality of plasma display panels 50 arranged in parallel with any one of opposing surfaces of the front base plate 11 and the rear base plate 31. An X electrode 12 and a Y electrode 14, and a plurality of address electrodes 32 arranged on the other side to intersect the X electrode 12 and the Y electrode 14 to form the display cell 36; It is configured by.

In order to drive the plasma display panel 50, the conventional ADS method of selective erasure driving is applied, and one frame of an input image signal is divided into a plurality of subfields, and each divided subfield has a reset period and an address. The discharge period and the sustain discharge period are included. In the reset period, charges are uniformly formed in all the display cells 36, and in the display discharge cells 36 which are not lit during the address discharge period, the charges are selectively erased. Each of the divided subfields is combined with each other so as to sustain and discharge the display cells 36 whose charges are not erased in a predetermined address discharge period with a predetermined weight.

In this selective erasing driving method, according to the present invention shown in FIG. 5, the reset pulse applied to the Y electrode 14 in the reset period is the same as the ramp-reset waveform of Matsushita of the selective writing method shown in FIG. As a similar waveform, a voltage that varies over the first time T1 to the fourth time T4 is applied.

That is, the reset voltage is the first from the initial voltage Vo to the discharge voltage Vd for uniformizing the wall charges of all the display cells 36 so as to uniformly charge the all display cells 36. It gradually rises to the ramp waveform during the time T1, and is maintained for the second time T2 so that the wall charges of all the display cells 36 accumulate in the self-erasable state at the discharge voltage Vd, and the first time After T1, the voltage is reduced from the discharge voltage Vd to the voltage before and after the initial voltage Vo and maintained for the third time T3, and then gradually ramps up to the ground 0V in the ramp waveform for the fourth time T4. Coercion

In addition, the X electrode 12 is maintained in the ground state (0V) in the reset period and the address discharge period, and the address electrode 32 is also maintained in the ground state (0V) in the reset period.

The configuration of the present invention illustrated in FIG. 5 will be summarized as follows.

1. Voltage waveform of the Y electrode 14:

-Increase the voltage up to 150V, the initial voltage (Vo).

The voltage is gradually increased during the period of 70 kV set in the first time T1 from 150 V to 400 V, which is the discharge voltage Vd.

-It is maintained for 20 ms set at the second time T2 at 400 V which is the discharge voltage Vd.

-Drop the voltage from 400V to 150V, the discharge voltage (Vd).

Maintain 10ms, the third time (T3) at 150V.

-Slowly decrease the voltage for 50 kHz, the fourth time (T4), from 150V to 0V.

A Y-level voltage of 70V is applied in the address discharge period, but a voltage dropped to OV is applied to the electrode scanned for erasing for 1 kV.

In the sustain discharge period, 150V is first applied from the X electrode 12 to stabilize the sustain discharge, and then maintain the sustain voltage at about 180V.

2. Voltage waveform of the X electrode 12:

-Keep it at GND (OV) during reset period and address discharge period.

-During sustain discharge period, first apply 150V sustain voltage, and after sustain discharge is stabilized, maintain the sustain voltage about 180V, and after sustain discharge, use X-Ramp Erase waveform to control wall charge. Is authorized.

3. Voltage waveform of the address electrode 32:

-Keep it at GND (0V) in reset period and sustain discharge period.

The address voltage is applied in the address discharge period.

As described above, the initial voltage of the reset pulse is set to a voltage around 150V, the discharge voltage is set to a voltage around 400V, and the first, second, third, and fourth times are respectively By driving the plasma display panel 50 at a time before and after 70 Hz, 20 Hz, 10 Hz and 50 Hz, it is expected that the luminance and contrast will be improved by improving the subfield through such an erase driving waveform. That is, since the erasing method reduces the addressing time (from 2 ms to 1 ms), it is possible to divide one frame into many subfields. For this reason, gray scale can be improved and high brightness is attained.

In addition, since the ramp-reset waveform, an improvement in contrast and a low address voltage can be expected, and the wall charge control can be easily performed to enable stable discharge. In addition, since the time can be reduced by the ramp-down slope, that is, the decrease of the fourth time T4, the luminance can be increased by increasing the sustain frequency. In the fourth time T4, the erasing method can be applied even if the value of 200 에서 is 30 에서 in the case of 42 ".

6 is a driving waveform diagram of a selective erasing method of a plasma display panel according to an embodiment of the present invention. In Fig. 6, although the voltage waveforms between the reset period and the address discharger are the same, only one sustain discharge voltage (sustain voltage) of the X electrode 12 and the Y electrode 14 (150V) is used. That is, in the sustain discharge period, the sustain discharge voltage of about 150V is applied to the X electrode 12 and the Y electrode 14, and the same voltage is applied even after the sustain discharge is stabilized.

Accordingly, the sustain discharge voltage is lowered from the existing 180V to 150V, thereby reducing power consumption and increasing the utilization of the switching device.

According to the configuration and operation of the method of driving the plasma display panel of the selective erasure driving method according to the embodiment of the present invention described above, the number of subfields can be increased by reducing the addressing time through the erasure driving waveform, It is possible to improve the scale, improve the brightness and contrast, and lower the sustain voltage to increase the utilization of switching elements, reduce power, and increase the life of the MOSFET. By using the lamp-reset waveform, the contrast can be improved and the low addressing voltage can be expected, the wall charge control is easy, and the stable discharge is possible. There is an effect of increasing the frequency of the pulse to increase the brightness.

Claims (6)

A plurality of X electrodes 12 and Y electrodes 14 arranged in parallel with any one of opposing surfaces of the front base plate 11 and the rear base plate 31, and the X electrode 12 and the Y electrode 14. 1 frame of an image signal input to drive the plasma display panel 50 having a plurality of address electrodes 32 disposed on the other surface to form the display cells 36 in a plurality of subfields. Each divided subfield includes a reset period, an address discharge period, and a sustain discharge period. In the reset period, charges are uniformly formed in all the display cells 36, and display cells (which are not lit in the address discharge period) In FIG. 36, the charges are selectively erased, and each of the subfields is turned on to turn on the display cells 36 whose charges are not erased in a predetermined address discharge period with a specific weight for each divided subfield. for In the driving method of the selective erase driving method of the plasma display panel to maintain discharge of the display cells 36 to the group during the sustain discharge period: In the reset period, in the Y electrode 14 for a first time from the initial voltage to the discharge voltage for uniformizing the wall charges of all the display cells 36 to uniformly charge the all display cells 36. It gradually rises to the ramp waveform, and maintains it for a second time so that the wall charges of all the display cells 36 accumulate in the self-erasable state at the discharge voltage, and after that time, it is stepped down from the discharge voltage to the initial voltage before and after Holding for a third time, and then applying a reset pulse which gradually ramps down to the ground in a ramp waveform for a fourth time; The X electrode 12 is held in the ground state (0V) during the reset period and the address discharge period; And the address electrode (32) is kept in the ground state (0V) during the reset period. The method of claim 1, wherein the sustain discharge is stabilized by first applying a voltage of about 150V to the X electrode 12 during the sustain discharge period, and then a sustain voltage of 150 or 180 V is applied to the X electrode 12 and the Y electrode 14. A method of driving a plasma display panel of a selective erasure driving method, characterized in that the front and rear voltages are applied alternately. The method of claim 1, wherein the initial voltage of the reset pulse is set to a voltage around 150V and the discharge voltage is set to a voltage around 400V. The selective erasure driving method according to claim 1, wherein the first, second, third, and fourth hours are set to a time before and after 70 ms, 20 ms, 10 ms and 50 ms, respectively. A method of driving a plasma display panel. A plurality of X electrodes 12 and Y electrodes 14 arranged in parallel to any one of the opposing surfaces of the front base plate 11 and the rear base plate 31, the X electrode 12 and the Y electrode 14. 1 frame of an image signal input to drive the plasma display panel 50 having a plurality of address electrodes 32 disposed on the other surface to form the display cells 36 in a plurality of subfields. Each divided subfield includes a reset period, an address discharge period, and a sustain discharge period. In the reset period, charges are uniformly formed in all the display cells 36, and display cells (which are not lit in the address discharge period) In FIG. 36, the charges are selectively erased, and each of the subfields is turned on to turn on the display cells 36 whose charges are not erased in a predetermined address discharge period with a specific weight for each divided subfield. for In the method of driving a plasma display panel of a selective erase driving method for sustaining discharge of the display cells 36 in the sustain discharge period: In the reset period, the Y electrode 14 is used to uniformize wall charges of all display cells 36 from an initial voltage set to a voltage around 150V to uniformly form charges on all display cells 36. And gradually ramps up to a ramp waveform for a first time until a discharge voltage set to a voltage around 400V, and maintains for a second time so that wall charges of all display cells 36 accumulate in a self-erasable state at that discharge voltage. After the first time, stepping down from the discharge voltage to before and after the initial voltage and maintaining for a third time, and then applying a reset pulse which gradually ramps down to the ground in a ramp waveform for a fourth time; A voltage dropped to OV to the Y electrode 14 scanned for erasing while applying a Y-level voltage around 70V to the Y electrode 14 except for the Y electrode 14 scanned for erasure in the address period. Is applied for 1 ms; The X electrode 12 is kept in the ground state (0V) during the reset period and the address discharge period, and is sequentially around 150V to the X electrode 12, the Y electrode 14, and the X electrode 12 during the sustain discharge period. After stabilizing the sustain discharge by applying a voltage of crosswise, a voltage of about 150 or 180V around the sustain voltage is applied to the Y electrode 14 and the X electrode 12 alternately; The address electrode 32 selectively applies an address pulse to maintain the ground state (0V) in the reset period and the sustain discharge period, and selectively erase the charge in the display cells 36 that will not be turned on in the address period. A method of driving a plasma display panel of a selective erasure driving method, characterized in that. The selective erasure driving method according to claim 5, wherein the first, second, third, and fourth hours are set to the time before and after 70 ms, 20 ms, 10 ms and 50 ms, respectively. A method of driving a plasma display panel.