KR20020015822A - stacking verticality style for Monolithic Microwave Integrated Circuit - Google Patents

stacking verticality style for Monolithic Microwave Integrated Circuit Download PDF

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KR20020015822A
KR20020015822A KR1020000048941A KR20000048941A KR20020015822A KR 20020015822 A KR20020015822 A KR 20020015822A KR 1020000048941 A KR1020000048941 A KR 1020000048941A KR 20000048941 A KR20000048941 A KR 20000048941A KR 20020015822 A KR20020015822 A KR 20020015822A
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layer
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silicon wafer
integrated circuit
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KR100342818B1 (en
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윤태준
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곽정소
주식회사 케이이씨
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6683High-frequency adaptations for monolithic microwave integrated circuit [MMIC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Waveguides (AREA)

Abstract

PURPOSE: A vertically-stacked monolithic microwave integrated circuit is provided to reduce an occupying volume by vertically stacking silicon wafers on a circuit board, and to increase an operation frequency by fabricating the silicon wafer by using silicon-on-insulator(SOI). CONSTITUTION: A plurality of upper and lower silicon wafers are formed on and under an oxide layer. A plurality of upper and lower polysilicon layers are deposited on a partial upper surface of the upper silicon wafer and on the entire lower surface of the lower silicon wafer by a predetermined thickness. A barium strontium titanate(BST) layer composed of barium and strontium is deposited on the lower surface of the lower silicon wafer to prevent power consumption. An oxide layer is formed on the lower surface of the BST layer and on the upper polysilicon layer. Upper and lower metal layers are made of a metal material. Solder balls(16a,16b) are connected to the metal layers. The solder ball of the upper metal layer is interconnected by a wire, and the solder ball of the lower metal layer is directly interconnected. An electrical signal can be transferred according to a circuit pattern formed on the surface of the circuit board(18).

Description

수직적층형 모놀리식 마이크로웨이브 집적회로{stacking verticality style for Monolithic Microwave Integrated Circuit}Stacking verticality style for Monolithic Microwave Integrated Circuit

본 발명은 수직적층형 모놀리식 마이크로웨이브 집적회로에 관한 것으로서, 좀더 자세하게는 회로기판상에 상하 수직으로 실리콘웨이퍼를 적층하여 부피를 줄이게 되므로 대용량의 원칩 설계가 가능하도록 하고 SOI를 이용하여 실리콘웨이퍼를 제작하게 되므로 동작주파수가 향상과 전력소비를 줄일 수 있도록 있는 수직적층형 모놀리식 마이크로웨이브 집적회로에 관한 것이다.The present invention relates to a vertically stacked monolithic microwave integrated circuit, and more particularly, by stacking silicon wafers vertically and vertically on a circuit board to reduce the volume, to enable a large-capacity one-chip design and to use a silicon wafer using SOI. The present invention relates to a vertically stacked monolithic microwave integrated circuit capable of improving operating frequency and reducing power consumption.

일반적인 레이더의 주된 전자소자로는 수신기(receiver)와 송신기(transmitter)를 들 수 있다. 레이더 수신부는 마이크로파 입력신호를 받아서 IF 단으로 변환하는 RF단과 저주파에서 신호처리를 하는 IF 단으로 구성되어 있다. 이중 RF단은 저잡음 증폭기(Low Noise Amplifier : LNA), 혼합기(Mixer), 전압조절 발진기(Voltage-Controlled Oscillator : VCO)등으로 구성되어 있으며, 기존 마이크로파 회로들은 하이브리드 형태가 주를 이루고 있었다.The main electronic devices of the general radar include a receiver and a transmitter. The radar receiver consists of an RF stage that receives a microwave input signal and converts it into an IF stage, and an IF stage that performs signal processing at a low frequency. The RF stage consists of a low noise amplifier (LNA), a mixer, a voltage-controlled oscillator (VCO), and the conventional microwave circuits are mainly hybrid.

그러나 1980년대 들어 초고주파 반도체 기술의 급속한 발전에 힘입어 하이브리드 마이크로파 회로들이 점차 모놀리식 마이크로웨이브 집적회로들로 대체되기 시작하였다.In the 1980s, however, with the rapid development of microwave technology, hybrid microwave circuits were gradually replaced by monolithic microwave integrated circuits.

레이더 부품의 모놀리식 마이크로웨이브 집적회로화는 수신기부품에서 뿐만 아니라, 최근에는 송신기 부품에까지 파급되고 있다. 레이더용 트랜스미터(Transmitter)는 일반적으로 큰 출력을 요구하므로 과거에는 마그네트론(Magnetron), 크리스트론(Klystron), TWT(Travelling Wave Tube)등을 사용하여 왔으나 신뢰성에 문제가 있어 반도체를 이용한 SSPA(Solid State Power Amplifier) 의 사용이 늘고있는 추세이다. 1990년대 들어서는 SSPA역시 하이브리드 형태에서 모놀리식 마이크로웨이브 집적회로 형태로 활발하게 진행되고 있다.Monolithic microwave integrated circuitry of radar components has spread to not only receiver components but also transmitter components in recent years. Radar transmitters generally require large outputs, so in the past they have used magnetrons, cristrons, and traveling wave tubes (TWTs), but because of reliability problems, solid state SSPAs using semiconductors The use of power amplifiers is increasing. In the 1990s, SSPA is also actively progressing from hybrid to monolithic microwave integrated circuit.

이러한, 모놀리식 마이크로웨이브 집적회로(MMIC:Monolithic Microwave Integrated Circuit)는 화합물 반도체의 응용 부품으로서 이동통신기기 시장에 급격히 확대되면서, 고주파 특성이 우수하고, 신호크기에 따른 특성변화가 적으며, RF단의 여러 소자들을 단일 칩으로 집적 가능하게한 정보통신용 부품으로서 향후 가장 유망한 통신 부품중 하나로서 부상하고 있는 부품이다.The monolithic microwave integrated circuit (MMIC) is an application component of compound semiconductors, which is rapidly expanding in the mobile communication device market, and has excellent high frequency characteristics, little change in characteristics according to signal size, and RF. It is an information communication component that enables the integration of several devices in a single chip, and is one of the most promising communication components in the future.

모놀리식 마이크로웨이브 집적회로는 현재 레이더뿐만 아니라 위성통신 및 이동통신의 RF 부품으로 그 사용 영역이 넓어지고 있는 마이크로파 시스템의 핵심기술이다.Monolithic microwave integrated circuits are the core technology of microwave systems that are expanding their use as RF components for satellite and mobile communication as well as radar.

이러한 일반적인 모놀리식 마이크로웨이브 집적회로 제작 과정을 살펴보면 다음과 같다.The general process of manufacturing a monolithic microwave integrated circuit is as follows.

우선 캐패시터의 밑판으로 사용되는 첫 번째 금속을 기판위에 증착한다.First, the first metal used as the base plate of the capacitor is deposited on the substrate.

그 후 유전체로 사용될 Si3N4나, SiO2등을 PECVD (Plasma Enhanced Chemical Vapor Deposition)등의 방법을 이용하여 수천 앵스트롬의 얇은 두께로 증착한 후 캐패시터의 윗판으로 쓰이는 두 번째 금속을 증착한다. 마지막으로 윗판과 평면형 피드(feed)구조를 연결하기 위하여 3차원적 연결구조인 에어브리지(Airbridge)를 제작한다.After that, Si3N4, SiO 2, etc., to be used as a dielectric is deposited to a thin thickness of several thousand angstroms by using a PECVD (Plasma Enhanced Chemical Vapor Deposition) method, and then a second metal used as a top plate of the capacitor is deposited. Finally, to connect the top plate and the planar feed structure, a three-dimensional connection structure, Airbridge, is manufactured.

캐패시터뿐 아니라 기판의 위와 밑을 연결하는 비아홀(Via Hole), 인덕터, 저항 등도 이러한 반도체 집적회로 공정기술을 이용하여 능동 소자의 기판위에 제작한다.In addition to capacitors, via holes, inductors, and resistors that connect the top and bottom of the substrate are fabricated on the substrate of active devices using this semiconductor integrated circuit process technology.

우선 그 크기와 무게가 HMIC에 비하여 수십 배에서 수백배이상 작아지는 장점을 지닌다. 반도체 공정을 이용한 photolitho graphy의 해상도가 1(㎛)이하이므로 선폭 및 선간의 간격을 마이크로미터 단위로 작게 할 수 있다.First of all, its size and weight are smaller than dozens or hundreds of times smaller than HMIC. Since the resolution of the photolithography using the semiconductor process is less than 1 (µm), the line width and the spacing between the lines can be reduced in micrometers.

일 예로 마이크로스트립라인의 경우를 살펴보면 두께가 100(㎛)인 GaAs위에 50Ω의 특성 임피던스를 갖기 위한 라인의 선폭은 50(㎛) 정도로서 HMIC의 일반적인 경우보다도 훨씬 얇은 선폭이 모놀리식 마이크로웨이브 집적회로에서 사용된다.For example, in the case of the microstrip line, the line width of the line having a characteristic impedance of 50 에 on the GaAs having a thickness of 100 μm is about 50 μm, which is much thinner than the general case of the HMIC. Used in

선폭과 선 간격의 축소는 칩의 축소로 이어져 일반적인 모놀리식 마이크로웨이브 집적회로 저잡음 증폭기의 크기는 수(㎜2)정도이고 전력증폭기는 수십(㎜2) 정도로서 HMIC의 수십 분의 일에 불과하다. 휴대전화기 같은 경우 점차 경량화, 소량화 추세로 발전되고 있으므로 작은 칩 크기를 갖는 모놀리식 마이크로웨이브 집적회로의 수요가 늘어날 것이 예상된다.The reduction of line width and line spacing leads to chip reduction, and the size of a typical monolithic microwave integrated circuit low noise amplifier is about several millimeters (mm2) and about tens of millimeters (mm2) of power amplifier. . In the case of mobile phones, such as light weight and small amount is being developed, the demand for monolithic microwave integrated circuits with small chip size is expected to increase.

모놀리식 마이크로웨이브 집적회로는 모든 능동소자와 수동소자들이 하나의 기판위에서 다 구현된 회로형태를 지칭하는 것으로서, 첨부도면 도 1에서 보는 바와 같다.The monolithic microwave integrated circuit refers to a circuit form in which all active devices and passive devices are implemented on one substrate, as shown in FIG. 1.

첨부도면 도 1에서 보는 바와 같이 종래의 모놀리식 마이크로웨이브 집적회로는 하나의 회로기판(1)상에 실리콘웨이퍼(2)(8)를 좌우에 각각 연결하되, 상기 좌측 실리콘웨이퍼(2)주변에 폴리실리콘층(3)을 적층하여 금속재질의 상판(4)으로 둘러쌓은 후 상기 상판(4)에 솔더볼(5)과 와이어(6)를 본딩하여 능동소자가 형성되도록 하고 상기 능동소자의 우측에 회로기판과 면접촉되어 있는 실리콘웨이퍼 상단에 상기 와이어(6)를 접합하고 상면에 산화막과 금속판을 적층한 후 솔더볼과 와이어를 회로기판에 접합하여 수동소자가 이루어지도록 하여 마이크로파 회로 동작에 필요한 모든 RF소자를 구현할 수 있는 구성으로 이루어져있다.As shown in FIG. 1, in the conventional monolithic microwave integrated circuit, silicon wafers 2 and 8 are connected to left and right sides on one circuit board 1, and the left silicon wafer 2 is surrounded. The polysilicon layer (3) is laminated on the top plate (4) of metal material and then bonded to the solder ball (5) and the wire (6) on the top plate 4 to form an active element and the right side of the active element The wire 6 is bonded to the upper surface of the silicon wafer which is in surface contact with the circuit board, and the oxide film and the metal plate are laminated on the upper surface, and then the solder ball and the wire are bonded to the circuit board so that the passive element is made. It consists of a configuration that can implement an RF device.

그러나, 이러한 종래의 모놀리식 마이크로웨이브 집적회로는 하나의 기판상에 능동, 수동소자를 각각 개별적으로 수평적으로 연결하게 되므로 전체적인 부피가 증가하게 되므로 고밀도의 회로설계의 어려움과 구조설계단가가 상승하는 요인이 발생하며, 능동소자와 수동소자간에 형성된 거리만큼 와이어를 길게 연결해야되므로 와이어에 커패시커(capacitor)가 형성되어 전력소실과 주파수 특성을 저해하는 요인이 되는 문제점을 가지고 있다.However, these conventional monolithic microwave integrated circuits connect active and passive elements horizontally to each other individually on a single substrate, thereby increasing the overall volume, thereby increasing the difficulty of high-density circuit design and structural design cost. In this case, since a wire must be connected as long as the distance formed between the active element and the passive element, a capacitor is formed on the wire, which has a problem of degrading power loss and frequency characteristics.

본 발명은 이와 같은 종래의 제반 문제점을 해결하기 위기 위한 것으로서 그 목적은 회로기판상에 상하 수직으로 실리콘웨이퍼를 적층하여 부피를 줄이게 되므로 대용량의 원칩 설계가 가능하도록 하고 SOI를 이용하여 실리콘웨이퍼를 제작하게 되므로 동작주파수가 향상과 전력소비를 줄일 수 있도록 하는 데 있다.The present invention is intended to solve such problems in the related art, and its purpose is to stack silicon wafers vertically and vertically on a circuit board to reduce the volume, thereby enabling a large-capacity one-chip design and manufacturing silicon wafers using SOI. Therefore, the operating frequency is to improve and reduce the power consumption.

도 1은 종래의 수평형 모놀리식 마이크로웨이브 집적회로의 단면구성도이다.1 is a cross-sectional view of a conventional horizontal monolithic microwave integrated circuit.

도 2, 도 3,도 4,도 5,도 6은 본 발명의 실시예에 따른 수직적층형 모놀리식 마이크로웨이브 집적회로의 제조과정의 구성도이다.2, 3, 4, 5, and 6 are schematic diagrams of a manufacturing process of a vertically stacked monolithic microwave integrated circuit according to an exemplary embodiment of the present invention.

-도면의 주요부분에 대한 부호설명-Code descriptions for the main parts of the drawings

1,18;회로기판 2,11a,11b;실리콘웨이퍼1,18; circuit board 2, 11a, 11b; silicon wafer

3,13a,13b;폴리실리콘층 4;상판3,13a, 13b; polysilicon layer 4; top plate

5,16a,16b;솔더볼 6,17;와이어5,16a, 16b; Solder Ball 6,17; Wire

12;산화막층 14;비에스티층12; oxide layer 14; BESTI layer

15a,15b;금속막층15a, 15b; metal film layer

이하, 첨부된 도면에 의해 본 발명의 기술적 구성을 상세히 설명하면 다음과 같다.Hereinafter, the technical configuration of the present invention with reference to the accompanying drawings in detail.

본 발명은 모놀리식 마이크로웨이브 집적회로소자를 상하로 적층시키기 위한 구조에 관한 것으로서, 도2 내지 도 6에서 보는 바와 같이 중앙과 외부에 노출되는 상부나 하부에 일정두께의 판이 형성을 형성하여 외부의 이물질 유입을 방지함과 동시에 전기적인 신호 전달이 원활하게 이루어질 수 있도록 하는 산화막층(12)의 상부와 하단에 이온이 주입된 판막이 증착된 복수의 상하단 실리콘웨이퍼(11a)(11b)와, 상기 상단 실리콘웨이퍼(11a)의 상면에 일부분에 증착되도록 하고 하단 실리콘웨이퍼(11b)의 하면 전체에 일정 두께로 증착된 복수의 상하단 폴리실리콘층(13a)(13b)과, 상기 하단폴리실리콘(13b)층의 하면에 증착되어 전력손실이 방지될 수 있도록 바륨과 스트론륨을 혼합되어 층을 이루어 증착된 비에스티(BST;barium strontium titanate)층(14)과, 상기 비에스티층(14)의 저면과 상단 폴리실리콘층(13a)의 상면에 형성되어 이물질 유입을 방지함과 동시에 전기적인 신호가 상호 전달될 수 있도록 하는 산화막으로 층을 형성하거나 금속재질로 형성된 상하단의 금속막층(15a)(15b)과, 상기 금속막층(15a)(15b)에 연결되어 외부와의 전기적인 신호가 전달될 수 있도록 하는 솔더볼(16a)(16b)과, 상기 금속막층(15a)의 솔더볼(16a)간에 와이어(17)를 연결하고 금속막층(15b)의 솔더볼(16b)간에는 직접 연결되어 연결되도록 하여 표면에 형성된 회로패턴에 따라 전기적인 신호가 상호 전달될 수 있도록 하는 회로기판(18)이 연결되어 이루어진 구성을 갖는다.The present invention relates to a structure for stacking a monolithic microwave integrated circuit device up and down, as shown in Figures 2 to 6 a plate having a predetermined thickness formed on the top or bottom exposed to the center and the outside to form And a plurality of upper and lower silicon wafers 11a and 11b on which upper and lower portions of the oxide film layer 12 are plated with ions implanted thereon to prevent foreign substances from being introduced and to facilitate electrical signal transmission. A plurality of upper and lower polysilicon layers 13a and 13b deposited on a portion of the upper surface of the upper silicon wafer 11a and deposited to a predetermined thickness on the entire lower surface of the lower silicon wafer 11b and the lower polysilicon 13b. A barium strontium titanate (BST) layer 14 formed by mixing barium and strontium so as to be deposited on the lower surface of the layer to prevent power loss; Upper and lower metal film layers formed of an oxide film formed on the bottom surface of the tee layer 14 and the top surface of the upper polysilicon layer 13a to prevent foreign substances from being introduced and to allow electrical signals to be transferred to each other. 15a, 15b, solder balls 16a and 16b connected to the metal film layers 15a and 15b to allow an electrical signal to be transmitted to the outside, and solder balls of the metal film layer 15a. The circuit board 18 connects the wires 17 between the wires 16a and the direct connection between the solder balls 16b of the metal film layer 15b so that electrical signals can be transferred to each other according to a circuit pattern formed on the surface. It is connected and made up.

본 발명의 모놀리식 마이크로웨이브 집적회로소자를 상하로 적층시키기 위한 제조방법에 관한 것으로서, 도 2 내지 도 6에서 보는 바와 같이 중앙과 외부에 노출되는 상부나 하부에 일정두께의 판이 형성을 형성하여 외부의 이물질 유입을 방지함과 동시에 전기적인 신호 전달이 원활하게 이루어질 수 있도록 하는 산화막층(12)의 상부와 하단에 각각 이온이 주입된 판막 복수의 상하단 실리콘웨이퍼(11a)(11b)가 증착하고, 상기 상단 실리콘웨이퍼(11a)의 상면에 일부분에 증착되도록 하고 하단 실리콘웨이퍼(11b)의 하면 전체에 일정 두께의 복수 상하단 폴리실리콘층(13a)(13b)이 증착될 수 있도록 하며, 상기 하단 폴리실리콘(13b)층의 하면에 증착되어 전력손실을 억제할 수 있도록 바륨과 스트론륨을 혼합되어 층을 이루는 비에스티(BST;barium strontium titanate)층(14)이 적층될 수 있도록 하고, 상기 비에스티층(14)의 저면과 상단 폴리실리콘층(13a)의 상면에 산화막이나 금속재질로 형성된 상하단의 금속막층(15a)(15b)이 증착될 수 있도록 하며, 상기 금속막층(15a)(15b)에 외부와의 전기적인 신호가 전달될 수 있도록 하는 솔더볼(16)이 접착될 수 있도록 하고, 상기 금속막층(15a)의 솔더볼간에 와이어(17)를 연결하여 안착시키고 금속막층(15b)의 솔더볼 표면이 안착되도록 하여 표면에 형성된 회로패턴에 따라 전기적인 신호가 상호 전달될 수 있도록 회로기판(18)에 연결하는 제조방법의 구성을 갖는다.A method for manufacturing a monolithic microwave integrated circuit device of the present invention is stacked up and down, as shown in Figures 2 to 6 by forming a plate having a predetermined thickness on the upper or lower portion exposed to the center and the outside A plurality of upper and lower silicon wafers 11a and 11b in which ions are injected are deposited on the upper and lower ends of the oxide layer 12 to prevent external foreign substances from being introduced and to facilitate electrical signal transmission. To deposit a portion on the upper surface of the upper silicon wafer (11a) and to deposit a plurality of upper and lower polysilicon layers (13a, 13b) of a predetermined thickness on the entire lower surface of the lower silicon wafer (11b), the lower poly A barium strontium titanate (BST) layer formed by mixing barium and strontium to form a layer to be deposited on the bottom surface of the silicon 13b layer to suppress power loss. 14) may be stacked, and upper and lower metal film layers 15a and 15b formed of an oxide film or a metal material may be deposited on the bottom surface of the BST layer 14 and the top surface of the upper polysilicon layer 13a. The solder ball 16 may be bonded to the metal film layers 15a and 15b to allow an electrical signal to be transmitted to the outside, and the wires 17 may be connected between the solder balls of the metal film layer 15a. By mounting the solder ball surface of the metal film layer (15b) to have a configuration of the manufacturing method for connecting to the circuit board 18 so that the electrical signal can be transferred to each other according to the circuit pattern formed on the surface.

이와 같이 구성하는 본 발명의 작용효과를 상세히 설명하면 다음과 같다.Referring to the effects of the present invention configured in this way in detail as follows.

본 발명은 모놀리식 마이크로외이브 집적회로의 능동소자와 수동소자를 상하로 적층시키기 위한 것으로서, 도 2a에서와 같이 이온을 주입하여 형성된 두 개의 실리콘웨이퍼(11a)(11b)를 산화물로 형성된 산화막층(12)이 상단과 하단에 증착되도록 하며 특히 외부에 노출되는 부위는 외부의 이물질 유입을 방지되면서 전기적인 신호 전달이 원활하게 이루어질 수 있도록 적층하게 된다.The present invention is to stack the active element and passive element of the monolithic micro external integrated circuit up and down, and as shown in Figure 2a, two silicon wafers (11a) (11b) formed by implanting ions as an oxide film formed of an oxide The layer 12 is deposited on the top and the bottom, and particularly, the parts exposed to the outside are laminated to prevent the inflow of foreign substances while smoothly transmitting the electrical signals.

실리콘웨이퍼(11a)(11b)는 산화막층(12)와 수직으로 적층되어 접착될 수 있도록 하여 산화막층(12)을 통해 캐리어 전자가 상하로 이동하여 확산되는 것을 방지하고 SOI(Silicon on insulator)의 이용으로 동작주파수를 상승과 저전력의 효과를 갖는다.The silicon wafers 11a and 11b may be stacked vertically and bonded to the oxide layer 12 to prevent carrier electrons from moving upward and downward through the oxide layer 12 and to diffuse the silicon on insulator (SOI). By using it has the effect of increasing the operating frequency and low power.

이후에, 상하 실리콘웨이퍼(11a)(11b)는 도 2b내지 도 2c에서 보듯이 상하단 실리콘웨이퍼(11a)(11b)의 각 상하단면에 폴리실리콘(13a)(13b)를 적어도 1내지 2(㎛)의 두께로 증착시키고 하단의 폴리실리콘(13b)에 바륨과 스트륜이 혼합하여 막을 형성시킨 비에스티층(14)을 적어도 1(㎛)이하로 적층하여 전력손실을 방지하게 되는 것이다.Thereafter, the upper and lower silicon wafers 11a and 11b are formed of at least 1 to 2 micrometers of polysilicon 13a and 13b on the upper and lower end surfaces of the upper and lower silicon wafers 11a and 11b, as shown in FIGS. 2B and 2C. ) To prevent the loss of power by stacking the BEST layer 14 having a thickness of 2) and forming a film by mixing barium and a streak on the lower polysilicon 13b.

한편 실리콘웨이퍼(11a)(11b)는 외부와 전기적인 신호를 상호 전달하기 위해 도 2d에서 보듯이 상하단 실리콘 웨이퍼(11a)(11b)에 각각 산화막이나 금속재질의 금속막층(15a)(15b)을 증착시켜 실리콘웨이퍼(11a)(11b)와 외부의 전기장치간에 전기신호가 상호 전달될 수 있도록 하는 것이다.On the other hand, the silicon wafers 11a and 11b are formed on the upper and lower silicon wafers 11a and 11b, respectively, by the oxide film or the metal film layers 15a and 15b, respectively, to transfer electrical signals to the outside. By depositing, electrical signals can be transferred between the silicon wafers 11a and 11b and the external electric devices.

마지막으로 실리콘웨이퍼(11a)(11b)는 회로기판(18)과 전기적인 신호를 상호 전달하기 위해 상단 실리콘웨이퍼(11a)에 증착시킨 금속막층(15a)에는 와이어(17)를 본딩하여 회로기판(18)과 전기적인 신호가 상호 전달될 수 있도록 솔더볼(16a)을 본딩하고, 하단 실리콘웨이퍼(11b)는 회로기판(18)과 직접 표면에 접착될 수 있도록 솔더볼(16b)을 본딩하여 전기적인 신호 상호 전달될 수 있도록 하므로서 회로기판에 상하로 적층된 실리콘웨이퍼의 안착면적을 줄이게 되므로 원칩화를 이루어수 있으며 실리콘웨이퍼를 SOI로 이용하게 되므로 동작주파수가 상승하고 저전력으로 동작시킬 수 있는 것이다.Finally, the silicon wafers 11a and 11b bond the wires 17 to the metal film layer 15a deposited on the upper silicon wafer 11a in order to transfer electrical signals to the circuit board 18. 18) and the solder ball (16a) to bond the electrical signal to each other, the lower silicon wafer (11b) is bonded to the solder ball (16b) to be directly bonded to the circuit board 18, the electrical signal Since it can be transferred to each other to reduce the seating area of the silicon wafer stacked on the circuit board up and down, it can be made in one chip, and the silicon wafer is used as the SOI, so the operating frequency is increased and can be operated at low power.

이와 같이 작용하는 본 발명은 회로기판상에 상하 수직으로 실리콘웨이퍼를 적층하여 부피를 줄이게 되므로 대용량의 원칩 설계가 가능하도록 하고 SOI를 이용하여 실리콘웨이퍼를 제작하게 되므로 동작주파수가 향상과 전력소비를 줄일 수 있도록 있는 효과가 있다.The present invention, which acts as above, reduces the volume by stacking silicon wafers vertically and vertically on a circuit board, thereby enabling a large-capacity one-chip design and manufacturing silicon wafers using SOI, thereby improving operating frequency and reducing power consumption. It has an effect so that.

Claims (2)

고집적 모놀리식 마이크로웨이브 집적회로에 있어서, 중앙과 외부에 노출되는 상부나 하부에 일정두께의 판이 형성을 형성하여 외부의 이물질 유입을 방지함과 동시에 전기적인 신호 전달이 원활하게 이루어질 수 있도록 하는 산화막층(12)의 상부와 하단에 이온이 주입된 판막이 증착된 복수의 상하단 실리콘웨이퍼(11a)(11b)와, 상기 상단 실리콘웨이퍼(11a)의 상면에 일부분에 증착되도록 하고 하단 실리콘웨이퍼(11b)의 하면 전체에 일정 두께로 증착된 복수의 상하단 폴리실리콘층(13a)(13b)과, 상기 하단폴리실리콘(13b)층의 하면에 증착되어 전력손실이 방지될 수 있도록 바륨과 스트론륨을 혼합되어 층을 이루어 증착된 비에스티(BST;barium strontium titanate)층(14)과, 상기 비에스티층(14)의 저면과 상단 폴리실리콘층(13a)의 상면에 형성되어 이물질 유입을 방지함과 동시에 전기적인 신호가 상호 전달될 수 있도록 하는 산화막으로 층을 형성하거나 금속재질로 형성된 상하단의 금속막층(15a)(15b)과, 상기 금속막층(15a)(15b)에 연결되어 외부와의 전기적인 신호가 전달될 수 있도록 하는 솔더볼(16)과, 상기 금속막층(15a)의 솔더볼간에 와이어를 연결하고 금속막층(15b)의 솔더볼간에는 직접 연결되어 연결되도록 하여 표면에 형성된 회로패턴에 따라 전기적인 신호가 상호 전달될 수 있도록 하는 회로기판(18)이 연결되어 이루어진 수직적층형 모놀리식 마이크로웨이브 집적회로 구조.In the highly integrated monolithic microwave integrated circuit, an oxide film which forms a plate having a predetermined thickness on the upper part or the lower part exposed to the center and the outside to prevent the inflow of foreign substances from the outside and at the same time facilitate the electrical signal transmission. A plurality of upper and lower silicon wafers 11a and 11b on which upper and lower plates of the layer 12 are implanted are deposited, and a lower silicon wafer 11b is deposited on a portion of the upper surface of the upper silicon wafer 11a. ) Is deposited on the bottom and bottom of the plurality of upper and lower polysilicon layers (13a, 13b) and the lower polysilicon (13b) layer is deposited on the entire lower surface of the barium and strontium to prevent power loss BST (barium strontium titanate) layer 14, which is mixed and deposited as a layer, is formed on the bottom surface of the BST layer 14 and the upper surface of the upper polysilicon layer 13a to prevent foreign substances from entering. At the same time, a layer of an oxide film that allows electrical signals to be transferred to each other or a metal material layer 15a and 15b at upper and lower ends formed of a metal material and connected to the metal film layers 15a and 15b to be electrically connected to the outside. The wires are connected between the solder balls 16 and the solder balls of the metal layer 15a to directly transmit signals, and the solder balls 16 are directly connected to the solder balls of the metal layer 15b. A vertically stacked monolithic microwave integrated circuit structure in which circuit boards (18) are connected to each other so that signals can be transmitted to each other. 모놀리식 마이크로웨이브 집적회로소자를 상하로 적층시키기 위한 제조방법에 있어서, 중앙과 외부에 노출되는 상부나 하부에 일정두께의 판이 형성을 형성하여 외부의 이물질 유입을 방지함과 동시에 전기적인 신호 전달이 원활하게 이루어질 수 있도록 하는 산화막층(12)의 상부와 하단에 이온이 주입된 판막 복수의 상하단 실리콘웨이퍼(11a)(11b)가 증착하고, 상기 상단 실리콘웨이퍼(11a)의 상면에 일부분에 증착되도록 하고 하단 실리콘웨이퍼(11b)의 하면 전체에 일정 두께의 복수 상하단 폴리실리콘층(13a)(13b)이 증착될 수 있도록 하며, 상기 하단 폴리실리콘(13b)층의 하면에 증착되어 전력손실을 억제할 수 있도록 바륨과 스트론륨을 혼합되어 층을 이루는 비에스티(BST;barium strontium titanate)층(14)이 적층될 수 있도록 하고, 상기 비에스티층(14)의 저면과 상단 폴리실리콘층(13a)의 상면에 산화막이나 금속재질로 형성된 상하단의 금속막층(15a)(15b)이 증착될 수 있도록 하며, 상기 금속막층(15a)(15b)에 외부와의 전기적인 신호가 전달될 수 있도록 하는 솔더볼(16)이 접착될 수 있도록 하고, 상기 금속막층(15a)의 솔더볼간에 와이어(17)를 연결하여 안착시키고 금속막층(15b)의 솔더볼 표면이 안착되도록 하여 표면에 형성된 회로패턴에 따라 전기적인 신호가 상호 전달될 수 있도록 회로기판(18)에 연결하여 이루어진 수직적층형 모놀리식 마이크로웨이브 집적회로 제조방법.In the manufacturing method for stacking a monolithic microwave integrated circuit device up and down, a plate having a predetermined thickness is formed on the top or bottom exposed to the center and the outside to prevent the inflow of foreign matters and at the same time to transmit the electrical signal A plurality of upper and lower silicon wafers 11a and 11b in which ions are implanted are deposited on upper and lower portions of the oxide layer 12 so as to be smoothly formed, and deposited on a portion of an upper surface of the upper silicon wafer 11a. And a plurality of upper and lower polysilicon layers 13a and 13b having a predetermined thickness are deposited on the entire lower surface of the lower silicon wafer 11b, and is deposited on the lower surface of the lower polysilicon 13b layer to suppress power loss. The barium strontium titanate (BST) layer 14 may be stacked by mixing barium and strontium, and the bottom surface of the BST layer 14 may be stacked. The upper and lower metal film layers 15a and 15b formed of an oxide film or a metal material may be deposited on the upper surface of the upper polysilicon layer 13a, and an electrical signal may be applied to the metal film layers 15a and 15b. A circuit formed on the surface to allow the solder ball 16 to be bonded to be transferred, the wire 17 between the solder ball of the metal film layer 15a to be seated and the solder ball surface of the metal film layer 15b to be seated. Method for manufacturing a vertically stacked monolithic microwave integrated circuit formed by connecting to a circuit board (18) so that electrical signals can be transmitted to each other according to the pattern.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9257947B2 (en) 2013-09-27 2016-02-09 Mitsubishi Electric Corporation Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9257947B2 (en) 2013-09-27 2016-02-09 Mitsubishi Electric Corporation Semiconductor device

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