JP2768873B2 - Microwave integrated circuit and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microwave integrated circuit that can be miniaturized.

[0002]

2. Description of the Related Art FIG. 6 is a perspective view showing a conventional microwave integrated circuit (hereinafter referred to as MIC).
FIG. 6D shows a manufacturing process for manufacturing the MIC.
FIG. 7 is a sectional view taken along line BB of FIG. In the figure, 1 is a carrier made of a conductor, 8 is a solder, 12 is a back metal, 3 is an alumina substrate, 4 is a microstrip line, 6 is a chip capacitor, 7 is an FET, 9 is an Au wire, and 10 is a ground (GND). ) Is a conductive adhesive for bonding the chip capacitor 6 and the FET 7.

Next, the manufacturing process will be described. FIG.
As shown in (a), the metal used for the microstrip line 4, for example, Cr / Au is provided on both surfaces of the alumina substrate 3.
Is formed, and the microstrip line 4 having a desired pattern on the surface is obtained by a photoetching technique. The metal deposited on the back surface becomes the back metal 12. Then, FIG.
As shown in FIG. 7B, the Au ribbon 10 is thermocompression-bonded as shown in FIG. 7B in order to establish conduction between a part of the microstrip line 4 and the back metal 12, that is, to ground.

Then, as shown in FIG. 7C, the back metal 12 of the alumina substrate 3 and the Au ribbon 10 are soldered on the carrier 1 (for example, CuW) by soldering.
Next, as shown in FIG.
The chip capacitor 6 for grounding one electrode on the ET 7 and the microstrip line 4 is connected to the conductive adhesive 1 respectively.
7. Die bond with 7. Next, an Au wire 9 is wire-bonded so as to connect each electrode of the FET 7 to a desired position of the microstrip line 4.

The above description is an example of the structure and manufacturing method of a general MIC. When the thickness of the alumina substrate 3 is set to a standard 635 μm dielectric constant of 10, a 50 Ω line width which is a basic design is about 600 μm. Becomes FIG.
If the area of the alumina substrate 3 is large at the time of soldering in (c),
Voids (vacancies) 18 shown in the figure may be generated, and the voids 18 expand during a subsequent thermal process, and cracks 19 are generated in the alumina substrate 3 as shown in FIG. The line 4 may be disconnected.

[0006]

Since the conventional microwave integrated circuit is constructed as described above, the 50Ω line width is as wide as 600 μm, which hinders miniaturization. Thus, if the thickness of the alumina substrate 3 is set to 100 μm, the 50Ω line width becomes about 90 μm, which can be downsized. However, since the substrate is thin, substrate cracking occurs frequently in substrate handling in the manufacturing process, and the yield is remarkably deteriorated. Although the chip capacitor 6 is used for the bias circuit, the chip size is large,
There is a problem in reducing the size of the device.

Further, the chip capacitor 6 and the FET 7
Since the microstrip line 4 is routed to the end face of the alumina substrate 3 and the Au ribbon 10 is connected to the back metal 12 in order to ground the ground, an extra line length is formed up to the ground plane and parasitic impedance is generated. This causes a characteristic deterioration. In addition, voids 18 may be generated during soldering of the alumina substrate 3, and the voids 18 expand due to a subsequent heat process, and cracks 19
And the microstrip line 4 is disconnected.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a microwave integrated circuit which can be miniaturized, and which has high yield and high reliability, and a method of manufacturing the same. And

[0009]

According to a first aspect of the present invention, there is provided a microwave integrated circuit comprising: a carrier made of a conductor; and a film formed on the carrier and partially implanted or ion-expanded.
Dispersion to form an ion-implanted layer with a predetermined dielectric constant.
Both are insulating substrates with via holes formed in place
And a predetermined pattern on the insulating substrate and the ion-implanted layer.
Microstrip line formed by
The micro-hole formed in the via hole of the substrate.
Via holes that connect the stripline to the carrier
And an electrode .

According to a second aspect of the present invention, there is provided a method of manufacturing a microwave integrated circuit, comprising the steps of: forming an insulating substrate on a carrier made of a conductor;
A film is formed, and ion implantation or ion expansion is performed on a part of the insulating substrate.
To form an ion-implanted layer having a predetermined dielectric constant,
A mask is formed on the insulating substrate and the ion-implanted layer in a predetermined pattern.
Form a cross-strip line and place it on the insulating substrate
A via hole is formed in the
Via that grounds the cross strip line to the carrier
A hole electrode is formed.

[0011]

Method for producing a microwave integrated circuit in the invention of microwave integrated circuits and claim 2 in [action] The invention of claim 1, for forming directly the insulating substrate on a carrier, Mai
Microwave integration with a narrow cross-trip line width
The circuit can be miniaturized, and even if the substrate is thin,
Each substrate can be handled, so substrates can be
The yield is improved without cracking. Further soldering of the board
Substrate cracks due to void expansion
And high reliability can be obtained. Ma
MIM capacitors replace conventional chip capacitors
To reduce the size of the capacitor
As a result, microwave integrated circuits can be miniaturized.
Can be. In addition, the ion-implanted layer has physical properties
As a result, the area of the MIM capacitor can be reduced.
Alternatively, the capacitance value can be set arbitrarily. In addition,
Au ribbon and chip conditioner for back metal and ground
Since no sensors are required, the number of parts and processes can be reduced.
It becomes possible and the price can be reduced. In addition, vias
A hole is formed and a micro strip is formed in this via hole.
To form a via hole electrode that connects the loop to the carrier.
Therefore, there is no parasitic impedance due to the conventional grounding method.
Thus, the performance of the circuit can be improved.

[0012]

[Embodiment 1] An embodiment of the present invention will be described below with reference to the drawings. FIG.
In the drawings, 1 is a carrier, 2 is an insulating substrate formed on the carrier 1, and in this embodiment, an SiO ₂ substrate 2 is used. Reference numeral 5 denotes a carrier 1 using the SiO ₂ substrate 2 as an insulating layer.
, A lower electrode, 5a are upper electrodes thereof, 11a and 11b are via holes provided in the SiO ₂ substrate 2, and 12 is a via hole electrode for grounding the carrier 1. Incidentally, 4, 7, and 9 correspond to the same reference numerals in FIG.

FIGS. 2A to 2D are cross-sectional views taken along the line AA of FIG. 1 showing the MIC manufacturing process. In FIG. 2, 14
Is a resist provided on the SiO ₂ substrate 2, 15 is ion implantation for modifying a part of the SiO ₂ substrate 2, 16 is ion implantation selectively by the ion implantation 15 and the resist 14 to modify the SiO ₂ substrate 2 This is the ion-implanted layer.

Next, the manufacturing process will be described. FIG.
First, on a carrier 1 (for example, CuW) shown in FIG.
The O ₂ substrate 2 is, for example, 30 μm
m to form a film. Next, a resist 14 is formed in a desired pattern, and high-energy ion implantation 15 is selectively performed using the resist 14 as a mask as shown in the figure. For example, phosphorus is used as the ion source, and the amount of ion implantation is arbitrary. Through the above process, the ion implantation layer 16 is formed. Thereafter, heat treatment (annealing) is performed to remove the resist 14 and activate the ion implantation layer 16. The heat-treated ion-implanted layer 16 becomes phosphorus glass and has a higher dielectric constant than the SiO ₂ substrate 2.

[0015] Then, as shown in FIG. ₂ (b), SiO 2
For example, a Cr / Au film is formed on the substrate 2 and the ion-implanted layer 16, and the microstrip line 4 having a desired pattern is obtained by a photo-etching technique. The pattern on the ion implantation layer 16 in the obtained microstrip line 4 is the upper electrode 5a of the MIM capacitor 5 as shown in FIG.
Becomes The 50Ω line width of the microstrip line 4 obtained by the above process is about 60 μm when the relative permittivity of the SiO ₂ substrate 2 is εr = 4 and the substrate thickness is 30 μm, which is 1/10 of 600 μm of the conventional MIC. Therefore, the size can be considerably reduced due to the pattern design.

Next, as shown in FIG. 2C, via holes 11a and 11b are formed at desired locations on the SiO ₂ substrate 2 using, for example, a buffered hydrofluoric acid solution. Next, a via-hole electrode 12 is formed at the location of the via-hole 11a by, for example, Ti / Au by a sputter deposition method, and a part of the microstrip line 4 is grounded. Conventionally, a grounding pattern was routed to the edge of the substrate and grounded with an Au ribbon. However, in this embodiment, since the thickness of the SiO ₂ substrate 2 is thin,
Via holes 11a and 11b are easy to make and FET
7, the ground can be taken so that the impedance is minimized, and the performance of the FET 7 can be sufficiently brought out.
Next, as shown in FIG. 2D, the FET 7 is soldered 8 at the position of the via hole 11b which is the opening of the SiO ₂ substrate 2.
Is soldered to the carrier 1. Next, desired electrodes of the microstrip line 4 and the FET 7 are connected to the Au wire 9.
Wire bonding.

As described above, according to the first embodiment, Si
Since the O ₂ substrate 2 is formed directly on the carrier 1, there is no need to solder the substrate as in the prior art, and therefore there is no risk of the substrate crack 19 or the microstrip line 4 being broken by voids (vacancies) 18. Furthermore, since the SiO ₂ substrate 2 is formed directly on the carrier 1, the microstrip
Line width can be reduced to about 1/10 of conventional
Ultra-small microwave integrated circuit due to design of wave circuit pattern
Can be of, and without concern that the substrate is divided by the substrate handling thinner even the manufacturing process of the substrate thickness, it can be produced in high yield. Further, since the FET 7 is directly soldered to the carrier 1, the heat generated at the junction of the FET 7 to the carrier 1 through the alumina substrate 3 can be directly radiated to the carrier 1. Can be pulled out enough. Further, Si to carrier 1
The soldering of the O ₂ substrate 2 is unnecessary, and the chip capacitor for grounding one end and the Au ribbon 10 for grounding the FET 7 are also unnecessary, so that the number of parts and the number of manufacturing steps can be reduced. .

Embodiment 2 FIG. In the first embodiment, the plasma CVD method is used to form the SiO ₂ substrate 2 on the carrier 1. However, a sputter deposition method, an ion plating deposition method, or a printing and firing method of a glass paste may be used.

In the first embodiment, the substrate material is SiO.
_{Although 2} was used, as shown in FIG. 3, another inorganic insulating material 20 such as silicon nitride, silicon oxynitride, or a diamond thin film may be used. Alternatively, as shown in FIG. 4, an organic insulating material 21 such as a fluororesin or an epoxy resin may be used.

Embodiment 3 FIG. In Example 1 described above, ion implantation 15 of phosphorus was performed with high energy selectively at a desired location on the SiO ₂ substrate 2 to obtain an ion implantation layer 16 (modified layer), which was used as an insulating layer of the MIM capacitor 5. Boron, lead, or the like may be used as the ion source of the ion implantation 15.

Embodiment 4 FIG. In Example 1 described above, in order to obtain the insulating layer of the MIM capacitor 5, a part of the SiO ₂ substrate 2 was ion-implanted 15 and modified, but as shown in FIG. May be used. Note that in FIG.
2 is an ion diffusion source and 23 is an ion diffusion layer.

Embodiment 5 FIG. In the first embodiment, when forming the via holes 11a and 11b, a wet etching method using a buffered hydrofluoric acid solution is employed, but a dry etching method such as plasma etching or reactive etching may be used. Also,
Although the via-hole electrode 12 is formed by the sputter etching method, an electric field or an electroless plating method may be used.

[0023]

As described above, according to the first aspect of the present invention , a carrier made of a conductor and a film formed on the carrier are formed.
And perform ion implantation or ion diffusion on a part to
An ion-implanted layer of electric conductivity is formed, and
An insulating substrate having an ear hole formed thereon and
Formed in a predetermined pattern on the ion-implanted layer
The strip line and the via formed in the insulating substrate
Grounded microstrip line to the carrier
Because it was configured to have an earhole electrode, the microphone
Loss strip line width can be reduced to about 1/10
Microwave integration on the microwave circuit pattern design
The circuit can be miniaturized, and even if the substrate is thin,
Each substrate can be handled, so substrates can be
The yield is improved without cracking. Further soldering of the board
Substrate cracks due to void expansion
And high reliability can be obtained. Ma
Also, instead of a conventional chip capacitor,
Part of lip line is upper electrode, substrate is insulating layer, carrier
MIM capacitor with the lower electrode also serving as ground
Can reduce the size of the capacitor.
As a result, microwave integrated circuits can be made smaller.
Wear. Also, change the physical properties of the ion-implanted layer to an arbitrary dielectric constant.
As a result, the area or volume of the MIM capacitor
The quantity value can be set arbitrarily. In addition, career
There is no need to solder the insulating board, and the back
No need for ground, Au ribbon for grounding and chip capacitors
Therefore, the number of parts and the number of processes can be reduced.
This has the effect of reducing costs. In addition, vias
A hole is formed and a micro strip is formed in this via hole.
To form a via hole electrode that connects the loop to the carrier.
Therefore, there is no parasitic impedance due to the conventional grounding method.
Thus, there is an effect that the performance of the circuit can be improved.

According to the second aspect of the present invention, the conductive material
An insulating substrate is formed on a carrier made of
Predetermined permittivity by performing ion implantation or ion diffusion on a part
Forming an ion-implanted layer on the insulating substrate and the ion-implanted layer.
Microstrip line with a predetermined pattern on the
Forming and forming via holes at predetermined positions on the insulating substrate
Insert the microstrip line into the via hole
Form a via hole electrode to be grounded to the carrier.
As in the first aspect of the present invention, the micro
Wave integrated circuits can be miniaturized and
And high reliability can be achieved.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG. 1 showing the manufacturing process of the first embodiment.

FIG. 3 is a side sectional view showing another embodiment of the present invention.

FIG. 4 is a side sectional view showing another embodiment of the present invention.

FIG. 5 is a side sectional view showing another embodiment of the present invention.

FIG. 6 is a perspective view of a conventional microwave integrated circuit.

FIG. 7 is a sectional view taken along line BB of FIG. 6 showing a conventional manufacturing process.

[Explanation of symbols]

Reference Signs List 1 carrier 2 SiO ₂ substrate (insulating substrate) 4 microstrip line 5a upper electrode (microstrip line) 5 MIM capacitors 11a and 11b via hole 12 via hole electrode 15 ion implantation 16 ion implantation layer

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Claims (2)

(57) [Claims] 1. A carrier made of a conductor, and a film formed on the carrier and subjected to ion implantation or ion diffusion to a part thereof.
As a result, an ion implantation layer having a predetermined dielectric constant is formed,
An insulating substrate having via holes formed at predetermined positions,
Form in a predetermined pattern on the insulating substrate and on the ion-implanted layer
Microstrip line formed on the insulating substrate
The microstrip formed in the via hole
And a via-hole electrode for grounding the loop to the carrier . 2. A forming an insulating substrate on a carrier made of conductive material, by ion implantation or ion diffusion in a part of the insulating substrate to form an ion implantation layer of predetermined dielectric constant, the insulating substrate And a predetermined pattern on the ion-implanted layer.
Form a cross-strip line and place it on the insulating substrate
A via hole is formed in the
Via that grounds the cross strip line to the carrier
A method for manufacturing a microwave integrated circuit in which a hole electrode is formed.