CN108400123A - Heterogeneous integrated radio frequency system of wafer scale and preparation method thereof - Google Patents
Heterogeneous integrated radio frequency system of wafer scale and preparation method thereof Download PDFInfo
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- CN108400123A CN108400123A CN201810186672.4A CN201810186672A CN108400123A CN 108400123 A CN108400123 A CN 108400123A CN 201810186672 A CN201810186672 A CN 201810186672A CN 108400123 A CN108400123 A CN 108400123A
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- H—ELECTRICITY
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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Abstract
The present invention relates to a kind of heterogeneous integrated radio frequency system of wafer scale and production methods, include at least the first substrate, the second substrate, insulating bond layer, at least two chips；Wherein：Second substrate, insulating bond layer, at least two chips are set between the first substrate, the second substrate, include the first chip being connect with first substrate and the second chip for being connect with second substrate；At least one through-hole is provided on the insulating bond layer, the through-hole side wall is coated with conductive coating；One at least two chip connect with the first substrate, another at least two chips is connect with the second substrate, and at least two chips are electrically connected by the through-hole；Bonded layer align material between wafer is provided on first substrate and/or the second substrate；The support of bonded layer align material connects first substrate and second substrate between the wafer.The embodiment of the present invention, effective lifting system integrated level realize miniaturization target.
Description
Technical field
The invention belongs to microelectronics technologies, and in particular to a kind of heterogeneous integrated radio frequency system of wafer scale and its making side
Method.
Background technology
With the continuous development of semiconductor chip manufacturing technology and electronic system, miniaturization, multi-functional, high frequency and high speed
Operation and the requirements such as low cost be gradually evolved into future communication systems, space and military system application, high-resolution video camera and
Object is paid close attention in the applications such as sensor and car radar.
Compound semiconductor materials has its exclusive advantage, and the semiconductor devices to be manufactured with compound similarly has
There is its unique performance.In order to further enhance the overall performance of system, people are according to the function of required device, specific selection
Manufacture the best substrate of device.Such as silicon (Si) is always the leading material in semiconductor technology, in circuit function, is integrated
There is great advantage in terms of degree, cost；The high speed of second generation semi-conducting material GaAs (GaAs)；Indium phosphide (InP) is because of it
Have the characteristics that high frequency, high-gain and high power, and is widely used in millimeter wave and submillimeter wave frequency range；And have broad stopband,
High breakdown field strength and high-power third generation compound semiconductor materials gallium nitride (GaN) etc..The device of each substrate manufacture exists
It is different from its processing technology step, a kind of substrate material can not be processed using different processing technologys, therefore in list
In a system mostly complete system is combined into gold thread bonding pattern using the semiconductor chip with various substrates material.This
The system area of sample manufacture is huge, is unfavorable for miniaturization.
The development of current semiconductor manufacturing and encapsulation technology can be by the semiconductor active with different function
Device and passive device transverse direction same layer are integrated on a single substrate, and the relevant technologies such as application short distance interconnection bonding can obtain
Than conventional printed circuit performance higher and more dense circuit.In recent years use laminated multi-chip integrated technology, cause circuit and
System performance, which further obtains, to be promoted and expands to working frequency close to 100GHz or so.But in laminated multi-chip integrated technology
In, because various devices are cross growths, and due to machining accuracy problem, can cause among each device can there are several micro-
Rice increases the area occupied and volume of system to more than ten microns of spacing.Meanwhile further increasing with frequency, it is multiple
Bonding line internal loss and ghost effect between substrate chip also become more serious, it is difficult to overcome.Therefore heterogeneous integrated technology quilt
It proposes to be used for solving the problems, such as system compact and high frequency.
Heterogeneous integrated technology is by the circuit unit of various various substrates materials and chip while to process on one substrate,
Planar integrated circuit is fabricated to three dimensional integrated circuits in the way of by multiple-level stack and vertically interconnecting.Make traditional system bulk
It is further decreased with area, realizes system compact.Simultaneously using heterogeneous integrated technology can effective promotion signal transmission performance,
Reliability is high, it is at low cost the advantages that.
With the fast development of heterogeneous integrated technology so that people are to the millimeter wave and submillimeter wave frequency range in electromagnetic spectrum
The interest being used is growing.Therefore in order to realize application of the system in millimeter wave and submillimeter wave frequency range, using three-dimensional
Heterogeneous integrated technology, and silicon integrated RF technology and the high frequencies compound semiconductor materials such as indium phosphide and gallium nitride is combined to manufacture
Device composition system, radio frequency system area occupied can be effectively reduced, and the further working frequency of lifting system.
In conclusion current laminated multi-chip is all using the method for interconnection bonding, the chip of various substrates material is horizontal
To being integrated on single silicon substrate, to improve the complicated integrated level of radio frequency system, reduce system area occupied, to lifting system
Overall performance, but these methods have the following disadvantages：
In the prior art, current semiconductor chip manufacture machining accuracy is limited to usually to lead since common method is unstable
It causes that level of integrated system can be reduced there are several microns of spacing between the chip of horizontal integrating, is unfavorable for system compact development.Together
When, it is mutual between multiple substrate chips as system overall work frequency is further increased to millimeter wave and submillimeter wave frequency range
Connection block and bonding loss and ghost effect become serious, to reduce systematic entirety energy.
Third, with the increase of working frequency, one single chip area will become very little, be interconnected during multi-chip is integrated several
What resolution ratio, dimensional tolerance etc. is all corresponding to be reduced, and is proposed very high requirement to interconnection precision, can be caused this method unstable in this way
Fixed, there is deviation in the relative position for frequently resulting in each chip chamber, and system entirety yield rate is greatly reduced.
Invention content
It is an object of the invention in view of the above shortcomings of the prior art, propose a kind of heterogeneous integrated radio frequency system of wafer scale
Structure and preparation method thereof reduces system entirety area occupied and volume, to miniaturization to improve conventional radio frequency level of integrated system
System Development；The loss and ghost effect for reducing chip interconnection and bonding under high frequency situations, improve system operating frequency characteristic.
Based on a kind of above-mentioned purpose heterogeneous integrated radio frequency system of wafer scale provided by the invention, include at least the first substrate,
Second substrate, insulating bond layer, at least two chips；Wherein：
Second substrate, insulating bond layer, at least two chips are set between the first substrate, the second substrate, including
The first chip being connect with first substrate and the second chip being connect with second substrate；
At least one through-hole is provided on the insulating bond layer, the through-hole side wall is coated with conductive coating；
One at least two chip connect with the first substrate, at least two chips another and second lining
Bottom connects, and at least two chips are electrically connected by the through-hole；
Bonded layer align material between wafer is provided on first substrate and/or the second substrate；It is bonded between the wafer
Layer align material support connects first substrate and second substrate so that keeps setting between the first substrate and the second substrate
Fixed distance.
Optionally, the system also includes metal interconnections；The insulating bond layer includes that there are one the through-holes for setting
First insulating bond layer and the second insulating bond layer for being provided at least two through-holes；The chip further includes and described
The third chip of two insulating bond layers connection；
First substrate and second substrate make for compound semiconductor；
Described through-hole one end is provided with conductive micro convex point, the conductive micro convex point for connecting another through-hole so that is located at not
The through-hole alignment of same layer connects；
The metal interconnection connects two through-holes of the second insulating bond layer.
Optionally, bonded layer align material includes the first wafer linkage being set on first substrate between the wafer
It closes layer align material and is set to bonded layer align material between the second wafer set on second substrate；Between first wafer
Bonded layer align material is bonded or is stacked between bonded layer align material and the second wafer.
Optionally, at least one of first substrate and the second substrate include substrate material and epitaxial material；It is described
Epitaxial material is set to the substrate material side.
Optionally, first substrate is silicon carbide substrates；Second substrate is InP substrate.
Optionally, the chip is gallium nitride power amplifier chip, gallium nitride phase shifter chip, indium phosphide low noise are put
One kind in the chips and aerial array such as big device chip, indium phosphide power switch chip, filter.
Optionally, bonded layer align material is the polymer of BCB (BCB) between the wafer.
Optionally, the first insulating bond layer material is SiO2 insulating polymers or Si3N4 insulating polymers；Described
Two insulating bond layer materials are SiO2 insulating polymers, Si3N4 insulating polymers, AlN insulating polymers, Al2O3 insulation polymerizations
Object or benzocyclobutene close object.
Optionally, the conductive coating of the through-hole is Au, Cu or Cu-Sn metallic compound；The making of the metal interconnection
Material is Au, Cu metallic compound；Metal charge in the conduction micro convex point is Cu-Sn metallic compounds.
Meanwhile the present invention also provides a kind of manufacturing method of the heterogeneous integrated radio frequency system of wafer scale, the method includes with
Lower step：
Hole is opened up on insulating bond layer, is coated on the hole wall in the hole conductive coating and is formed conductive through-hole, and
The conductive micro convex point of through-hole one end manufacture；The bonded layer align material between making wafer on the first substrate and/or the second substrate；
First Grown has the first chip, second Grown to have the second chip；It is set on the insulating bond layer
It is equipped with third chip；The insulating bond layer includes the first insulating bond layer being connect with the first substrate or the second substrate, and
The the second insulating bond layer detached with first substrate and the second substrate；
Bonded layer align material between wafer is carried out by alignment bonding using low-temperature bonding mode, while using low-temperature bonding side
The micro convex point of at least two target through-holes to be aligned is bonded by formula so that the target through-hole alignment connection, to make
It obtains the first chip, the second chip and third chip and passes through the target through-hole and corresponding conductive micro convex point realization electrical connection.
The present invention has the following advantages that compared with prior art：
In the embodiment of the present invention, types of functionality chip and compound semiconductor device are carried out by the technology of their own
Manufacture this ensure that each monolithic has its best performance, and is reduced finally by the heterogeneous integrated technology of wafer scale
Risk in system manufacturing process, and close Top-down design can be provided between compound semiconductor and device；
It, can will such as heterojunction of indium phosphide bipolar transistor using hetero-epitaxy transfer techniques in the embodiment of the present invention
(HBT, Heterojunction Bipolar Transistor), the counterfeit modulation doping heterojunction field effect transistor of indium phosphide
(PHEMT, Pseudomorphic High Electron Mobility Transistor) low noise, GaAs Power switch
It is integrated on a complete wafer etc. the Films In Passive Microwave Devices such as active microwave device and phase-shifter, filter, it can be effective
Lifting system integrated level reduces the area occupied of system entirety, to realize miniaturization target.In addition using with high frequency characteristics
Semiconductor devices, the working frequency of effective lifting system.
The interconnection between chip is realized using micro convex point, through-hole technology, substitute the gold of chip chamber in the embodiment of the present invention
Silk bonding, to effectively shorten internal mutual on line so that signal transmission performance is promoted, and at high frequencies, is reduced and posted
Come into force the influence answered, and improves the reliability of system performance.
The embodiment of the present invention makes two for the integrated mode for using Intercalative binding layer material between wafer and wafer
Different substrates are sticked together by bonded layer, more effectively realize wafer scale bonding, are reduced opposite between different chips
There is the probability of error in position, improves the yield rate of system.
Description of the drawings
Fig. 1 is the heterogeneous integrated radio frequency system overall structure diagram of the wafer scale of an embodiment of the present invention；
Fig. 2 is the substrat structure schematic diagram of an embodiment of the present invention；
Fig. 3 is the system production process schematic diagram of the present invention；
Fig. 4 is a kind of flow diagram of specific embodiment of the present invention.
Specific implementation mode
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
The present invention provides a kind of heterogeneous integrated radio frequency system of wafer scale, and structure is as shown in Figure 1, include at least the first substrate
101, the chip that the second substrate 102, insulating bond layer, at least two different layers are arranged；Wherein：
Second substrate 102, insulating bond layer, at least two chips are set to the first substrate 101, the second substrate 102
Between, include the first chip 103 being connect with first substrate 101, the second chip being connect with second substrate 102
104；
At least one through-hole 105 is provided on the insulating bond layer, 105 side wall of the through-hole is coated with conductive coating；
One at least two chip connect with the first substrate, at least two chips another and second lining
Bottom connects, and at least two chips are electrically connected by the through-hole 105；
It is provided with bonded layer align material between wafer on first substrate, 101 and/or second substrate 102；The wafer
Between the support of bonded layer align material connect first substrate 101 and second substrate 102 so that the first substrate 101 and the
The distance of setting is kept between two substrates 102.
From the above it can be seen that the heterogeneous integrated radio frequency system of wafer scale provided by the invention, in the first substrate and
At least two chips are set between two substrates, and at least two chip is arranged at a distance from different with the first substrate, realizes
The over all Integration of two or more chips reduces the occupancy volume and area occupied of system entirety, reaches system compact
Technique effect.Meanwhile the heterogeneous integrated radio frequency system of wafer scale of the above embodiment of the present invention, wherein at least two chip is by setting
The through-hole being placed on insulating bond layer is electrically connected, and substitutes the gold wire bonding of chip chamber, saves link cost, additionally it is possible to effectively
Shorten internal mutual on line so that signal transmission performance is promoted, and at high frequencies, is reduced the influence of ghost effect, carried
The high reliability of system performance.
In some embodiment of the invention, referring still to Fig. 1, the system also includes metal interconnections 106；The insulation key
Layer is closed to include setting there are one the first insulating bond layer 107 of the through-hole 105 and be provided at least two through-holes 105
Second insulating bond layer 108；The chip further includes the third chip 109 being connect with the second insulating bond layer 108；
First substrate 101 and second substrate 102 make for compound semiconductor；
105 one end of the through-hole is provided with conductive micro convex point 1051, the conductive micro convex point for connecting another through-hole 105
1052 so that be located at the alignment connection of through-hole 105 of different layers；
The metal interconnection 106 connects two through-holes 105 of the second insulating bond layer 108.
Specifically, the conduction micro convex point 1051 includes contacting bottom surface and arc-shaped top surface with through-hole 105, as welding
Point, the contact that is electrically connected, contraposition reference point use, and are set to through-hole 105 and need and another through-hole alignment and one end for being electrically connected.
Specifically, shown in referring to Fig.1, the second insulating bond layer 108 be set to the first substrate 101 and the second substrate 102 it
Between, in the present embodiment there are two setting, it is layered on top of each other setting；The two second insulating bond layers 108 respectively by two or
Multiple first insulating bond layers 107 are connect with the first substrate 101 or the second substrate 102, are relatively fixed in the first substrate 101 and
Between two substrates 102.Third chip 109 is set between two the second insulating bond layers 108.In the second insulating bond layer 108
On, multiple through-holes 105 are provided with, to which the first chip 103, the second chip 104, third chip 109 can pass through the first insulation key
The combination between the through-hole of layer 107, the through-hole and metal interconnection 106 of the second insulating bond layer 109 is closed to connect to be formed each other
Conducting.
In other embodiments of the present invention, more second insulating bond layers 109 can be also arranged as required to, to realize
Connection is stacked between the chip of more layers.The embodiment of the present invention realizes the interconnection between chip using micro convex point, through-hole technology,
The gold wire bonding for substituting chip chamber, to effectively shorten internal mutual on line so that signal transmission performance is promoted, and in high frequency feelings
Under condition, reduce the influence of ghost effect, improves the reliability of system performance.
In another specific embodiment of the invention, referring still to Fig. 1, bonded layer align material includes setting between the wafer
Bonded layer align material 110 and being set on second substrate 102 is set between the first wafer being placed on first substrate 101
The second wafer between bonded layer align material 111；It is bonded between bonded layer align material 110 and the second wafer between first wafer
The bonding of layer align material 111 is stacked.
The embodiment of the present invention makes two for the integrated mode for using Intercalative binding layer material between wafer and wafer
Different substrates are sticked together by bonded layer, more effectively realize that wafer scale is bonded, bonded layer is directed at material between the first wafer
Material, when the first substrate and the second substrate bonding connect, can make with bonded layer align material between the second wafer as alignment mark
With raising aligning accuracy reduces contraposition difficulty and position aligning time, the several of error occurs in relative position between reducing different chips
Rate improves the yield rate of system.
In some embodiment of the invention, at least one of first substrate and the second substrate include substrate material and
Epitaxial material；The epitaxial material is set to the substrate material side.For example, figure can be used in the first substrate and the second substrate
Structure shown in 2：Substrate material 201 is provided with epitaxial material 202 as a substrate in 201 side of substrate material；Wherein,
Epitaxial material 202 includes the multiple layers of different materials being stacked, for example, nucleating layer, buffer layer, insert layer and barrier layer.
For above system structure example, first substrate 101 is SiC substrate；Second substrate 102 serves as a contrast for InP
Bottom；Bonded layer align material makes for BCB polymer between the wafer；BCB has excellent electrical insulation capability, and has resistance to height
Temperature, the advantages that dielectric constant is small, dielectric loss is small.First insulating bond layer, 107 material be SiO2 insulating polymers or
Si3N4 insulating polymers；Second insulating bond layer, 108 material is SiO2 insulating polymers, Si3N4 insulating polymers, AlN
One kind in insulating polymer, Al2O3 insulating polymers or BCB insulating polymers.When the second insulating bond layer 108 is provided with
More than one when, different material can be used and make.The conductive coating of the through-hole is Au, Cu or Cu-Sn metallic compound；
The making material of the metal interconnection is Au, Cu metallic compound；In a particular embodiment, the conductive micro convex point is filled with gold
Belong to, to realize that conducting function, metal charge are Cu-Sn metallic compounds；The chip includes following functional chip：Nitridation
Gallium power amplifier chip, gallium nitride phase shifter chip, indium phosphide the low noise amplifier chip, indium phosphide power switch chip,
One kind in the chips such as filter or aerial array.In a particular embodiment, the first chip, the second chip, third chip
Include the chip of at least one function, at least one of above-mentioned functional chip specifically may be selected.
Further, the present invention also provides a kind of manufacturing method of the heterogeneous integrated radio frequency system of wafer scale, including it is as shown in Figure 3
The step of：
Step 301：The first substrate, the second substrate and respective chip are prepared, insulating bond layer is prepared, prepares third core
Piece.Specifically, being opened up on insulating bond layer, hole, coating conductive coating forms conductive through-hole on the hole wall in the hole, and
Conductive micro convex point is manufactured in described through-hole one end；Bonded layer is directed at material between making wafer on the first substrate and/or the second substrate
Material；First Grown has the first chip, second Grown to have the second chip；On the insulating bond layer
It is provided with third chip.The insulating bond layer includes the first insulating bond layer being connect with the first substrate or the second substrate, with
And the second insulating bond layer detached with first substrate and the second substrate.
Wherein, when preparing the first substrate, the second substrate and respective chip, corresponding substrate material is selected, in substrate material
Epitaxial material required for one chip of growth regulation or the second chip, then manufactures the first chip or with conventional semiconductor process on material
Two chips.
Next using chemical plasma enhancing chemical vapor deposition (PECVD, Plasma Enhanced Chemical
Vapor Deposition) etc. one insulating bond layer of equipment growth regulation, followed in turn by photoresist pair the first insulating bond layer carry out
Photoetching, develop the first chip or the required telltale hole of the second chip figure, utilize sputtering or evaporation and electroplating technology
Conductive layer coating is carried out to the side wall in the hole, forms conductive through-hole.Using inductively coupled plasma (ICP,
Inductively Coupled Plasma) dry etching removes unwanted part in the first insulating bond layer, and uses back
Flow Technique produces conductive micro convex point.
Then again in surface spin coating photoresist, expose, bonded layer alignment patterns between the wafer that develops.And utilize PECVD
Etc. equipment grow BCB polymer in the corresponding graphics field in surface, form bonded layer align material between wafer, then use wet method
The photoresist for removing previous step coating, finally completes the making of bonded layer align material between wafer.
When making third chip, the substrate material needed for third chip is selected, grows one first in substrate material front
The second insulating bond layer of layer, then the required epitaxial material of regrowth third chip, then reuses conventional semiconductor process
Manufacture third chip, including positive technique and backside through vias technique.
One layer of second insulating bond layer is regrowed above third chip later, then in the second insulating bond layer surface
Photoresist is coated, mask layer is formed, third institute is made by lithography on the second insulating bond layer above third chip using electron beam
The hole needed and the required metal interconnection pattern of third chip, it is then mutual in the hole and metal by sputtering or evaporation technology
Metallic compound is filled in connection figure, and is thickeied by being electroplated, and conductive through-hole and metal interconnection are formed.Pass through ICP dry method
Quarter etches away the second additional insulating bond layer material, and produces conductive micro convex point using technique of backflow, removes third later
The substrate material of chip manufactures through-hole and conductive micro convex point on the second insulating bond layer below epitaxial material.
Step 302：Bonded layer align material between wafer is carried out by alignment bonding using low-temperature bonding mode, while using low
The micro convex point of at least two target through-holes to be aligned is bonded by warm bonding pattern so that the target through-hole alignment connects
It connects, so that the first chip, the second chip and third chip are real by the target through-hole and corresponding conductive micro convex point
Now it is electrically connected.
In a kind of specific embodiment of the present invention, described method includes following steps：
Step 401, it is silicon carbide-based substrate to choose corresponding compound semiconductor substrate material, and sharp on underlay substrate
With metallo-organic compound chemical gaseous phase deposition, it is required that the equipment such as molecular beam epitaxy grow gallium nitride, indium phosphide device
Nucleating layer, buffer layer, insert layer and barrier layer homepitaxy material, followed by manufacturing processes customary, including sputtering, evaporation, light
It carves, plating, prepares corresponding first chip or the second chip, after the completion of the first chip or the second chip front side technique,
Via process is carried out in substrate back, realizes the heat dissipation effect to respective chip；
Step 402, using PECVD device, one layer of first insulating bond layer is grown, material uses Si3N4 or SiO2.Then
In first insulating bond layer surface spin-on polyimide (PI) photoresist, corresponding mask layer is formed, and light is carried out to its surface
It carves, development, exposes the figure in the required hole of the first chip, finally utilize sputter or evaporator that one layer of metal compound is deposited
The seed metals such as object Ti/Au, Cu, Cu/Sn, again spin coating photoresist carry out photoetching and development, and coordination galvanization technique device to hole
The coating that side wall carries out conductive layer forms through-hole, then sputters one layer of solder Sn so that solder Sn forms conductive micro convex point；
Step 403, first remove photoresist with wet etching, then recycle the etching apparatus such as ICP, etch away in through-hole 3
Metal other than seed layer metal, finally utilize reflux technique make with solder micro convex point 4；
Step 404, again in surface spin coating photoresist, photoetching, development are also passed through, produces and is bonded between wafer
Layer alignment patterns.And BCB polymer is grown in the corresponding graphics field in surface using equipment such as PECVD, form wafer linkage
Close layer material.Then the photoresist for removing coating with wet method, removes extra BCB polymer with dry etching, completes between wafer
It is bonded the making of layer material；
Step 405, with step 401, the substrate material needed for third chip is chosen, grows one layer of second insulation on substrate
Bonded layer completes the manufacture of third chip, grows other one layer of second insulating bond layer in third chip surface later；
Step 406, with step 402,403, produced on the second insulating bond layer of third chip surface containing through-hole,
Metal interconnection and conductive micro convex point；
Step 407, by the micro convex point of the second insulating bond layer and the micro convex point of corresponding first insulating bond layer into line unit
It closes, realizes that multiple-level stack avoids chip from damaging using low-temperature bonding mode, realize chip to integrating between wafer；
Step 408, using technologies such as hetero-epitaxy transfer, mechanical thinning and polishing or wet etchings, remove third chip
Substrate material, surface leave other one layer of second insulating bond layer, then the repeatedly technique of step 406, in the second insulating bond
Through-hole and conductive micro convex point are manufactured on layer；
Step 409, it using low-temperature bonding mode, bonding layer material will carry out pair between the wafer of step 404 and 408 manufactures
Quasi- bonding, while according to design structure, the conductive micro convex point of corresponding through-hole is subjected to bonding connection, it is complete to complete one
The heterogeneous integrated system of wafer scale high frequency three dimensional making.
It should be appreciated that multiple embodiments described in this specification are merely to illustrate and explain the present invention, it is not used to limit
The fixed present invention.And in the absence of conflict, the features in the embodiments and the embodiments of the present application can be combined with each other.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
The specific implementation of the present invention is confined to these explanations.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to the present invention's
Protection domain.
Claims (10)
1. a kind of heterogeneous integrated radio frequency system of wafer scale, which is characterized in that include at least the first substrate, the second substrate, insulation key
Close layer, at least two chips；Wherein：
Second substrate, insulating bond layer, at least two chips are set between the first substrate, the second substrate, including with institute
The second chip stated the first chip of the first substrate connection and connect with second substrate；
At least one through-hole is provided on the insulating bond layer, the through-hole side wall is coated with conductive coating；
One at least two chip connect with the first substrate, another at least two chips connects with the second substrate
It connects, and at least two chips are electrically connected by the through-hole；
Bonded layer align material between wafer is provided on first substrate and/or the second substrate；Bonded layer pair between the wafer
Quasi- materials for support connects first substrate and second substrate so that setting is kept between the first substrate and the second substrate
Distance.
2. the heterogeneous integrated radio frequency system of wafer scale according to claim 1, which is characterized in that the system also includes metals
Interconnection；The insulating bond layer includes setting there are one the first insulating bond layer of the through-hole and is provided with described at least two
Second insulating bond layer of through-hole；The chip further includes the third chip being connect with the second insulating bond layer；
First substrate and second substrate make for compound semiconductor；
Described through-hole one end is provided with conductive micro convex point, the conductive micro convex point for connecting another through-hole so that is located at different layers
Through-hole alignment connection；
The metal interconnection connects two through-holes of the second insulating bond layer.
3. the heterogeneous integrated radio frequency system of wafer scale according to claim 1, which is characterized in that bonded layer pair between the wafer
Quasi- material includes bonded layer align material and being set to second substrate between the first wafer being set on first substrate
On bonded layer align material between the second wafer for setting；Bonded layer between bonded layer align material and the second wafer between first wafer
Align material is bonded or is stacked.
4. the heterogeneous integrated radio frequency system of wafer scale according to claim 1, which is characterized in that first substrate and second
At least one of substrate includes substrate material and epitaxial material；The epitaxial material is set to the substrate material side.
5. the heterogeneous integrated radio frequency system of wafer scale according to claim 4, which is characterized in that first substrate is carbonization
Silicon substrate；Second substrate is InP substrate.
6. the heterogeneous integrated radio frequency system of wafer scale according to claim 1, which is characterized in that the chip is gallium nitride work(
Rate amplifier chip, gallium nitride phase shifter chip, indium phosphide the low noise amplifier chip, indium phosphide power switch chip, filtering
One kind in the chips and aerial array such as device.
7. the heterogeneous integrated radio frequency system of wafer scale according to claim 1, which is characterized in that bonded layer pair between the wafer
Quasi- material is the polymer of BCB.
8. the heterogeneous integrated radio frequency system of wafer scale according to claim 1, which is characterized in that the first insulating bond layer
Material is SiO2 insulating polymers or Si3N4 insulating polymers；The second insulating bond layer material be SiO2 insulating polymers,
Si3N4 insulating polymers, AlN insulating polymers, Al2O3 insulating polymers or benzocyclobutene close object.
9. the heterogeneous integrated radio frequency system of wafer scale according to claim 1, which is characterized in that the conductive coating of the through-hole
For Au, Cu or Cu-Sn metallic compound；The making material of the metal interconnection is Au, Cu metallic compound；The conduction is micro-
Metal charge in salient point is Cu-Sn metallic compounds.
10. a kind of manufacturing method of the heterogeneous integrated radio frequency system of wafer scale, which is characterized in that include the following steps：
Hole is opened up on insulating bond layer, conductive coating is coated on the hole wall in the hole and forms conductive through-hole, and described
The conductive micro convex point of through-hole one end manufacture；The bonded layer align material between making wafer on the first substrate and/or the second substrate；It is described
First Grown has the first chip, second Grown to have the second chip；It is provided on the insulating bond layer
Third chip；The insulating bond layer includes the first insulating bond layer being connect with the first substrate or the second substrate, and with institute
State the first substrate and the second insulating bond layer of the second substrate separation；
Bonded layer align material between wafer is carried out by alignment bonding using low-temperature bonding mode, while using low-temperature bonding mode,
The micro convex point of at least two target through-holes to be aligned is bonded so that the target through-hole alignment connection, so that
First chip, the second chip and third chip realize electrical connection by the target through-hole and corresponding conductive micro convex point.
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Inventor after: Ma Xiaohua Inventor after: Hao Yue Inventor after: Yi Chupeng Inventor after: Zhu Jiejie Inventor after: Zhao Ziyue Inventor after: Chen Weiwei Inventor before: Ma Xiaohua Inventor before: Hao Yue Inventor before: Yi Chupeng Inventor before: Zhu Jiejie Inventor before: Zhao Ziyue |