CN108400123B - Wafer-level heterogeneous integrated high-frequency system and manufacturing method thereof - Google Patents
Wafer-level heterogeneous integrated high-frequency system and manufacturing method thereof Download PDFInfo
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Abstract
The invention relates to a wafer-level heterogeneous integrated high-frequency system and a manufacturing method thereof, which at least comprise a first substrate, a second substrate, an insulating bonding layer and at least two chips; wherein: the second substrate, the insulating bonding layer and the at least two chips are arranged between the first substrate and the second substrate and comprise a first chip connected with the first substrate and a second chip connected with the second substrate; at least one through hole is formed in the insulating bonding layer, and a conductive coating is coated on the side wall of the through hole; one of the at least two chips is connected with the first substrate, the other of the at least two chips is connected with the second substrate, and the at least two chips are electrically connected through the through holes; an alignment material of a bonding layer between wafers is arranged on the first substrate and/or the second substrate; the inter-wafer bonding layer is aligned with the material support to connect the first substrate and the second substrate. The embodiment of the invention effectively improves the system integration level and realizes the miniaturization aim.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a wafer-level heterogeneous integrated high-frequency system and a manufacturing method thereof.
Background
With the continuous development of semiconductor chip manufacturing technology and electronic systems, the requirements of miniaturization, multifunction, high frequency and high speed operation, low cost and the like gradually become important targets of future communication systems, space and military system applications, high definition cameras and sensors, automotive radars and other applications.
Compound semiconductor materials have their unique advantages, and thus semiconductor devices made with the compounds also have their unique properties. To further improve the overall performance of the system, one specifically selects the best substrate to fabricate the device, depending on the desired device function. For example, silicon (Si) has been the dominant material in semiconductor technology, which has great advantages in terms of circuit function, integration, cost; the high speed of the second generation semiconductor material gallium arsenide (GaAs); indium phosphide (InP) is widely used in millimeter and submillimeter-wave bands because of its high frequency, high gain, and high power characteristics; and a third generation compound semiconductor material gallium nitride (GaN) with wide bandgap, high breakdown field strength and high power. The devices manufactured by each substrate are different in processing technology steps, and one substrate material cannot be processed by different processing technologies, so that semiconductor chips with different substrate materials are mostly used in a single system, and are combined into a complete system in a gold wire bonding mode. The system thus manufactured has a large area, which is not favorable for miniaturization.
Current advances in semiconductor manufacturing and packaging technology have allowed semiconductor active devices and passive devices with different functions to be integrated laterally and simultaneously on a single substrate, and the use of short-pitch interconnect bonding and related technologies has allowed higher performance and denser circuits than conventional printed circuit boards. The recent use of stacked multi-chip integration techniques has led to further improvements in circuit and system performance and expansion of operating frequencies to near 100GHz or so. However, in the stacked multi-chip integration technology, because various devices are laterally grown and due to processing precision problems, a distance of several micrometers to ten and several micrometers is left between the devices, and the occupied area and the volume of the system are increased. Meanwhile, with the further increase of the frequency, the internal loss and parasitic effect of the bonding wires among the substrate chips become more serious and are difficult to overcome. Heterogeneous integration techniques have therefore been proposed to address the problems of system miniaturization and high frequency.
The heterogeneous integration technology is to process circuit units and chips of various different substrate materials on one substrate simultaneously, and to manufacture a planar integrated circuit into a three-dimensional integrated circuit by means of multilayer stacking and vertical interconnection. The volume and the area of the traditional system are further reduced, and the system is miniaturized. Meanwhile, by adopting a heterogeneous integration technology, the signal transmission performance can be effectively improved, and the method has the advantages of high reliability, low cost and the like.
With the rapid development of heterogeneous integration technology, people are increasingly interested in utilizing millimeter wave and sub-millimeter wave frequency bands in the electromagnetic spectrum. Therefore, in order to realize the application of the system in millimeter wave and submillimeter wave frequency bands, the system is formed by adopting a three-dimensional heterogeneous integration technology and combining a silicon integrated radio frequency technology and devices made of high-frequency compound semiconductor materials such as indium phosphide, gallium nitride and the like, the occupied area of the radio frequency system can be effectively reduced, and the working frequency of the system is further improved.
In summary, the current stacked multi-chip employs an interconnection bonding method to laterally integrate chips of different substrate materials onto a single silicon substrate, so as to improve the complexity of the radio frequency system and reduce the occupied area of the system, thereby improving the overall performance of the system, but these methods all have the following disadvantages:
in the prior art, the manufacturing and processing precision of the current semiconductor chip is limited, and because a common method is unstable, a distance of several microns is often left between chips which are transversely integrated, so that the system integration level is reduced, and the system miniaturization development is not facilitated. Meanwhile, as the overall operating frequency of the system is further increased to millimeter wave and sub-millimeter wave frequency bands, interconnection blocks, bonding losses and parasitic effects among the plurality of substrate chips become severe, thereby reducing the overall performance of the system.
Thirdly, with the increase of the working frequency, the area of a single chip becomes very small, the geometric resolution, the dimensional tolerance and the like of interconnection in multi-chip integration are correspondingly reduced, and high requirements are put on the interconnection precision, so that the method is unstable, the relative position among the chips is often deviated, and the overall yield of the system is greatly reduced.
Disclosure of Invention
The invention aims to provide a wafer-level heterogeneous integrated high-frequency system structure and a manufacturing method thereof aiming at the defects of the prior art, so as to improve the integration level of the traditional radio frequency system, reduce the whole occupied area and volume of the system and develop towards a miniaturized system; the chip interconnection and bonding loss and parasitic effect under the high-frequency condition are reduced, and the working frequency characteristic of the system is improved.
The wafer-level heterogeneous integrated high-frequency system at least comprises a first substrate, a second substrate, an insulating bonding layer and at least two chips; wherein:
the second substrate, the insulating bonding layer and the at least two chips are arranged between the first substrate and the second substrate and comprise a first chip connected with the first substrate and a second chip connected with the second substrate;
at least one through hole is formed in the insulating bonding layer, and a conductive coating is coated on the side wall of the through hole;
one of the at least two chips is connected with the first substrate, the other of the at least two chips is connected with the second substrate, and the at least two chips are electrically connected through the through holes;
an alignment material of a bonding layer between wafers is arranged on the first substrate and/or the second substrate; the inter-wafer bonding layer is aligned with the material support to connect the first substrate and the second substrate, so that a set distance is kept between the first substrate and the second substrate.
Optionally, the system further comprises a metal interconnect; the insulating bonding layer comprises a first insulating bonding layer provided with one through hole and a second insulating bonding layer provided with at least two through holes; the chip further comprises a third chip connected with the second insulating bonding layer;
the first substrate and the second substrate are made of compound semiconductors;
one end of the through hole is provided with a conductive micro-bump which is used for connecting with a conductive micro-bump of another through hole, so that the through holes in different layers are aligned and connected;
the metal interconnection is connected with the two through holes of the second insulating bonding layer.
Optionally, the inter-wafer bonding layer alignment material includes a first inter-wafer bonding layer alignment material disposed on the first substrate and a second inter-wafer bonding layer alignment material disposed on the second substrate; and the first inter-wafer bonding layer alignment material and the second inter-wafer bonding layer alignment material are bonded or stacked together.
Optionally, at least one of the first substrate and the second substrate comprises a substrate material and an epitaxial material; the epitaxial material is disposed on one side of the substrate material.
Optionally, the first substrate is a silicon carbide substrate; the second substrate is an indium phosphide substrate.
Optionally, the chip is one of a gallium nitride power amplifier chip, a gallium nitride phase shifter chip, an indium phosphide low-noise amplifier chip, an indium phosphide power switch chip, a filter, and an antenna array.
Optionally, the alignment material of the bonding layer between wafers is benzocyclobutene polymer (BCB).
Optionally, the first insulating bonding layer is made of SiO2 insulating polymer or Si3N4 insulating polymer; the second insulating bonding layer is made of SiO2 insulating polymer, Si3N4 insulating polymer, AlN insulating polymer, Al2O3 insulating polymer or benzocyclobutene compound.
Optionally, the conductive coating of the through hole is Au, Cu, or Cu — Sn metal compound; the metal interconnection is made of Au and Cu metal compounds; the metal filler in the conductive micro-bump is a Cu-Sn metal compound.
Meanwhile, the invention also provides a manufacturing method of the wafer-level heterogeneous integrated high-frequency system, which comprises the following steps:
forming a hole on the insulating bonding layer, coating a conductive coating on the wall of the hole to form a conductive through hole, and manufacturing a conductive micro-bump at one end of the through hole; manufacturing an inter-wafer bonding layer alignment material on the first substrate and/or the second substrate; a first chip grows on the first substrate, and a second chip grows on the second substrate; a third chip is arranged on the insulating bonding layer; the insulating bonding layer comprises a first insulating bonding layer connected with the first substrate or the second substrate and a second insulating bonding layer separated from the first substrate and the second substrate;
and carrying out alignment bonding on the alignment material of the bonding layer between the wafers by adopting a low-temperature bonding mode, and simultaneously bonding the micro-bumps of at least two target through holes to be aligned by adopting the low-temperature bonding mode to ensure that the target through holes are aligned and connected, so that the first chip, the second chip and the third chip are electrically connected through the target through holes and the corresponding conductive micro-bumps.
Compared with the prior art, the invention has the following advantages:
in the embodiment of the invention, various functional chips and compound semiconductor devices are manufactured by the advantageous processes of the functional chips and the compound semiconductor devices, so that each single chip is ensured to have the optimal performance, the risk in the system manufacturing process is reduced by the wafer-level heterogeneous integration technology, and the compact longitudinal integration between the compound semiconductor and the devices can be provided;
in the embodiment of the invention, active microwave devices such as an indium phosphide Heterojunction Bipolar Transistor (HBT) and an indium phosphide pseudo modulation doped Heterojunction field effect Transistor (PHEMT) low-noise amplifier and a gallium arsenide power switch, and passive microwave devices such as a phase shifter and a filter can be integrated on a complete wafer by using a heteroepitaxial transfer technology, so that the system integration level can be effectively improved, the overall occupied area of the system can be reduced, and the miniaturization target can be realized. In addition, the semiconductor device with high-frequency characteristics is used, so that the working frequency of the system is effectively improved.
In the embodiment of the invention, the interconnection between the chips is realized by using the micro-bump and through hole technology, and gold wire bonding between the chips is replaced, so that the internal interconnection line is effectively shortened, the signal transmission performance is improved, the influence of parasitic effect is reduced under the high-frequency condition, and the reliability of the system performance is improved.
The embodiment of the invention adopts a mode of inserting bonding layer materials aiming at the integration between the wafers, so that two different substrates are adhered together through the bonding layer, the wafer-level bonding is more effectively realized, the probability of errors occurring in relative positions between different chips is reduced, and the yield of a system is improved.
Drawings
FIG. 1 is a schematic diagram of an overall structure of a wafer level heterogeneous integrated high frequency system according to an embodiment of the present invention;
FIG. 2 is a schematic view of a substrate structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a system fabrication process of the present invention;
FIG. 4 is a flow chart illustrating an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
The invention provides a wafer-level heterogeneous integrated high-frequency system, which has a structure shown in figure 1 and at least comprises a first substrate 101, a second substrate 102, an insulating bonding layer and at least two chips arranged in different layers; wherein:
the second substrate 102, the insulating bonding layer and the at least two chips are arranged between the first substrate 101 and the second substrate 102, and comprise a first chip 103 connected with the first substrate 101 and a second chip 104 connected with the second substrate 102;
at least one through hole 105 is formed in the insulating bonding layer, and a conductive coating is coated on the side wall of the through hole 105;
one of the at least two chips is connected with the first substrate, the other of the at least two chips is connected with the second substrate, and the at least two chips are electrically connected through the through hole 105;
an alignment material of a bonding layer between wafers is arranged on the first substrate 101 and/or the second substrate 102; the inter-wafer bonding layer alignment material support connects the first substrate 101 and the second substrate 102, so that a set distance is maintained between the first substrate 101 and the second substrate 102.
From the above, it can be seen that the wafer-level heterogeneous integrated high-frequency system provided by the invention has the advantages that the at least two chips are arranged between the first substrate and the second substrate, and the at least two chips are arranged at different distances from the first substrate, so that the overall integration of two or more chips is realized, the overall occupied volume and the occupied area of the system are reduced, and the technical effect of system miniaturization is achieved. Meanwhile, in the wafer-level heterogeneous integrated high-frequency system of the embodiment of the invention, at least two chips are electrically connected through the through holes arranged on the insulating bonding layer, gold wire bonding between the chips is replaced, the connection cost is saved, internal interconnection lines can be effectively shortened, the signal transmission performance is improved, the influence of parasitic effect is reduced under the high-frequency condition, and the reliability of the system performance is improved.
In some embodiments of the present invention, still referring to fig. 1, the system further includes metal interconnects 106; the insulating bonding layer comprises a first insulating bonding layer 107 provided with one of the through holes 105 and a second insulating bonding layer 108 provided with at least two of the through holes 105; the chip further comprises a third chip 109 connected to the second insulating bonding layer 108;
the first substrate 101 and the second substrate 102 are made of compound semiconductors;
one end of the through hole 105 is provided with a conductive micro bump 1051 for connecting with a conductive micro bump 1052 of another through hole 105, so that the through holes 105 in different layers are aligned and connected;
the metal interconnect 106 connects the two vias 105 of the second insulating bonding layer 108.
Specifically, the conductive micro bump 1051 includes a bottom surface contacting the through hole 105 and an arc-shaped top surface, which is used as a solder point, an electrical connection point, and an alignment reference point, and is disposed at one end of the through hole 105 that needs to be aligned with and electrically connected to another through hole.
Specifically, referring to fig. 1, the second insulating bonding layer 108 is disposed between the first substrate 101 and the second substrate 102, two in this embodiment, and stacked on each other; the two second insulating bonding layers 108 are connected to the first substrate 101 or the second substrate 102 through two or more first insulating bonding layers 107, respectively, and are relatively fixed between the first substrate 101 and the second substrate 102. The third chip 109 is disposed between two second insulating bonding layers 108. On the second insulating bonding layer 108, a plurality of through holes 105 are disposed, so that the first chip 103, the second chip 104, and the third chip 109 can be electrically connected to each other through the combined connection among the through holes of the first insulating bonding layer 107, the through holes of the second insulating bonding layer 109, and the metal interconnects 106.
In other embodiments of the present invention, more second insulating bonding layers 109 may be further disposed as needed, so as to achieve stacked connection between chips of more layers. According to the embodiment of the invention, the micro-bump and through hole technology is used for realizing interconnection between chips, and gold wire bonding between the chips is replaced, so that internal interconnection lines are effectively shortened, the signal transmission performance is improved, the influence of parasitic effect is reduced under the high-frequency condition, and the reliability of the system performance is improved.
In another embodiment of the present invention, still referring to fig. 1, the inter-wafer bonding layer alignment material includes a first inter-wafer bonding layer alignment material 110 disposed on the first substrate 101 and a second inter-wafer bonding layer alignment material 111 disposed on the second substrate 102; the first inter-wafer bonding layer alignment material 110 and the second inter-wafer bonding layer alignment material 111 are bonded or stacked together.
The embodiment of the invention adopts a mode of inserting bonding layer materials for integration between wafers, so that two different substrates are adhered together through the bonding layers, wafer-level bonding is more effectively realized, and the bonding layer alignment material between the first wafer and the bonding layer alignment material between the second wafer can be used as alignment marks when the first substrate and the second substrate are bonded, so that the alignment precision is improved, the alignment difficulty and the alignment time are reduced, the probability of errors occurring in relative positions between different chips is reduced, and the yield of a system is improved.
In some embodiments of the present invention, at least one of the first and second substrates comprises a substrate material and an epitaxial material; the epitaxial material is disposed on one side of the substrate material. For example, both the first substrate and the second substrate may adopt the structure shown in fig. 2: the substrate material 201 is used as a base, and an epitaxial material 202 is arranged on one side of the substrate material 201; epitaxial material 202 includes, among other things, multiple layers of different materials, such as nucleation layers, buffer layers, insertion layers, and barrier layers, arranged in a stack.
For the above system structure example, the first substrate 101 is a SiC substrate; the second substrate 102 is an InP substrate; the alignment material of the bonding layer between the wafers is made of BCB polymer; BCB has excellent electrical insulation performance, and has the advantages of high temperature resistance, small dielectric constant, small dielectric loss and the like. The first insulating bonding layer 107 is made of SiO2 insulating polymer or Si3N4 insulating polymer; the second insulating bonding layer 108 is made of one of SiO2 insulating polymer, Si3N4 insulating polymer, AlN insulating polymer, Al2O3 insulating polymer, or BCB insulating polymer. When more than one second insulating bonding layer 108 is provided, different materials may be used. The conductive coating of the through hole is Au, Cu or Cu-Sn metal compound; the metal interconnection is made of Au and Cu metal compounds; in a specific embodiment, the conductive micro bump is filled with metal to realize a conductive function, and the metal filler is a Cu-Sn metal compound; the chip comprises the following functional chips: one of gallium nitride power amplifier chip, gallium nitride phase shifter chip, indium phosphide low noise amplifier chip, indium phosphide power switch chip, filter chip, or antenna array. In a specific embodiment, the first chip, the second chip, and the third chip may each include at least one functional chip, and specifically, at least one of the functional chips may be selected.
Further, the present invention also provides a method for manufacturing a wafer level heterogeneous integrated high frequency system, comprising the steps as shown in fig. 3:
step 301: preparing a first substrate, a second substrate and a corresponding chip, preparing an insulating bonding layer and preparing a third chip. Specifically, a hole is formed in an insulating bonding layer, a conductive coating is coated on the wall of the hole to form a conductive through hole, and a conductive micro-bump is manufactured at one end of the through hole; manufacturing an inter-wafer bonding layer alignment material on the first substrate and/or the second substrate; a first chip grows on the first substrate, and a second chip grows on the second substrate; and a third chip is arranged on the insulating bonding layer. The insulating bonding layer includes a first insulating bonding layer connected to the first substrate or the second substrate, and a second insulating bonding layer separated from the first substrate and the second substrate.
When preparing the first substrate, the second substrate and the corresponding chip, selecting the corresponding substrate material, growing an epitaxial material required by the first chip or the second chip on the substrate material, and then manufacturing the first chip or the second chip by using a conventional semiconductor process.
And then growing a first insulating bonding layer by using equipment such as chemical Plasma Enhanced Chemical Vapor Deposition (PECVD), photoetching the first insulating bonding layer by using photoresist, developing a pattern of a signal hole required by the first chip or the second chip, and coating a conductive layer on the side wall of the hole by sputtering or evaporation and electroplating processes to form a conductive through hole. And removing unnecessary parts in the first insulating bonding layer by using Inductively Coupled Plasma (ICP) dry etching, and manufacturing the conductive micro bump by using a reflow technology.
And then, spin-coating photoresist on the surface again, and exposing and developing the alignment pattern of the bonding layer between the wafers. And growing BCB polymer in a corresponding pattern area on the surface by utilizing equipment such as PECVD (plasma enhanced chemical vapor deposition) equipment and the like to form an alignment material of the bonding layer between the wafers, removing the photoresist coated in the previous step by using a wet method, and finally finishing the manufacture of the alignment material of the bonding layer between the wafers.
When the third chip is manufactured, a substrate material required by the third chip is selected, a second insulating bonding layer is firstly grown on the front surface of the substrate material, then an epitaxial material required by the third chip is grown, and then the third chip is manufactured by using a conventional semiconductor process, wherein the conventional semiconductor process comprises a front surface process and a back surface through hole process.
And then growing a second insulating bonding layer on the third chip again, coating photoresist on the surface of the second insulating bonding layer to form a mask layer, photoetching a third required hole and a metal interconnection pattern required by the third chip on the second insulating bonding layer above the third chip by using an electron beam, filling a metal compound in the hole and the metal interconnection pattern by a sputtering or evaporation process, and forming a conductive through hole and a metal interconnection by thickening. And etching away the extra second insulating bonding layer material by ICP dry etching, manufacturing a conductive micro bump by using a reflow technology, removing the substrate material of the third chip, and manufacturing a through hole and a conductive micro bump on the second insulating bonding layer below the epitaxial material.
Step 302: and carrying out alignment bonding on the alignment material of the bonding layer between the wafers by adopting a low-temperature bonding mode, and simultaneously bonding the micro-bumps of at least two target through holes to be aligned by adopting the low-temperature bonding mode to ensure that the target through holes are aligned and connected, so that the first chip, the second chip and the third chip are electrically connected through the target through holes and the corresponding conductive micro-bumps.
In one embodiment of the present invention, the method comprises the steps of:
step 406, synchronous steps 402 and 403, manufacturing a second insulating bonding layer on the surface of the third chip, wherein the second insulating bonding layer contains a through hole, a metal interconnection and a conductive micro bump;
409, aligning and bonding the bonding layer materials between the wafers manufactured in the steps 404 and 408 by adopting a low-temperature bonding mode, and bonding and connecting the conductive micro-bumps of the corresponding through holes according to a designed structure, thereby completing the manufacture of a complete wafer-level high-frequency three-dimensional heterogeneous integrated system.
It is to be understood that the various embodiments described herein are for purposes of illustration and explanation only and are not intended to be limiting. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A wafer-level heterogeneous integrated high-frequency system is characterized by at least comprising a first substrate, a second substrate, an insulating bonding layer and at least two chips; wherein:
the insulating bonding layer and at least two chips are arranged between a first substrate and a second substrate, and the at least two chips comprise a first chip connected with the first substrate and a second chip connected with the second substrate;
at least one through hole is formed in the insulating bonding layer, and a conductive coating is coated on the side wall of the through hole;
the at least two chips are electrically connected through the through holes; an alignment material of a bonding layer between wafers is arranged on the first substrate and/or the second substrate; the inter-wafer bonding layer is aligned with the material support to connect the first substrate and the second substrate, so that a set distance is kept between the first substrate and the second substrate;
the system further includes a metal interconnect; the insulating bonding layer comprises a first insulating bonding layer provided with one through hole and a second insulating bonding layer provided with at least two through holes; the chip further comprises a third chip connected with the second insulating bonding layer;
the first substrate and the second substrate are made of compound semiconductors;
one end of the through hole is provided with a conductive micro-bump which is used for connecting with a conductive micro-bump of another through hole, so that the through holes in different layers are aligned and connected;
the metal interconnection is connected with at least two through holes of the second insulating bonding layer;
the first chip, the second chip and the third chip are connected through the through holes, the metal interconnections and the conductive micro-bumps.
2. The wafer-level hetero-integrated high-frequency system according to claim 1, wherein the inter-wafer bonding layer alignment material comprises a first inter-wafer bonding layer alignment material disposed on the first substrate and a second inter-wafer bonding layer alignment material disposed on the second substrate; and the first inter-wafer bonding layer alignment material and the second inter-wafer bonding layer alignment material are bonded or stacked together.
3. The wafer-level hetero-integrated high-frequency system according to claim 1, wherein at least one of the first and second substrates comprises a substrate material and an epitaxial material; the epitaxial material is disposed on one side of the substrate material.
4. The wafer-level heterogeneous integrated high frequency system according to claim 3, wherein the first substrate is a silicon carbide substrate; the second substrate is an indium phosphide substrate.
5. The wafer-level heterogeneous integrated high frequency system of claim 1, wherein the chip is one of a gallium nitride power amplifier chip, a gallium nitride phase shifter chip, an indium phosphide low noise amplifier chip, an indium phosphide power switch chip, a filter chip, and an antenna array.
6. The wafer-level heterogeneous integrated high-frequency system according to claim 1, wherein the inter-wafer bonding layer alignment material is benzocyclobutene polymer.
7. The wafer-level heterogeneous integrated high-frequency system according to claim 1, wherein the material of the first insulating bonding layer is SiO2 insulating polymer or Si3N4 insulating polymer; the material of the second insulating bonding layer is SiO2 insulating polymer, Si3N4 insulating polymer, AlN insulating polymer, Al2O3 insulating polymer or benzocyclobutene polymer.
8. The wafer-level heterogeneous integrated high-frequency system according to claim 1, wherein the conductive coating of the via is Au, Cu, or Cu-Sn metal compound; the metal interconnection is made of Au and Cu metal compounds; the metal filler in the conductive micro-bump is a Cu-Sn metal compound.
9. A method for manufacturing a wafer-level heterogeneous integrated high-frequency system is characterized by comprising the following steps:
forming a hole on the insulating bonding layer, coating a conductive coating on the wall of the hole to form a conductive through hole, and manufacturing a conductive micro-bump at one end of the through hole; manufacturing an inter-wafer bonding layer alignment material on the first substrate and/or the second substrate; a first chip grows on the first substrate, and a second chip grows on the second substrate; a third chip is arranged on the insulating bonding layer; the insulating bonding layer comprises a first insulating bonding layer connected with the first substrate or the second substrate and a second insulating bonding layer separated from the first substrate and the second substrate;
aligning and bonding the alignment material of the bonding layer between the wafers by adopting a low-temperature bonding mode, and bonding the micro-bumps of at least two target through holes to be aligned by adopting the low-temperature bonding mode to align and connect the target through holes so as to realize the electric connection of the first chip, the second chip and the third chip through the target through holes and the corresponding conductive micro-bumps;
connecting the first chip, the second chip and the third chip through the through holes, the metal interconnection and the conductive micro-bumps; the metal interconnection is used for connecting the through holes.
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| CN111916415A (en) * | 2020-06-17 | 2020-11-10 | 山东大学 | SiC heat sink based on laser processing and preparation method thereof |
| CN112582371B (en) * | 2020-12-14 | 2023-07-25 | 中国科学院上海微系统与信息技术研究所 | Three-dimensional intelligent microsystem chip |
| CN112653395B (en) * | 2020-12-24 | 2023-03-14 | 西安电子科技大学 | Circuit design method for improving gain flatness of multi-stage MMIC power amplifier |
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| US9761547B1 (en) * | 2016-10-17 | 2017-09-12 | Northrop Grumman Systems Corporation | Crystalline tile |
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