KR20020014956A - A method for fabricating semiconductor device using high density plasma oxide - Google Patents
A method for fabricating semiconductor device using high density plasma oxide Download PDFInfo
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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Abstract
Description
본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체 소자 제조 공정 중 층간절연막 형성 공정에 관한 것이며, 더 자세히는 고밀도플라즈마(high density plasma, HDP) 산화막을 사용한 층간절연막 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to an interlayer insulating film forming process in a semiconductor device manufacturing process, and more particularly, to an interlayer insulating film forming process using a high density plasma (HDP) oxide film.
반도체 소자는 통상 다층 구조로 이루어지는데, 각각의 층을 이루는 전도라인 간의 절연을 위하여 산화막계 절연막이 사용되고 있다.A semiconductor device usually has a multilayer structure, and an oxide film-based insulating film is used for insulation between conductive lines constituting each layer.
종래에는 워드라인 형성 후, 그리고 비트라인 형성 후 층간절연 및 평탄화를 위하여 BPSG(borophospho silicate glass)막을 주로 사용하고 있다. BPSG막 공정은 BPSG 증착 후 막질의 고밀도화(densification) 및 평탄화를 위한 장시간의 열처리 공정(플로우 공정)이 필수적으로 수반된다. 뿐만 아니라 BPSG 플로우 진행 후에는 CMP를 실시하여 평탄도를 높이고 있다.Conventionally, a borophospho silicate glass (BPSG) film is mainly used for interlayer insulation and planarization after word line formation and after bit line formation. The BPSG film process essentially involves a long time heat treatment process (flow process) for densification and planarization of the film quality after BPSG deposition. In addition, after the BPSG flow, CMP is performed to increase flatness.
그러나, 이와 같이 BPSG막을 사용한 종래의 층간절연막 형성 공정은 BPSG막 내의 붕소와 인의 농도 불균일에 기인하여 BPSG 플로우 공정시 결정 결함(crystal defect)이 발생하는 문제점이 있었다. BPSG 결정 결함은 후속 마스크 공정시 패턴 프로파일을 악화시킬 뿐만 아니라 비트라인 패턴 사이의 간극에 보이드(void)를 유발하는 요인이 되고 있다.However, the conventional interlayer insulating film forming process using the BPSG film has a problem in that crystal defects occur in the BPSG flow process due to the uneven concentration of boron and phosphorus in the BPSG film. BPSG crystal defects not only worsen the pattern profile in subsequent mask processes but also cause voids in the gaps between the bitline patterns.
첨부된 도면 도 1은 종래기술에 따라 비트라인 간극에 BPSG를 매립하고 BPSG 플로우 및 CMP 공정을 실시한 상태의 단면 SEM 사진과 원내를 확대하여 도시한 것으로, 확대도에서 비트라인 간극에 보이드(A)가 발생함을 확인할 수 있다.1 is an enlarged cross-sectional SEM photograph of a state in which a BPSG is embedded in a bit line gap and a BPSG flow and a CMP process are carried out according to the related art, and an enlarged view shows voids (A) in the bit line gap. You can see that occurs.
또한, 이처럼 BPSG막을 사용하는 층간절연막 형성 공정은 장시간의 BPSG 플로우 공정에 따른 생산성 저하와 열적 부담(thermal budget)이 우려된다.In addition, the interlayer insulating film forming process using the BPSG film is concerned about productivity degradation and thermal budget due to a long BPSG flow process.
그리고, BPSG의 웨이퍼 센터/에지 간의 큰 초기 두께 차이값(500∼700Å)은 후속 CMP 공정 후에도 전체 평탄도를 떨어뜨리는 요인이 되고 있다. 통상적으로, CMP 공정 후의 웨이퍼 센터/에지 간의 높이 차는 700∼1000Å에 이른다.In addition, a large initial thickness difference value (500 to 700 GPa) between wafer centers / edges of the BPSG is a factor of lowering the overall flatness even after a subsequent CMP process. Typically, the height difference between the wafer centers / edges after the CMP process amounts to 700 to 1000 mW.
상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 본 발명은, 웨이퍼 전체의 평탄도를 증대시킬 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.The present invention proposed to solve the problems of the prior art as described above, an object of the present invention is to provide a method for manufacturing a semiconductor device that can increase the flatness of the entire wafer.
또한 본 발명은, 층간절연막 형성시 열적 부담을 줄이고 비트라인 간극을 보이드 없이 매립할 수 있는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.In addition, an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the thermal burden when forming the interlayer insulating film and can fill the bit line gap without voids.
도 1은 종래기술에 따라 비트라인 간극에 BPSG를 매립하고 BPSG 플로우 및 CMP 공정을 실시한 상태의 단면 SEM 사진.1 is a cross-sectional SEM photograph of a state in which BPSG is embedded in a bit line gap and a BPSG flow and a CMP process are performed according to the prior art.
도 2a 및 도 2b는 본 발명의 일 실시예에 따른 반도체 소자 제조 공정도.2A and 2B illustrate a semiconductor device manufacturing process according to an embodiment of the present invention.
도 3은 BPSG막을 증착한 웨이퍼의 프로파일을 모식화하여 나타낸 도면.3 is a diagram schematically illustrating a profile of a wafer on which a BPSG film is deposited.
도 4는 HDP 산화막을 증착한 웨이퍼 웨이퍼의 프로파일을 모식화하여 나타낸 도면.4 is a diagram schematically illustrating a profile of a wafer wafer on which an HDP oxide film is deposited.
도 5a 및 도 5b는 각각 비트라인 형성 후 층간절연막으로 HDP 산화막을 증착한 상태의 단면 SEM 사진.5A and 5B are cross-sectional SEM photographs of HDP oxides deposited as interlayer dielectrics after bit line formation.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
20 : 하부층20: lower layer
21 : BPSG막21: BPSG film
22 : 비트라인22: bit line
23 : 측벽 스페이서23: sidewall spacer
24 : HDP 산화막24: HDP oxide film
상기의 기술적 과제를 달성하기 위한 본 발명의 특징적인 반도체 소자 제조방법은, 비트라인이 형성된 전체 구조 상부에 평탄화 절연막으로 BPSG막을 증착하는 제1 단계; 상기 BPSG막 상에 비트라인을 형성하는 제2 단계; 상기 비트라인이형성된 전체 구조 상부에 고밀도플라즈마(HDP) 산화막을 증착하는 제3 단계; 및 화학적기계적 연마(CMP) 공정을 실시하여 상기 고밀도플라즈마 산화막을 평탄화시키는 제4 단계를 포함하여 이루어진다.A characteristic semiconductor device manufacturing method of the present invention for achieving the above technical problem, the first step of depositing a BPSG film with a planarization insulating film on the entire structure of the bit line; Forming a bit line on the BPSG film; Depositing a high density plasma (HDP) oxide layer on the entire structure of the bit line; And a fourth step of planarizing the high density plasma oxide film by performing a chemical mechanical polishing (CMP) process.
바람직하게 본 발명은, 열처리를 실시하여 상기 고밀도플라즈마 산화막을 치밀화하는 제5 단계를 더 포함하여 이루어진다.Preferably, the present invention further comprises a fifth step of densifying the high-density plasma oxide film by performing heat treatment.
또한, 본 발명의 특징적인 반도체 소자 제조방법은, 비트라인이 형성된 웨이퍼 상부에 층간절연막으로 고밀도플라즈마 산화막을 증착하되, 상기 고밀도플라즈마 산화막 증착시, SiH4/O2/He = 80∼120/110∼150/80∼120sccm의 증착 소오스의 유량, 25000∼35000/25000∼3000W의 저주파 파워/고주파 바이어스 파워 조건을 사용한다.In addition, the characteristic semiconductor device manufacturing method of the present invention, while depositing a high density plasma oxide film as an interlayer insulating film on the wafer on which the bit line is formed, when the high density plasma oxide film, SiH 4 / O 2 / He = 80 ~ 120/110 A flow rate of a deposition source of ˜150 / 80 to 120 sccm and a low frequency power / high frequency bias power condition of 25000 to 35000/25000 to 3000W are used.
바람직하게, 상기 고밀도플라즈마 산화막 증착시, 25000∼35000의 증착율, 15∼25의 식각/증착 비율을 적용한다.Preferably, in the deposition of the high density plasma oxide film, a deposition rate of 25000 to 35000 and an etching / deposition ratio of 15 to 25 are applied.
즉, 본 발명은 워드라인 층간절연막으로는 BPSG(borophospho silicate glass)막을 사용하고, 비트라인 층간절연막으로는 HDP(high density palsma) 산화막을 사용하는 기술이다. BPSG막은 웨이퍼의 센터 부분이 에지 부분에 비해 두껍게 증착되는 성질이 있으며, HDP 산화막은 그와 반대로 웨이퍼의 에지 부분이 센터 부분에 비해 두껍게 증착되는 성질이 있어 웨이퍼 전체적인 두께 균일도를 확보할 수 있다. 또한, HDP 산화막 증착시 증착율을 감소시켜 식각/증착 비율을 높이고, 고주파 바이어스 파워를 증가시킴으로써 HDP 산화막의 갭필링 특성을 향상시킬 수있다.That is, the present invention uses a borophospho silicate glass (BPSG) film as a word line interlayer insulating film and a high density palsma (HDP) oxide film as the bit line interlayer insulating film. The BPSG film has a property of depositing the center portion of the wafer thicker than the edge portion, and the HDP oxide film has the property of depositing the edge portion of the wafer thicker than the center portion, on the contrary, to secure the overall thickness uniformity of the wafer. In addition, it is possible to improve the gap peeling characteristics of the HDP oxide film by reducing the deposition rate during the deposition of the HDP oxide film to increase the etching / deposition ratio and increasing the high frequency bias power.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 2a 및 도 2b는 본 발명의 일 실시예에 따른 반도체 소자 제조 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.2A and 2B illustrate a semiconductor device manufacturing process according to an embodiment of the present invention, which will be described below with reference to the drawings.
본 실시예에 따르면, 우선 도 2a에 도시된 바와 같이 워드라인이 형성된 하부층(20) 상에 층간절연막으로 BPSG막(21)을 증착하고, 통상의 비트라인 형성 공정을 실시하여 비트라인(22) 및 측벽 스페이서(23)를 형성한 다음, 전체 구조 상부에 HDP 산화막(24)을 6000∼8000Å 두께로 증착한다. 이때, 증착율을 감소시켜 식각/증착 비율을 높이고, 고주파 바이어스 파워를 증가시킴으로써 HDP 산화막(24)의 갭필링 특성을 보완한다. 또한, HDP 산화막(24) 증착시 HDP 챔버의 사이드측의 증착 균일도를 향상시키기 위하여 가스 노즐의 수향을 24개 이상으로 증가시키고, 노즐의 길이를 증가시키는 것이 바람직하며, 비트라인과 후속 캐패시터의 패턴 쉬프트 및 붕괴를 방지하기 위하여 HDP 산화막(24)의 막질을 치밀화하기 위한 열처리를 실시하는 것이 바람직하다.According to the present embodiment, first, as shown in FIG. 2A, the BPSG film 21 is deposited on the lower layer 20 having the word line as an interlayer insulating film, and the bit line 22 is formed by performing a conventional bit line forming process. And the sidewall spacers 23 are formed, and then the HDP oxide film 24 is deposited to a thickness of 6000 to 8000 Å over the entire structure. At this time, the deposition rate is reduced to increase the etching / deposition ratio, and the high frequency bias power is increased to compensate for the gap peeling characteristic of the HDP oxide film 24. In addition, in order to improve the deposition uniformity on the side of the HDP chamber when the HDP oxide film 24 is deposited, it is preferable to increase the direction of the gas nozzle to 24 or more, and to increase the length of the nozzle, and to pattern the bit line and the subsequent capacitor. In order to prevent shift and collapse, it is preferable to perform a heat treatment for densifying the film quality of the HDP oxide film 24.
HDP 산화막(24)의 증착 레시피(recipe)는 다음과 같다.The deposition recipe of the HDP oxide film 24 is as follows.
가) 증착 소오스의 유량 : SiH4/O2/He = 80∼120/110∼150/80∼120sccmA) Flow rate of deposition source: SiH 4 / O 2 / He = 80 ~ 120/110 ~ 150/80 ~ 120sccm
나) 파워 : 저주파 파워/고주파 바이어스 파워 = 25000∼35000/25000∼3000WB) Power: Low frequency power / High frequency bias power = 25000 ~ 35000/25000 ~ 3000W
다) 증착율 : 25000∼35000C) Deposition Rate: 25000 ~ 35000
라) 식각/증착 비율 : 15∼25D) Etch / Deposition Ratio: 15 ~ 25
다음으로, 도 2b에 도시된 바와 같이 CMP 공정을 실시하여 HDP 산화막(24)을 평탄화시킨다.Next, as shown in FIG. 2B, the CMP process is performed to planarize the HDP oxide film 24.
첨부된 도면 도 3은 BPSG막을 증착한 웨이퍼의 프로파일을 모식화하여 나타낸 것으로, 웨이퍼(30)의 에지 부분에 비해 센터 부분의 BPSG막(31) 두께가 상대적으로 두껍게 나타나고 있다.FIG. 3 schematically illustrates a profile of a wafer on which a BPSG film is deposited, and the thickness of the BPSG film 31 in the center portion is relatively thick as compared to the edge portion of the wafer 30.
한편, 첨부된 도면 도 4는 HDP 산화막을 증착한 웨이퍼 웨이퍼의 프로파일을 모식화하여 나타낸 것으로, 웨이퍼(40)의 센터 부분에 비해 에지 부분의 HDP 산화막(41)의 두께가 상대적으로 두껍게 나타나고 있다.On the other hand, Figure 4 is a schematic representation of the profile of the wafer wafer on which the HDP oxide film is deposited, the thickness of the HDP oxide film 41 of the edge portion is relatively thick compared to the center portion of the wafer 40.
이와 같은 BPSG막과 HDP 산화막의 증착 성질을 이용하여 전술한 일 실시예와 같이 워드라인 층간절연막으로 BPSG막을 사용하고 비트라인 층간절연막으로 HDP 산화막을 사용하면 상호 보완적인 작용을 유발하여 웨이퍼 전체적인 평탄도를 증대시킬 수 있다.By using the deposition properties of the BPSG film and the HDP oxide film, the BPSG film is used as the wordline interlayer insulating film and the HDP oxide film is used as the bitline interlayer insulating film as described in the above-described embodiment, thereby inducing a mutually complementary action to improve the overall flatness of the wafer. Can be increased.
첨부된 도면 도 5a 및 도 5b는 각각 비트라인 형성 후 층간절연막으로 HDP 산화막을 증착한 상태의 단면 SEM 사진으로, HDP 산화막 증착시 증착율이 높고 고주파 바이어스 파워가 낮은 경우 비트라인 간극에 보이드가 발생(도 5a 참조)하는 반면, HDP 산화막 증착시 증착율이 낮고 고주파 바이어스 파워가 높은 경우에는 비트라인 간극에 보이드가 발생하지 않음(도 5b 참조)을 확인할 수 있다. 즉, 증착율이 높으면 HDP 산화막 증착시 식각 작용이 상대적으로 활발해짐을 의미하며, 고주파 바이어스 파워를 증대시키면 챔버 바텀 쪽으로 증착 소오스 입자의 직진성이 증대되어 갭필링 특성이 개선되는 것이다.5A and 5B are cross-sectional SEM photographs in which HDP oxides are deposited as interlayer insulating films after bit line formation, respectively, and voids are generated in the bit line gaps when the deposition rate is high and the high frequency bias power is low when HDP oxides are deposited ( On the other hand, when the deposition rate is low and the high frequency bias power is high when the HDP oxide film is deposited, it can be seen that no void occurs in the bit line gap (see FIG. 5B). That is, a high deposition rate means that the etching operation becomes relatively active when the HDP oxide film is deposited. Increasing the high frequency bias power increases the straightness of the deposition source particles toward the bottom of the chamber, thereby improving the gap filling property.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
전술한 본 발명은 BPSG와 HDP 산화막의 증착 특성을 이용하여 웨이퍼 전체적인 평탄도를 향상시키는 효과가 있으며, HDP 산화막 증착시 증착 조건을 조절하여 비트라인 간극을 보이드 없이 매립할 수 있으며, BPSG 플로우를 위한 장시간의 열처리를 생략할 수 있어 열적 부담을 줄이는 효과가 있다.The present invention described above has the effect of improving the overall flatness of the wafer by using the deposition characteristics of the BPSG and HDP oxide film, it is possible to fill the bit line gap without voids by adjusting the deposition conditions during HDP oxide deposition, BPSG flow for Since the heat treatment for a long time can be omitted, there is an effect of reducing the thermal burden.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20040050517A (en) * | 2002-12-10 | 2004-06-16 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR20060073286A (en) * | 2004-12-24 | 2006-06-28 | 동부일렉트로닉스 주식회사 | Method and apparatus for manufacturing insulating layer with improved gap filling performance |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20040050517A (en) * | 2002-12-10 | 2004-06-16 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
| KR20060073286A (en) * | 2004-12-24 | 2006-06-28 | 동부일렉트로닉스 주식회사 | Method and apparatus for manufacturing insulating layer with improved gap filling performance |
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