KR20020014766A - Method for processing gray scale display of plasma display panel - Google Patents

Abstract

PURPOSE: A method for processing a display gray level of a plasma display panel(PDP) is provided, which enables to reduce an image quality degradation, by increasing a display gray level of the PDP. CONSTITUTION: According to the method, two adjacent unit display regions are set as a pair of display regions, among a number of unit display regions. If an analog image signal for the first and the second unit display region, the analog signal is converted into digital data of m bit respectively. And data of n bit larger than m are output by performing a compensation processing, as to digital data of m bit. And n bit data for the first and the second unit display region are divided into upper m bit data and lower (n-m) bit data. And the divided (n-m) bit data for the first and the second unit display region are added. And a fixed value is distributed as to the m bit data for the first and the second unit display region on the basis of the addition result. Then, by the processing result of the above, the distributed m bit data is output to a plasma display panel(150) to display a gray level.

Description

Display gradation processing method of plasma display panel {METHOD FOR PROCESSING GRAY SCALE DISPLAY OF PLASMA DISPLAY PANEL}

The present invention relates to a gradation display processing method of a plasma display panel in which a display gradation can be increased without increasing a subfield of a plasma display panel (PDP).

Fig. 1 is a block showing the configuration of a PDP device according to the prior art, which includes a level adjusting unit 1 for adjusting a level of an analog video signal x, and converting the level-adjusted video signal into 8-bit digital video data. An A / D conversion unit 2 for storing the 8-bit digital image data, and an r reverse correction unit 3 for performing r reverse correction operation, which is a reverse correction of r correction (gradation correction), and storing the digital image data. A synchronization signal is received from the frame memory 4, an output processor 5 for detecting digital image data stored in the frame memory 4, and outputting the detected digital image data to the plasma display panel 6, and the analog image signal x. A synchronous separation section 7 for separating, a timing pulse generation section 8 for generating timing pulses according to the synchronous signal, a memory control section 9 for controlling the frame memory 4 according to the timing pulses, and By the timing pulse, And a drive timing generator 10 for outputting a drive pulse to the PDP 6.

The operation of the PDP device configured as described above is as follows.

FIG. 2 is a configuration diagram showing an arrangement of subfields used in a conventional PDP apparatus. In order to implement gradation of image data, the PDP includes subfields SF1 to SF8 having different relative ratios of discharge sustaining periods in one frame period. ), And converts the input analog video signal x into a digital signal of the number of bits corresponding to the number of subfields, and then turns on the pixel corresponding to the converted digital signal by means of a suitable subfield to produce a predetermined gray level. Displays an image. The discharge holding period is proportional to the light emission luminance of the PDP.

In the example shown in Fig. 2, 256 grayscale images are displayed by eight grayscale bits. The most significant grayscale bit (8 bits) corresponds to SF1, and the next lower grayscale bit (7 bits) corresponds to SF2. The next lower gray bit (6 bits) to SF3, the next lower gray bit (5 bits) to SF4, the next lower gray bit (4 bits) to SF5, and the next lower gray bit (3 bits) to SF6. The next lower gray level bits (2 bits) correspond to SF7, respectively, and the lowest gray level bits (1 bit) correspond to SF8.

Since each discharge sustain period of each of the subfields SF1 to SF8 corresponds to the number of gray levels, 128, 64, 32, 16, 8, 4, 2, and 1 are added to the subfield, respectively. In order to make it good, light emission luminance is comprised in order.

As described above, when gray scale display is performed on the PDP, r reverse correction, which is reverse correction of r correction (gradation correction), is performed in order to maintain compatibility with light emission characteristics of the CRT.

That is, the level of the analog input video signal x is adjusted by the level adjusting section 1, converted into 8-bit digital video data by the A / D conversion section 2, and then the 8-bit r reverse correction section 3 R is corrected by r) and output to the PDP 6 via the frame memory 4 and the output processing section 5.

As described above, when r inverse correction, which is the inverse correction of the gradation correction, is performed on the digital image data, there is a problem that the display gradation of the low luminance portion of the display image displayed on the PDP 6 is remarkably lowered and the image quality deteriorates. have.

The above problem can be solved by increasing the display gradation of the PDP from 256 to 512 gradations. However, as the display gradation increases as described above, the number of subfields increases, so that the increasing luminance decreases, and as the number of light emitting pulses in the subfields increases, a fairy tale-like contour (fairy-tale fake outline), for example, a human's cheek, becomes smooth. There is a problem in that image quality deterioration occurs, such as a phenomenon in which gray scales are disturbed in a changing part.

SUMMARY OF THE INVENTION The present invention provides a gray scale display processing method of a plasma display panel in which the display gray scale of a PDP is increased to reduce image quality deterioration such as moving picture contours without increasing the subfields in order to solve the above problems. Is in.

The present invention provides a device having a PDP composed of a plurality of unit display areas (pixels), the first step of setting two adjacent unit display areas as a pair of display areas, and a pair of display areas. When the analog video signals for the first and second unit display areas constituting the second video signal are input, the second step of converting m (m is a positive integer) bits into digital data, respectively, and the converted m bits of digital data And a third step of performing a predetermined correction process and outputting n (n is a positive integer larger than m and being nm <m) bits as data, and n-bit data for the first and second unit display areas. A fourth step of dividing the upper m-bit data and the lower (nm) bit data, a fifth step of adding (nm) bit data for the divided first and second unit display regions, and the addition First and second based on the results And a sixth step of distributing a predetermined value to the m-bit data for the unit display area of the &lt; RTI ID = 0.0 &gt; and &lt; / RTI &gt; a seventh step of outputting the m-bit data based on the processing result of the sixth step to the PDP for grayscale display.

1 is a block diagram showing a configuration of a PDP apparatus according to the prior art.

2 is a configuration diagram showing an arrangement of subfields used in a conventional PDP apparatus.

3 is a block diagram showing the configuration of a PDP apparatus according to the present invention;

4 is a block diagram showing details of a rounding part of FIG. 3;

Fig. 5 is a block diagram showing an operation configuration of an adjacent pixel for processing display gradations of a PDP apparatus according to the present invention.

Explanation of symbols on main parts of drawings

100: level adjustment unit 110: A / D conversion unit

120: region correction unit 130: frame memory

140: output processing unit 150: plasma display panel (PDP)

151: area of adjacent pixels A and B 160: rounding part

161,163,166: Adder 162, 164: Delayer

165 control unit 170 synchronization separation unit

180: timing pulse generator 190: memory controller

200: drive timing generator y: input signal

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing the configuration of a PDP according to the present invention.

PDP 150 for displaying the input video signal, level adjusting unit 100 for adjusting the level of the analog video signal y, and A / D conversion for converting the level-adjusted video signal into 8-bit digital video data. The unit 110 and the 8-bit digital image data A / D converted from the A / D converter 110 perform r inverse correction operation, which is the inverse correction of the gradation correction (r correction), R inverse correction unit 120 for outputting as data, a frame memory 130 for storing the digital image data, an output processor 140 for outputting digital image data of the frame memory 130 to the PDP 150; And a synchronization separator 170 for separating the synchronization signal from the analog image signal y, a timing pulse generator 180 generating a timing pulse based on the synchronization signal, and a frame memory based on the timing pulse. Save data to 130, and the frame memo A memory controller 190 for controlling data output from the output processor 140 at 130, a driving timing generator 200 generating a pulse for driving the PDP 150 based on the timing pulse; And a rounding unit 160 that performs predetermined arithmetic processing on the 10-bit data r-corrected from the r-reverse correction unit 120 and outputs the data to the frame memory 130 as 8-bit data image data. .

4 is a detailed block diagram illustrating the rounding unit of FIG. 3.

The rounding unit 160 includes adders 161, 163, and 166, delay units 162 and 164 for delaying data of 8 bits and 2 bits, respectively, using a FIFO memory element, and a controller 165. It is composed of

The operation of the PDP device configured as described above is as follows.

In FIG. 3, the A / D converter 110 converts the input video signal into 8-bit digital image data and outputs the r / D converter 120 to the r inverse compensator 120. The 8-bit digital video data is r-reverse corrected and output as 10-bit data. The output 10-bit data is divided into upper 8 bits and lower 2 bits of data by the rounding unit 160.

The lower 2 bits of data divided by the rounding unit 160 are divided into lower 2 bits of adjacent pixels A and B in the PDP 150 and added.

According to the result of adding the lower two bits of data, the rounding unit 160 adds a value of 0 to the pixels A and B, a method of adding a value of 1 to only the pixel A, and a pixel A and B, respectively. Select and add 1 to output.

That is, when the 10-bit pixels A and B data r-corrected by the r inverse corrector 120 are sequentially input to the rounding unit 160, the lower 2 bit data corresponding to the divided pixel A is delayed by the delay unit 164. After a delay of approximately one pixel in, the input is input to the adder 166 simultaneously with the lower two-bit data of the pixel B.

Meanwhile, the upper 8-bit data of the divided pixel A is added to the adder 163 after being delayed by one pixel by the delay unit 162 by the adder 161 and the upper 8-bit data of the pixel B is simultaneously input. It is input to the adder 161.

That is, the time when the upper 8 bit data of the pixel A is input to the adder 163, the time when the upper 8 bit data of the pixel B is input to the adder 161, and the lower 2 bits of each of the pixels A and B, respectively. The time that data is input to the adder 166 is the same.

The adder 166 adds the lower two-bit data of the pixels A and B and outputs them to the controller 165.

The control unit 165, if the range of the addition result value of the lower two-bit data output from the addition unit 166 is, for example, within the range of (000 to 001), to each of the adding units 161 and 163. By outputting a zero value, the adjacent pixels A and B are controlled so that a zero value is added to the upper 8 bit data. In other words, no other value is added to the data of the adjacent pixels A and B, respectively.

Subsequently, if the range of the addition result of the adding unit 166 is within the range of (010 to 101), the control unit 165 outputs a value of 0 to the adding unit 161 and at the same time, adds to the adding unit 163. A value of 1 is output to control the value 0 to be added to the upper 8 bit data of the adjacent pixel B, and the value 1 is added to the upper 8 bit data of the adjacent pixel A. Therefore, only the data of the adjacent pixel A is added.

If the range of the addition result of the lower two-bit data of the adding unit 166 is within the range of (110 to 111), the control unit 165 adds one value to each of the adding units 161 and 163. The output is controlled so that 1 value is added to the upper 8 bit data of both adjacent images A and B. FIG.

As described above, the 10-bit data of the pixel A and the pixel B adjacent to the pixel A corrected by the r inverse correction unit 120 are divided into upper 8-bit data and lower 2-bit data, and at the same time, the pixel A And adding each of the lower two bit data to the pixel B, adding the lower eight bit data to each of the added pixels A and B, and then outputting the added eight bit digital image data to the frame memory 130. By outputting to the PDP 150 via the processing unit 140, the gradation display corresponding to 9 bits can be performed by the 8-bit gradation signal. In addition, since there is no need to increase the subfield, a high quality image can be obtained by doubling the display gradation without lowering the maximum luminance of the PDP 150.

5 is a configuration diagram showing an operation configuration of an adjacent pixel for processing display gradations of a PDP apparatus according to the present invention.

The adjacent pixels A and B in the predetermined region 151 of the PDP 150 are elements that delay the time of one pixel of the delay units 162 and 164, that is, when the pixel is a pixel delay element. As shown in (a) of FIG. 3, there are pairs of horizontally adjacent pixels. In addition, when the elements of the delay units 162 and 164 are elements that delay the time for one horizontal line, that is, a line delay element, as shown in FIG. Becomes a pair of. In addition, when the elements of the delay units 162 and 164 are elements that delay one frame time, that is, a frame delay element, as shown in FIG. .

Also, as shown in Fig. 3B, by rotating the pixels A and B alternately in line, deterioration in image quality due to the moving picture false contour generated when the portion where the gradation gradually changes is shifted may be reduced, As shown in Fig. 3C, by shifting the position of the pixel A to which one value is added, deterioration of the accuracy of the image and generation of flicker can be prevented.

As described above, the present invention is a device having a PDP composed of a plurality of unit display regions (pixels), wherein two adjacent unit display regions of a plurality of unit display regions are set as a pair of display regions, and a pair of Analog video signals for the first and second unit display areas constituting the display area are input and converted into m-bit digital data, respectively, and predetermined correction processing is performed on the converted m-bit digital data. While outputting as n-bit data larger than m, n-bit data for the first and second unit display areas are respectively divided into upper m-bit data and lower (nm) bit data, and the divided first And (nm) bit data for the second unit display area are added, and predetermined values are distributed to the first and second unit display area m-bit data based on the addition result and output to the PDP. As a result, the display gradation can be increased without increasing the subfields of the PDP, thereby preventing the degradation of the increased luminance of the PDP and reducing the degradation of image quality such as a moving picture-like outline.

Claims (3)

A display apparatus for performing gradation display of a plasma display panel composed of a plurality of unit display regions, A first step of setting two adjacent unit display regions as a pair of display regions among the plurality of unit display regions; A second step of converting m (m is positive integer) bits into digital data when the analog video signals for the first and second unit display areas constituting the pair of display areas are input; Performing a predetermined correction process on each of the converted m-bit digital data and outputting n (n is a positive integer) bit larger than m as data; Dividing the output n-bit data for the first and second unit display regions into upper m-bit data and lower (n-m) bit data, respectively; A fifth step of adding the divided (n-m) bit data for the divided first and second unit display areas; A sixth step of allocating a predetermined value with respect to the m-bit data for the first and second unit display areas based on the addition result; And a seventh step of displaying the gray level by outputting the distributed m-bit data to the plasma display panel according to the sixth processing result. The method of claim 1, The sixth step includes a first mode in which a predetermined value is not allocated to m-bit data for the first and second unit display areas according to the addition result of the fifth step, and m-bit data for the first unit display area. Selects a second mode for allocating one value to the predetermined value, and a third mode for allocating one value to the predetermined value with respect to the m-bit data for the first and second unit display areas. A gradation display processing method of a plasma display panel, characterized in that the. The method of claim 1, The sixth step may include a first unit display area in which one value is allocated to an adjacent pixel of the plasma display panel in which a plurality of unit display regions are provided for each of a plurality of lines, and a second unit display in which one value is not allocated. And replacing the area for each line to process the gradation display.