JP2002072956A - Gray shades display processing method for plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce deterioration of picture quality such as a pseudo contour of a moving picture by increasing gray scales of a PDP without increasing sub-fields used for gray shades display of the PDP. SOLUTION: When analog video signals for two adjoining pixels A, B in the PDP are inputted, each of them is converted into an 8-bit digital data, and the converted 8-bit digital data is subjected to a prescribed correction, then outputted as the 10-bit data. The 10-bit data for the pixels A, B are divided into higher order 8-bit data and lower order 2-bit data; and the 2-bit data for the divided pixels A, B are added to each other, then a prescribe value is distributed to the 8-bit data of the pixels P, A, B based on the result of the addition. Thus, the gray shades display equivalent to 9-bits is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gradation display processing method for a plasma display panel.

[0002]

2. Description of the Related Art Plasma display panels (hereinafter referred to as P
In DP), one frame period is composed of a plurality of subfields SF1 to SF8, each having a different relative ratio of a lighting period (sustain discharge period; proportional to light emission luminance). Then, the input analog video signal is converted into a digital signal having the number of bits corresponding to the number of subfields by A / D conversion, and a corresponding pixel is turned on by an appropriate subfield based on the bit data to thereby perform a predetermined operation. A gradation image is displayed. The example of FIG. 5 is an example in which 256 grayscale display is performed by eight grayscale bits. The highest grayscale bit (eighth bit) corresponds to SF1, and the grayscale bits (7 bit Eye) to SF2, gradation bit (sixth bit) to SF3, gradation bit (fifth bit)
Corresponds to SF4, the gradation bit (the fourth bit) corresponds to SF5, the gradation bit (the third bit) corresponds to SF6, and the gradation bit (the second bit) corresponds to SF7. The first bit) corresponds to SF8.

In each of the subfields SF1 to SF8, the sustain discharge period has a gray scale number (relative ratio of light emission luminance:
128, 64, 3 (proportional to the number of light emission pulses (sustain pulses))
2, 16, 8, 4, 2, 1, and the display efficiency is considered to be the best when arranged in the order of the emission luminance as shown in FIG. 5, and each of these 256-gradation subfields SF1 to SF8 Is displayed based on the PDP.

[0004]

A PDP for performing gradation display
In order to maintain compatibility with the light emission characteristics of a CRT, a correction called γ reverse correction, which is a reverse correction of γ correction (tone correction), is performed. That is, as shown in FIG. 4, after the analog input video signal a is level-adjusted by the level adjustment unit 11 and further converted into 8-bit digital video data by the 8-bit A / D conversion unit 12, the 8-bit γ is converted. The γ is inversely corrected by the inverse correction unit 19 and output to the PDP 100 via the frame memory 13 and the output processing unit 14.

As described above, when the γ inverse correction indicating the inverse correction of the gradation correction is performed on the digital video data, the PDP
A problem occurs in that the display gradation of a low-luminance portion of the display image displayed on the display 100 is significantly reduced, which leads to deterioration of image quality. In order to avoid such image quality degradation, it is conceivable to double the display gray scale from 256 gray scales to 512 gray scales. However, when the display gray scale is increased, the number of sub-fields increases, so that the maximum luminance decreases. Moving image false contour (moving image false contour; a phenomenon in which gradation is disturbed in a smoothly changing portion such as a cheek of a person) due to an increase in the number of light emission pulses in a subfield. ) Occurs.

Accordingly, it is an object of the present invention to increase the display gradation without increasing the number of subfields and to reduce the deterioration of image quality such as a false contour of a moving image.

[0007]

SUMMARY OF THE INVENTION To solve such a problem, the present invention relates to a device having a PDP composed of a plurality of unit display areas (pixels). When an analog video signal for a first unit display area and a first step for setting one unit display area as a pair of display areas and an analog video signal for the first and second unit display areas forming the pair of display areas are input, m (m is a positive A second step of converting into (integer) bits of digital data, and performing a predetermined correction process on the m-bit digital data converted based on the processing of the second step to obtain n larger than m.
(N is a positive integer and nm−m <m) bits are output as a third step, and the n-bit data for the first and second unit display areas are converted to upper m-bit data and lower m-bit data, respectively. (N−m) -bit data
A fifth step of adding the (nm) bit data for the divided first and second unit display areas, and a first and second step based on the addition result of the fifth step.
A sixth step of allocating a predetermined value to the m-bit data for the unit display area, and a seventh step of outputting m-bit data based on the processing result of the sixth step to the PDP to perform gradation display And

The processing in the sixth step includes a first mode in which a predetermined value is not distributed to m-bit data for the first and second unit display areas based on the addition result in the fifth step. A second mode in which a value “1” is distributed as the predetermined value to the m-bit data for the first unit display area, and a value “1” to the m-bit data for the first and second unit display areas The method includes a process of selecting any one of the third modes to be distributed as the predetermined value. Also, the PDP is provided with a plurality of unit display areas for each of a plurality of lines, and the first step is a first unit display area to which the value “1” is allocated and a second unit display area to which the value “1” is not allocated. And a seventh step of performing a process of exchanging the unit display area for each line.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a PDP (plasma display panel) device to which the present invention is applied. In FIG. 1, the present PDP device is a PDP 100
And an A / D converter 1 for converting the level-adjusted video signal into digital video data, and a level adjuster 11 for adjusting the level of the input analog video signal a.
2 and a frame memory 1 for storing digital video data
3 and the digital video data in the frame memory 13
An output processing unit 14 for outputting to P100, a synchronization separation unit 15 for separating a synchronization signal from the analog video signal a, a timing pulse generation unit 16 for generating a timing pulse based on the synchronization signal, and a frame memory based on the timing pulse A memory control unit 17 for controlling the accumulation of data in the memory 13 and the output of data from the frame memory 13 to the output processing unit 14;
It has a drive timing generator 18 for generating a drive pulse of P100.

The PDP apparatus also performs γ inverse correction, which is the inverse correction of gradation correction (γ correction), on the 8-bit digital video data A / D converted by the A / D converter 12. The γ inverse correction unit 19 that performs the correction operation and outputs it as 10-bit data, and performs predetermined arithmetic processing shown in FIG. And a rounding section 20 for outputting to the frame memory 13 as bit data video data.

FIG. 2 is a block diagram showing the configuration of the rounding section 20. The rounding unit 20 includes the adding unit 2
1 to 23; delay units 24 and 25 each configured by a FIFO memory element and delaying data of 8 bits and 2 bits; and a control unit 26. By the way, the 8-bit digital video data A / D converted by the A / D converter 12 is converted into γ as described above.
The inverse correction unit 19 performs the γ inverse correction operation and outputs the result as 10-bit data. The rounding unit 20 divides the 10-bit data into upper 8 bits and lower 2 bits as shown in FIG. Here, the divided lower 2 bits of data are respectively assigned for lower 2 bits of adjacent pixels A and B in the PDP 100, and are added.

Then, the following three outputs (1) to (3) are selected from the addition result of the lower two-bit data. (1) Both pixels A and B add "0". (2) “1” is added only to the pixel A. (3) Add “1” to both pixels A and B.

That is, assuming that the 10-bit data for pixel A and the data for pixel B, which have been γ-inversely corrected by the γ-inverse correction unit 19, sequentially arrive at the rounding unit 20.
The lower two-bit data for the divided pixel A is supplied to the delay unit 25.
, And is input to the adder 23 simultaneously with the lower two-bit data for the pixel B. On the other hand, the divided high-order 8-bit data for pixel A is delayed by the delay unit 24 by one pixel via the addition unit 21 and then delayed by the addition unit 22.
Is input to At this time, the upper 8-bit data for pixel B is input to the adder 21 at the same time. That is, the timing at which the upper 8-bit data for pixel A is input to the adder 22, the timing at which the upper 8-bit data for pixel B is input to the adder 21, and the timing at which the lower 8-bit data for pixel A and pixel B are input.
The timing at which the bit data is input to the adder 23 is the same timing.

The adder 23 adds the lower two-bit data for the pixels A and B and outputs the result to the controller 26. Here, if the range of the result of addition of the lower two-bit data by the adding unit 23 is, for example, in the range of “000 to 001”, the control unit 26 sets “0” to both of the adding units 21 and 22. Then, control is performed so that the value “0” is added to the upper 8-bit data for both the adjacent images A and B. That is, in this case, addition is not performed on each data of the adjacent images A and B.

If the range of the addition result of the adding section 23 is, for example, within the range of “010 to 101”, the control section 26 outputs “0” to the adding section 21 and outputs the “0” to the adding section 22. Is controlled so that the value “0” is added to the upper 8 bit data of the adjacent image B, and the value “1” is output to the upper 8 bit data of the adjacent image A. Is controlled to be added. That is, in this case, the addition is performed only on the data of the adjacent image A. Further, the control unit 26 outputs “1” to both of the adding units 21 and 22 if the range of the addition result of the lower two-bit data by the adding unit 23 is within the range of “110 to 111”, for example. Then, control is performed so that the value “1” is added to the upper 8 bits of data for both the adjacent images A and B.

As described above, the 10-bit data for the pixel A and for the pixel B adjacent to the pixel A, which has been subjected to the γ-inverse correction from the γ-inverse correction unit 19, are converted into the upper 8-bit data and the lower 2-bit data.
Bit data and the lower 2 bits of data for pixels A and B are added, and a value based on the addition result is added to the upper 8 bits of data for pixels A and B, respectively. By outputting to the PDP 100 through the frame memory 13 and the output processing unit 14 as 8-bit digital video data,
With a gray scale signal of bits, gray scale display corresponding to 9 bits can be performed. Further, since there is no need to increase the number of subfields, a high-quality image can be obtained by doubling the display gradation without lowering the maximum luminance of the PDP 100.

FIG. 3 is a diagram showing an example of adjacent pixels to be processed by the rounding unit 20 of FIG. PDP10
The adjacent pixels A and B in the predetermined area 101 of 0
4, 25 elements are pixel (Pixel) delay elements (1
In the case of an element that delays the time for a pixel), a pair of horizontally adjacent pixels as shown in FIG. The adjacent pixels A and B in the predetermined area 101 are shown in FIG. 3B when the elements of the delay units 24 and 25 are line delay elements (elements that delay the time of one horizontal line). It becomes a pair of vertically adjacent pixels as shown. Further, adjacent pixels A and B are
When the elements of the delay units 24 and 25 are frame delay elements (elements that delay one frame time), FIG.
A pair of pixels adjacent to the frame as shown in FIG.

As shown in FIG. 4B, the pixels A,
By inverting the lines B alternately, it is expected that the deterioration of the image quality called the false contour of the moving image, which occurs when the portion where the gradation changes gradually, moves. Further, as shown in FIG. 4B, by shifting the position of the pixel A to which “1” is added, it is possible to prevent the deterioration of image definition and the occurrence of flicker.

[0019]

As described above, according to the present invention, in an apparatus having a PDP composed of a plurality of unit display areas (pixels), two or more adjacent unit display areas (pixels) are used.
When one unit display area is set as a pair of display areas, and analog video signals for the first and second unit display areas constituting the pair of display areas are input, they are converted into m-bit digital data and converted. The predetermined m-bit digital data is subjected to a predetermined correction process and output as n-bit data larger than the m, and the n-bit data for the first and second unit display areas are respectively converted to the upper m bits. Data and lower-order (nm) bit data, and (n) for the divided first and second unit display areas.
-M) Bit data is added, and a predetermined value is allocated to m-bit data for the first and second unit display areas based on the addition result and output to the PDP, so that the number of subfields is increased. Thus, the display gradation can be increased without causing a decrease in the maximum luminance of the PDP, and the image quality deterioration such as a false contour of a moving image can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a PDP device to which the present invention has been applied.

FIG. 2 is a block diagram showing a main configuration of the PDP device.

FIG. 3 is a diagram illustrating an operation of a main part of the PDP device.

FIG. 4 is a block diagram showing a configuration of a conventional PDP device.

FIG. 5 is a diagram showing an arrangement configuration of subfields used in a PDP device.

[Explanation of symbols]

11: Level adjustment unit, 12: A / D conversion unit, 13: Frame memory, 14: Output processing unit, 15: Synchronization separation unit, 1
6 timing pulse generator 17 memory controller 1
8: drive timing generation unit, 19: γ inverse correction unit, 20:
Rounding parts, 21 to 23 ... addition parts, 24, 25 ...
Delay unit, 26 Control unit, 100 Plasma display panel (PDP), 101 Area of adjacent pixels A and B, a
... Input video signal.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/66 101 G09G 3/28 K

Claims (3)

[Claims] 1. A display device having a plasma display panel composed of a plurality of unit display areas and performing a gradation display of the plasma display panel, wherein two adjacent unit display areas of the plurality of unit display areas are provided. A first step of setting as a pair of display areas; and inputting analog video signals for the first and second unit display areas constituting the pair of display areas, respectively.
(M is a positive integer) a second step of converting into digital data of bits, and a predetermined correction process is performed on the m-bit digital data converted based on the processing of the second step to perform a larger correction than the m. a third step of outputting n-bit (n is a positive integer) bit data, and n-bit data for the first and second unit display areas are respectively upper m-bit data and lower (nm) bits A fourth step of dividing the data into data and (nm) for the divided first and second unit display areas.
A fifth step of adding bit data, a sixth step of allocating a predetermined value to the m-bit data for the first and second unit display areas based on the addition result of the fifth step, A seventh step of outputting m-bit data based on the processing result of the step to the plasma display panel to perform a gray scale display, and performing a gray scale display. 2. The processing according to claim 1, wherein the processing in the sixth step is performed based on an addition result in the fifth step.
A first mode in which a predetermined value is not allocated to the m-bit data for the unit display area, a second mode in which a value “1” is allocated as the predetermined value to the m-bit data for the first unit display area, and A plasma display panel comprising a process of selecting any one of a third mode in which a value "1" is allocated as the predetermined value to m-bit data for the first and second unit display areas. Gradation display processing method. 3. The plasma display panel according to claim 2, wherein the plasma display panel is provided with a plurality of unit display areas for each of a plurality of lines, and the first step is a first unit display in which a value “1” is distributed. 8. A gradation display processing method for a plasma display panel, comprising an eighth step of performing a process of exchanging, for each line, an area and a second unit display area to which a value “1” is not distributed.