KR20020014546A - Multi layer metal interconnection and method of manufacturing the same - Google Patents
Multi layer metal interconnection and method of manufacturing the same Download PDFInfo
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- KR20020014546A KR20020014546A KR1020000047887A KR20000047887A KR20020014546A KR 20020014546 A KR20020014546 A KR 20020014546A KR 1020000047887 A KR1020000047887 A KR 1020000047887A KR 20000047887 A KR20000047887 A KR 20000047887A KR 20020014546 A KR20020014546 A KR 20020014546A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 101
- 239000002184 metal Substances 0.000 title claims abstract description 101
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010410 layer Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 238000012360 testing method Methods 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010835 comparative analysis Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 비아홀(Via hole)을 통해 전기적으로 접촉되는 다층 금속배선 형성시, 비아홀의 오픈블량이나 비아홀의 환경을 측정하기 위한 다층 금속배선 및 그의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a multilayer metal wiring for measuring the openable amount of a via hole or an environment of a via hole, when forming a multilayer metal wiring in electrical contact through a via hole. It is about.
일반적으로 반도체 제조 공정에서 주로 사용되는 금속으로는 소자간의 전기적 연결을 위해 금속증착에 쓰이는 알루미늄 성분이 주로 이용되고, 상기 알루미늄은 실제로 소자와의 전기적 연결에 사용되는 금속부분만을 남기고 나머지 부분이 제거시킴으로써 금속배선이 형성된다.In general, as the metal mainly used in the semiconductor manufacturing process, an aluminum component used for metal deposition is mainly used for electrical connection between devices, and the aluminum is actually removed by leaving only the metal part used for electrical connection with the device. Metal wiring is formed.
그리고, 상기 금속배선을 상부의 다른 금속배선과 연결하기 위해 다층의 층간절연막을 적층하고, 상기 다층의 층간절연막 상에 하부 금속배선을 노출시키는 비아홀을 형성함으로써 상부의 다른 금속배선과의 연결을 위한 전기적 통로가 형성된다.In addition, the multilayer interlayer insulating film is laminated in order to connect the metal wiring with another metal wiring on the upper side, and a via hole for exposing the lower metal wiring on the multilayer interlayer insulating film is formed for connection with other metal wiring on the upper side. An electrical passage is formed.
최근에는, 고집적화된 메모리 소자나 주문형 반도체(ASIC; Application Specific Intergrated Circuit)의 대부분은 2층 이상의 금속배선을 이용하며, 5 층 이상의 금속배선을 이용하는 소자도 개발되고 있다.Recently, most of highly integrated memory devices and application specific integrated circuits (ASICs) use two or more metal wirings, and devices using five or more metal wirings have also been developed.
상기와 같이 금속배선층이 증가함에 따라 초기 반도체소자에서는 발생되지 않았던 문제점이 발생하고 있는데, 그 중 다층 금속 배선 공정시 금속 배선간의 전기적 접촉을 이루는 통로인 비아홀의 신뢰성이 저하되는 문제점이 발생되어 소자의 수율을 저하시킨다.As the metal wiring layer increases as described above, there is a problem that did not occur in the initial semiconductor device. Among them, the reliability of the via hole, which is a passage for making electrical contact between the metal wires, is degraded during the multilayer metal wiring process. Lowers the yield.
도 1은 종래기술에 따라 형성된 3층 금속배선의 평면도로서, 직사각형 형태의 제 3 층 금속배선만이 도시되어 있다.1 is a plan view of a three-layer metal wiring formed according to the prior art, in which only the third-layer metal wiring in a rectangular form is shown.
도 2는 도 1에 도시된 3층 금속배선의 형성 방법을 도시한 도면으로서, 소정공정이 완료된 반도체기판(11)상에 제 1 금속배선(12)을 형성한 후, 상기 제 1 금속배선(12)상에 제 1 층간절연막(13)을 형성하고, 상기 제 1 층간절연막(13)을 선택적으로 패터닝하여 후속 제 2 금속배선과 상기 제 1 금속배선(12)과의 전기적 통로인 비아홀을 오픈시킨다.FIG. 2 is a diagram illustrating a method of forming the three-layer metal wiring shown in FIG. 1, after forming a first metal wiring 12 on a semiconductor substrate 11 on which a predetermined process is completed. A first interlayer insulating film 13 is formed on the substrate 12, and the first interlayer insulating film 13 is selectively patterned to open a via hole, which is an electrical path between the second metal wiring and the first metal wiring 12. Let's do it.
이어서, 상기 비아홀에 매립되는 제 2 금속배선(14)을 형성한 후, 상기 제 2 금속배선(14)상에 제 2 층간절연막(15)을 형성하고, 상기 제 2 층간절연막(15)을 선택적으로 패터닝하여 후속 제 3 금속배선과 상기 제 2 금속배선(14)의 전기적 통로인 비아홀을 오픈시킨다.Subsequently, after forming the second metal wiring 14 buried in the via hole, a second interlayer insulating film 15 is formed on the second metal wiring 14, and the second interlayer insulating film 15 is selectively formed. Patterning to open a via hole, which is an electrical passage between the subsequent third metal wiring and the second metal wiring 14.
계속해서, 상기 노출된 비아홀에 매립되는 제 3 금속배선(16)을 형성한다.Subsequently, a third metal wiring 16 buried in the exposed via hole is formed.
이 때, 상기 제 1, 2 층간절연막(13, 15)은 산화막(Inter Metal Oxide; IMO), SOG(Spin On Glass), 산화막(IMO)의 적층막으로 이루어진다.In this case, the first and second interlayer insulating films 13 and 15 may be formed of a laminated film of an intermetal oxide (IMO), a spin on glass (SOG), and an oxide film (IMO).
상술한 종래기술에 의하면, 각층 금속간의 평탄화를 위해 이용하는 SOG를 포함한 층간절연막을 식각하여 비아홀을 형성할 때, 무기물에 의한 비아홀(Via hole)내의 바우잉(Bowing) 효과에 의해 비아홀의 오픈 불량이 발생하고, 이에 의해 비아홀 측벽을 음성적인 라운드 프로파일(Round profile)로 만들어 금속배선과 금속배선간의 오픈을 유발한다.According to the above-described prior art, when the via hole is formed by etching the interlayer insulating film containing SOG used for planarization between the metals, the via hole is opened due to the bowing effect in the via hole by the inorganic material. This causes the via hole sidewalls to become a negative round profile, causing the opening between the metal wiring and the metal wiring.
또한, 반도체소자의 배선층이 증가하면서 코아셀(Core cell)과 주변회로간의단차에 의하여 금속배선의 패드 부분에서는 최악의 비아홀 환경을 형성하게 되고, 이는 금속배선 공정후 후속공정의 재료들의 특성에 의하여 더욱 나쁜 환경이 된다.In addition, as the wiring layer of the semiconductor device increases, the worst-case via hole environment is formed in the pad portion of the metal wiring due to the step between the core cell and the peripheral circuit, which is caused by the characteristics of the material of the subsequent process after the metal wiring process. It is a worse environment.
이와 같은 비아홀의 오픈 블량이나 비아홀 환경을 측정하기 위해서, 종래기술에서는 일반적으로, 비아홀의 상태를 확인하기 위해 웨이퍼 테스트(Wafer test)를 전행한 후 문제가 발생된 비아홀의 단면을 주사전자현미경(Scanning Electron Microscope)이나 FIB를 이용하여 분석하였으나, 분석과정에서 문제를 초래할 수 있어 분석하기가 쉽지 않다. 또한, 비아홀의 문제점을 확인하기 위하여 제품과 제품 사이에 테스트패턴(Test pattern)을 삽입하여 비아홀 패턴을 검사하였으나, 이는 라인 공정이 완료되어야 가능하고 패턴이 작고 실제 코아셀(Core cell)과의 차이등에 의하여 정확한 정보를 확보하기가 어렵다.In order to measure the amount of via holes and the environment of via holes, in the prior art, after performing a wafer test to check the state of via holes, a scanning electron microscope (scanning) is performed on a cross section of the via hole where a problem occurs. Electron Microscope) or FIB, but the analysis can cause problems in the analysis is not easy to analyze. In addition, in order to check the problem of the via hole, a test pattern was inserted between the product and the product to test the via hole pattern. However, this is possible only when the line process is completed, the pattern is small, and the difference from the actual core cell. It is difficult to secure accurate information.
본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 다층 금속배선의 전기적 통로인 비아홀의 오픈불량이나 나쁜 환경에 따른 금속배선간의 전기적 특성을 정확하게 측정하는데 적합한 다층 금속배선 및 그의 제조 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the problems of the prior art, a multi-layer metal wiring suitable for accurately measuring the electrical characteristics between the metal wiring due to the poor or open environment of the via hole, which is an electrical passage of the multi-layer metal wiring and a method of manufacturing the same. The purpose is to provide.
도 1은 종래기술에 따른 다층 금속배선의 평면도,1 is a plan view of a multi-layered metal wiring according to the prior art,
도 2는 종래기술에 따른 다층 금속배선의 형성 방법을 도시한 도면,2 is a view showing a method of forming a multilayer metal wire according to the prior art;
도 3a 내지 도 3c는 본 발명의 실시예에 따른 3층 금속배선들의 패턴을 도시한 도면,3A to 3C illustrate a pattern of three-layer metal wirings according to an embodiment of the present invention.
도 4a 내지 도 4d는 본 발명의 실시예에 따른 3층 금속배선의 형성 방법을 도시한 도면.4A to 4D illustrate a method of forming a three-layer metal wiring according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 제 1 금속배선21 semiconductor substrate 22 first metal wiring
23 : 제 1 층간절연막 24 : 제 1 비아홀23: first interlayer insulating film 24: first via hole
25a, 25b : 제 2 금속배선 26 : 제 2 층간절연막25a, 25b: second metal wiring 26: second interlayer insulating film
27 : 제 2 비아홀 28a, 28b : 제 3 금속배선27: second via hole 28a, 28b: third metal wiring
상기의 목적을 달성하기 위한 본 발명의 다층 금속배선은 다층의 비아홀을 통해 전기적으로 접속된 다층의 금속배선의 주패턴; 및 상기 주패턴간의 전기적특성 및 상기 비아홀의 상태를 측정하기 위해 상기 주패턴 형성시 일정 간격을 갖고 동시에 형성된 서브패턴을 포함하여 이루어짐을 특징으로 하고, 본 발명의 다층 금속배선의 형성 방법은 반도체기판상에 제 1 금속배선을 형성하는 단계; 상기 제 1 금속배선을 노출시키는 비아홀을 형성하는 단계; 및 상기 비아홀에 매립되어 상기 제 1 금속배선과 접속되는 주패턴과 상기 주패턴과 소정간격 거리를 두고 형성되어 상기 제 1 금속배선과 주패턴간의 전기적특성을 측정하기 위한 서브패턴으로 이루어지는 제 2 금속배선을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The multi-layered metal wiring of the present invention for achieving the above object is a main pattern of the multi-layered metal wiring electrically connected through the multilayer via hole; And a subpattern formed at the same time with a predetermined interval when the main pattern is formed to measure the electrical characteristics between the main patterns and the state of the via hole. The method of forming a multilayer metal wiring according to the present invention includes a semiconductor substrate. Forming a first metal wire on the substrate; Forming a via hole exposing the first metal wiring; And a second metal embedded in the via hole, the main pattern connected to the first metal wiring, and a subpattern for measuring electrical characteristics between the first metal wiring and the main pattern at a predetermined distance from the main pattern. It characterized in that it comprises a step of forming a wiring.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 3a 내지 도 3c는 본 발명의 실시예에 따른 3층 금속배선의 패턴을 각각 도시한 평면도로서, 제 1 금속배선은 통상과 동일하게 직사각형의 패턴이며, 제 2 금속배선은 상기 제 1 금속배선에 오버랩되어 형성되고 상기 제 1 금속배선과 접속되는 비아홀을 제외한 영역에 소정간격 거리를 두고 기생 패턴들()이 형성된다.3A to 3C are plan views showing patterns of the three-layer metal wiring according to the embodiment of the present invention, wherein the first metal wiring is a rectangular pattern as usual, and the second metal wiring is the first metal wiring. The parasitic patterns () are formed at a predetermined distance apart from the via hole connected to the first metal wire and overlapped with each other.
그리고, 제 3 금속배선은 상기 제 2 금속배선에 오버랩되어 형성되고 상기 제 2 금속배선의 표면을 노출시키는 복수개의 비아홀을 통해 접속되며, 상기 제 3 금속배선도 복수개의 기생패턴들이 형성된다.The third metal wire is overlapped with the second metal wire and is connected through a plurality of via holes exposing the surface of the second metal wire, and the third metal wire is also formed with a plurality of parasitic patterns.
상술한 것처럼, 제 2, 3 금속배선을 비아홀을 통해 콘택되는 주패턴외에 기생패턴들을 형성하여 상기 비아홀을 통해 전기적으로 접속된 제 1,2,3 금속배선의 전기적 특성을 측정할 수 있다.As described above, parasitic patterns may be formed in addition to the main pattern in which the second and third metal wires are contacted through the via holes to measure electrical characteristics of the first, second and third metal wires electrically connected through the via holes.
도 4a 내지 도 4d는 본 발명의 실시예에 따른 3층 금속배선의 형성 방법을 도시한 공정 단면도이다.4A to 4D are cross-sectional views illustrating a method of forming a three-layer metal wiring according to an embodiment of the present invention.
도 4a에 도시된 바와 같이, 소정 공정이 완료된 반도체기판(21)상에 배선용 금속을 형성한 후, 선택적으로 패터닝하여 하부의 트랜지스터의 소스/드레인(도시 생략)과 연결되는 제 1 금속배선(22)을 형성한다. 이어서, 상기 제 1 금속배선(22)상에 산화막(IMO1)/SOG/산화막(IMO2)의 적층막으로 이루어진 제 1 절연막(23)을 형성한 후, 상기 제 1 절연막(23)상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 비아홀 마스크(도시 생략)를 형성한다.As shown in FIG. 4A, after the wiring metal is formed on the semiconductor substrate 21 having a predetermined process, the first metal wiring 22 is selectively patterned to be connected to a source / drain (not shown) of a lower transistor. ). Subsequently, a first insulating film 23 formed of a laminated film of an oxide film IMO1 / SOG / oxide oxide IMO2 is formed on the first metal wiring 22, and then a photosensitive film is formed on the first insulating film 23. It is applied and patterned by exposure and development to form a via hole mask (not shown).
계속해서, 상기 비아홀 마스크를 이용하여 하부의 제 1 절연막(23)을 식각하므로써 제 1 절연막(23) 하부의 제 1 금속배선(22)이 노출되는 제 1 비아홀(24)을 형성한 후, 상기 비아홀 마스크를 제거한다.Subsequently, the first insulating layer 23 under the first insulating layer 23 is formed by etching the lower first insulating layer 23 using the via hole mask to form the first via hole 24 through which the first metal wiring 22 is exposed. Remove the via hole mask.
도 4b에 도시된 바와 같이, 상기 제 1 비아홀(24)에 매립되는 제 2 금속배선(25a, 25b)을 형성하되, 상기 제 2 금속배선(25a, 25b)은 제 1 비아홀(24)을 통해 제 1 금속배선(22)과 전기적으로 접속되는 주패턴(25a)과 상기 주패턴(25a)에 일정간격 이격되어 후속 웨이퍼테스트시 제 1 비아홀 및 제 1 비아홀을 통해 전기적으로 접속되는 제 1 금속배선(22)과 제 2 금속배선의 주패턴(25a)의 전기적특성을 검출하기 위한 기생패턴(25b)으로 이루어진다.As shown in FIG. 4B, second metal wires 25a and 25b are formed in the first via hole 24, and the second metal wires 25a and 25b are formed through the first via hole 24. The first metal wire 25a electrically connected to the first metal wire 22 and the first metal wire 25 electrically spaced apart from the main pattern 25a by a first via hole and a first via hole during a subsequent wafer test. And a parasitic pattern 25b for detecting electrical characteristics of the main pattern 25a of the second metal wiring.
도 4c에 도시된 바와 같이, 상기 제 2 금속배선(25a, 25b)을 포함한 전면에 제 2 층간절연막(26)을 형성하고, 다른 비아홀마스크를 이용하여 상기 제 2 층간절연막(26)을 식각하여 하부의 제 2 금속배선(25a, 25b) 중 주패턴(25a)이 노출되는제 2 비아홀(27)을 형성한다. 이 때, 상기 제 2 비아홀(27)은 후속 제 3 금속배선과의 콘택을 위해 상기 제 2 금속배선의 주패턴상에 복수개 형성될 수 있다.As shown in FIG. 4C, the second interlayer insulating layer 26 is formed on the entire surface including the second metal wires 25a and 25b, and the second interlayer insulating layer 26 is etched using another via hole mask. A second via hole 27 in which the main pattern 25a is exposed is formed among the second metal wires 25a and 25b. In this case, a plurality of second via holes 27 may be formed on the main pattern of the second metal wiring to contact the third metal wiring.
도 4d에 도시된 바와 같이, 상기 제 2 비아홀(27)에 매립되는 제 3 금속배선(28a, 28b)을 형성하되, 상기 제 3 금속배선(28a, 28b)은 하부의 제 2 금속배선의 주패턴에 접속되는 부분과 상기 제 2 금속배선의 주패턴과 기생패턴을 전기적으로 접속시키는 부분으로 이루어진다.As shown in FIG. 4D, the third metal wires 28a and 28b are formed in the second via hole 27, and the third metal wires 28a and 28b are mainly formed on the lower second metal wires. And a part for electrically connecting the main part and the parasitic pattern of the second metal wiring to the part connected to the pattern.
상술한 바와 같이, 본 발명의 실시예를 이용하면, 다양화된 금속배선 패턴의 경우의 수에 따른 비교평가가 가능하고, 단일 금속배선에 대한 유용한 전기적인 정보, 즉, 금속배선간의 단락 정도, 금속배선 자체의 저항뿐만 아니라 패턴의 종류를 다양하게 가져감에 따라 다양한 경우의 금속배선간의 전기적인 정보를 쉽고 빠르게 확인할 수 있다.As described above, using the embodiments of the present invention, it is possible to make a comparative evaluation according to the number of cases of the diversified metallization patterns, and useful electrical information about the single metallization, that is, the degree of short circuit between the metallizations By bringing various kinds of patterns as well as resistance of the metal wiring itself, it is possible to quickly and easily check the electrical information between the metal wirings in various cases.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 바와 같은 본 발명의 다층 금속배선의 형성 방법은 비아홀을 통해 접속되는 금속배선의 형태를 다양하게 하므로써, 다층 비아홀을 통해 전기적으로 접속되는 다층 금속배선의 전기적 특성 및 비아홀의 특성을 웨이퍼 테스트시 정확하고 신속하게 측정할 수 있으므로 소자의 제조시간을 단축시키고 수율을 향상시킬 수 있는 효과가 있다.As described above, the method of forming the multi-layered metal wiring of the present invention can vary the shape of the metal wires connected through the via-holes, thereby testing the electrical characteristics and the characteristics of the via-holes electrically connected through the multi-layer via-holes. Accurate and rapid measurement can reduce the manufacturing time of the device and improve the yield.
Claims (4)
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