KR20020014151A - Apparatus and method for processing control signal between atm switch and router - Google Patents

Abstract

PURPOSE: A device for processing control signaling between an ATM switch and a router is provided to monitor control signals by using FIFO when the ATM switch and the router are remotely connected, so as to prevent the control signals from being lost. CONSTITUTION: A header converter(233) analyzes header information of data received from a switch(202) to separate data from control signals, and records the data in an FIFO(304), then transmits the control signals to a control signal controller(243). A control signal generator(213) generates each enable signal for informing the FIFO(304) of a data recording time and a data reading time. The control signal generator(213) generates appropriate signals with monitored information from the control signal controller(243). The control signal controller(243) monitors signals(ex, backpressure information) for informing of a self status that the switch(202) and a router(301) receive to each other. The control signal controller(243) informs the control signal generator(213) of the monitoring information, to make the generator(213) generate appropriate control signals.

Description

Control signaling processing device and method between AT switch and router {APPARATUS AND METHOD FOR PROCESSING CONTROL SIGNAL BETWEEN ATM SWITCH AND ROUTER}

The present invention relates to an asynchronous transfer mode system, and more particularly, to an apparatus and a method for processing control signaling for transmitting and receiving between a switch and a router using a FIFO.

In addition, the present invention ensures clock synchronization using the APO switch and the I / O cards that connect the ATM switch constituting the asynchronous transmission mode system by using a PIP at a remote connection It is to.

In the related art, when the A / M cards connecting the A / M switches are connected to the same back plane (near 30 cm) or the same back plane in the configuration of the system, the A / M device that cannot guarantee the synchronization of the clock When used, there is a way to use Pappo to ensure clock synchronization. 1 illustrates a remote connection apparatus using a PPO in an ATM system according to the prior art. As shown, the first backplane 1 includes a router 101 in charge of a cell routing function, a PIP 104 that is an input / output buffer of cells, and a PIP control unit 103 that controls the PIP 104. On the other hand, the second back plane (back plane2) is provided with a switch 102 in charge of cell switching, PIP 106 which is an input / output buffer of cells and a PIP control unit 106 for controlling the PIP 105. Here, the cover 104 and the cover 106 is used to ensure the synchronization of the clock.

As described above, the 'distance connection method using the packet' is a connection method without difficulty in terms of ensuring clock synchronization at both ends. However, when practically applied to the system, hardware (H / W) switching of the AT cell in the input / output card connected to the device for the AT switch and the switch for AT switching (H / W) Many problems arise if you do not take into account the control signals to and from the router, which adds routing taps and translates between virtual paths (VPs) and virtual channels (VCs). May occur. In the connection between the switch and the input / output card, the devices that are terminated in each of them and connected to each other are generally referred to as switch devices and routers. Therefore, the connection of the switch and the input / output card may be referred to as the connection of the switch device and the router. FIG. 1 is a diagram illustrating a connection between the switch and the input / output cards as a connection between the switch and the router. The switch 102 and the router 101 are located in different back plans. At each input end, there are blisters 104 and 106, which are controlled by the blister controller 103 and 105. Therefore, the data coming into the respective input stages are synchronized through the packets 104 and 106. Here, a problem that may occur when connecting the switch and the router using the PPO is that it is not possible to properly control the control signal for transmitting the status of each device.

3 illustrates a circuit capable of remote connection of a switch and a router according to the prior art. 3 illustrates a write logic unit 303 for storing data from a switch, a pico 304 for storing data from the write logic unit, a read logic unit 305 for storing data from the packet and outputting the data to the router 201. The clock driver 306, the SOC generator 307, and two flip-flops 308 and 309 are provided.

Referring to FIG. 3, when data received from the switch 202 is input to the write logic 203 of the PPO, the start cell of the data is first checked. When the start cell is confirmed, it is determined whether the data is valid data through the next header, and when it is determined that the start data is valid, the start cell of the data is recorded in the pico. At this time, since the header must be checked in order to input the data, the order of the data must be guaranteed by shifting the input data for two clocks. The data recorded in this manner creates an internal start cell in the SOC generator 307 two clocks before the start cell actually enters the router 201 to indicate when data is to be read from the PPO read logic 305. The data synchronized with the internal start cell are inputted to the router 201 after confirming various information about the router 202 in the read logic 305 (from the header). In this case, the more information input from the switch 202, the more time it takes to analyze the header, it is necessary to logic to shift the data. In addition, since the data after analyzing the header must be synchronized with the data input to the router 201, a start cell 2 clocks later than the internal start cell is created through the two flip-flops 308 and 309 and inputted to the router 201 with the data. Let's do it. Here, it is not absolute that the start cell to be input to the router 201 should be two clocks later than the internal start cell. Here, "two clocks" assumes that the start cell needs to be two clocks later than the internal start cell because the packet control assumes that the time required for the header conversion is two clocks. In fact, if the time taken to convert the header in the packet control unit is longer than 2 clocks, a delayed start cell must be created.

As mentioned above. Data and control information input from the switch are written by the capturing control unit and read again. In the related art, since the control signal is not monitored, the information contained in the control signal is not known to the control signal. However, it is not a big problem under the premise that all data and control information are recorded and read at the PPO. However, in general, the data processing speed of the router and the data processing speed of the switch are faster at the switch side. This is because, in ATM, the function of the router is to convert the header of the cell and add a routing tap, and the switch simply switches the data by decrypting only certain tap information of the header. Since the processing speeds are different as described above, in order to match the transfer rate, the switch generates idle data at a constant rate. In this case, in order to reduce the load of the router, the packet control unit of the router generally discards invalid data without writing it to the packet. Here, a problem arises if the packet control discards invalid data rather than user data just to match the transmission rate. In general, if the information exchanged between the switch and the router is a bottleneck, the performance of both devices can be greatly affected. For example, if a bottleneck occurs on a switch's port and the switch sends control information to the router that no longer sends data to the router, the router will hold the data for a certain amount of time to transmit to the switch. And then transmit so that the switch is free from bottlenecks. However, if the control signal to be transmitted is discarded by the packet controller because of invalid data generated to match the transmission rate in the switch, the switch cannot escape the bottleneck because there is no way for the router to recognize the state of the switch. That is, data loss will be increased in proportion to invalid data that is discarded.

Accordingly, an object of the present invention is to provide an apparatus and method for monitoring a control signal when a switch and a router are connected by using a PPO in an ATM system.

In order to achieve the above objects, a signaling processing device between ATM switch and router in ATM system analyzes header information from the received data and the packet for temporarily storing pure data, and transmits the control signal to the control signal controller. The pure data includes a header converter which stores the control signal, the control signal controller which analyzes the control signal from the header converter, and provides control information to a control signal generator, and a time point at which data is recorded and read in the packet. And a control signal generator for generating an enable signal for controlling and generating an internal control signal with the control information from the control signal controller.

1 is a view showing a remote connection device using a PPO in the AT switch according to the prior art.

2 is a view showing a remote connection apparatus using a cover according to an embodiment of the present invention.

3 is a diagram showing a circuit according to a remote connection of a switch and a router in the prior art.

4 is a diagram illustrating a circuit according to a remote connection of a switch and a router according to an embodiment of the present invention.

5 is a view for explaining a method of processing the second bottleneck information (router-> switch) according to an embodiment of the present invention.

6 is a diagram illustrating a pattern generation process of second bottleneck information (bp_in).

7 is a diagram illustrating a method of processing first bottleneck information according to an embodiment of the present invention.

8 is a diagram illustrating a pattern generation process of first bottleneck information (bp_out).

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding the reference numerals to the components of each drawing, the same components have the same reference numerals as much as possible even if displayed on different drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The present invention defines specific functional blocks of the canopy control unit shown in FIG. 1 to implement a function necessary for remote connection of two devices using a canopy, and to solve a problem that may occur when implementing such a function. The blanket control unit performs a function of controlling a blanket installed at each input terminal to ensure clock synchronization. Therefore, when the two devices are connected by using the Popo, the control unit generates a function block for generating an internal signal required, a control signal generation block (control signal generator, control signal controller) that monitors the control signal and generates an appropriate signal. It can be divided into a header conversion unit for processing.

2 is a view illustrating a remote connection apparatus using a covering according to an embodiment of the present invention. In particular, FIG. 2 shows a detailed configuration of the cover control unit. In the following description, it is assumed that data is transmitted from the switch to the router (switch-> router). Referring to FIG. 2, the header converter 233 analyzes header information received from the switch 202 into data and a control signal, records the data in the PPO 204, and the control signal is a control signal controller 243. To pass. The control signal generator 213 controls the signal signal 204 to generate an enable signal for notifying the signal to the time point at which data is written to the data signal 204 and the time point at which the data signal is read. Generates the appropriate signal with the information monitored by. The control signal controller 243 monitors a signal (for example, a bottleneck information) indicating the state of the switch 202 and the router 201, and transmits the monitoring information to the control signal generator 213. Inform them to generate appropriate control signals. This control signal is used as a signal for controlling the respective devices. Control signals exchanged between the switch 202 and the router 201 may vary from device to device. However, the control signal exchanged between the switch 202 and the router 201 is generally a bottleneck information such as "backpressure".

4 illustrates a circuit capable of remotely connecting a switch and a router according to an exemplary embodiment of the present invention. FIG. 4 shows a configuration different from that of FIG. 3 in that it monitors the backpressure. In the configuration, the write logic unit 403 for storing data from the switch 202, the PIO 404 for storing data from the write logic unit 403, the read logic 405 for storing data from the PPO 404, and additionally Data from the clock driver 407, the SOC generator 408, the two preflops 409 and 419, the parallel information generating unit 410, the bottleneck information monitoring unit 411 and the read logic unit 406 and the start cell from the preflop 419 and the And a logical summer 406 for inputting the bottleneck information from the bottleneck information monitoring unit 411 and outputting the logical result to the router 210.

Referring to FIG. 4, when data received from the switch 202 is input to the write logic 403 of the PPI, a start of cell (SOC) of the data is first checked. When the start cell is confirmed, it is determined whether the data is valid through the next header, and when it is determined that the start cell is valid, the start cell of the data is recorded in the PPO 404. At this time, since the header must be checked in order to input the data, the order of the data must be guaranteed by shifting the input data for two clocks. The recorded data creates an internal start cell at the SOC generator 408 two clocks before the start cell actually enters the router 201 to indicate when data is to be read from the PPO read logic 405. The data synchronized with the internal start cell is inputted to the router 201 through the logic summer 406 after confirming various information about the router 202 in the read logic 405 (from the header). In this case, the more information input from the switch 202, the more time it takes to analyze the header, it is necessary to logic to shift the data. In addition, since the data after analyzing the header must be synchronized with the data input to the router 201, a start cell 2 clocks later than the internal start cell is created through the two flip-flops 409 and 419 and inputted to the router 201 together with the data. Let's do it. Here, it is not absolute that the start cell to be input to the router 201 should be two clocks later than the internal start cell. Here, "two clocks" assumes that the start cell needs to be two clocks later than the internal start cell because the packet control assumes that the time required for the header conversion is two clocks. In fact, if the time taken to convert the header in the packet control unit is longer than 2 clocks, a delayed start cell must be created.

Here, the information simply combined with the data is input to the packet 404. In other words, this means that in the case of invalid data, the bottleneck information can be discarded with the invalid data. Accordingly, in the present invention, when invalid data is input to the capturing control unit, the bottleneck information bp_in is input to the bottleneck information monitoring unit 411 regardless of discarding the data. On the other hand, the information on monitoring the input bottle information is transmitted to the bottle information information generating unit 410, the bottle information information generating unit 410 generates an appropriate bottleneck information signal (bp signal) based on the input information, the read logic unit 405 Compares the bottleneck information (bo_out) to generate a bottleneck information pattern (bp pattern) to be input to the router 201. The generated bottleneck information pattern is ORed with the data in the logical summer 406 and inputted to the router 201.

For the purposes of the present disclosure, the bottleneck information (backpressure) transmitted from the router 201 to the switch 202 is referred to as first bottleneck information (back pressure out (RT-> switch, bp out)), and the switch 202 to the router 201 The transmitted bottleneck information is referred to as second bottleneck information (back pressure in (switch-> RT, bp_in)). As mentioned above, when the bottleneck information is not processed separately from the data, it is not possible to correctly control the state of each priority queue. Therefore, bottleneck information and data should be processed separately.

5 illustrates functional blocks for processing second bottleneck information bp_in according to an embodiment of the present invention. Referring to FIG. 5, first, the second bottleneck information input to the reading logic unit 501 of the capo is separated from the data and is input to the monitoring unit 506 irrespective of the data. Then, the pattern generation unit 507 included in the monitoring unit 506 makes the bottleneck information into a pattern again known by the router 201 and latches the latch through the latch 508 for a predetermined time. Thereafter, the latched bottleneck information pattern is output to the logical summer 504 in accordance with bp_start, and the logical summer 504 logically sums the bottleneck information pattern and the data and is transmitted to the router 201. In this case, bp_start uses a start cell indicating the time point at which data in the packet is read. Here, the serial bottleneck information checks the start patterns 1 and 2 because there is not enough register to latch all the bp patterns, and then the pattern is latched with 3-bit data as if it were a cue register. If the data is then ORed with the data transmitted to the router, it is converted to the serial by referring to the queue register and then ORed with the data.

6 illustrates a pattern generation process for the second bottleneck information. 6 illustrates a state transition of the monitoring unit of FIG. 5. Referring to FIG. 6, in step 611, it is checked whether a first start pattern has occurred. If the first star pattern occurs, the process proceeds to step 613. Otherwise, the process waits. In operation 613, it is checked whether a second start pattern occurs. If the second start pattern occurs, the process proceeds to step 615, otherwise, the process waits. When the generation of the first and second start patterns indicating the start of the bottleneck information pattern is checked, the bottleneck information pattern is latched through steps 615 to 621 and the start cell is checked in step 623. Here, if the start cell is input, the process proceeds to step 611; otherwise, the process waits.

FIG. 7 illustrates functional blocks for processing first bottleneck information bp_out according to an embodiment of the present invention. The first bottleneck information has already been mentioned but is a control signal in the direction of (RT-> Switch). Bp_out is not monitored as in the prior art, but as shown in FIG. 2, bp_out input to the switch is input to the capture controller again to determine whether to hold data to be input from the capture to the router. Here, the status of a specific queue of the router can be known through the bp_out signal. In general, the router has a queue for each priority, and data is managed for each queue. Therefore, the header conversion write logic unit 701 converts a specific header of the data to know the queue to which the data is to be input.In this case, the bp_out input to the capo control unit informs the status of each queue so that the data to be input must be held in the packet. You can decide whether or not to send it. At this time, the bp_out signal input to the pattern generator 707 is serially input, and the serial bp_out information is converted into a cue tap format, and the cue tap (destination cue information of the data to be input) of the data to be input from the comparator 708 is known. It is compared with the If the queue of data to be input is currently the bottleneck through bp_out, the data is held at the target during the next data entry time in the target. At this time, in order to compare bp_out with 3 bits input cue tap, serially input bp_out should be set in cue tap format. That is, it must be made in the form of 3-bit data. This operation is immediately performed by the pattern generator 707.

8 illustrates a pattern generation process for the first bottleneck information. Since the process of FIG. 8 is similar to the process of FIG. 6 described above, only differences will be described below. First, the status of each cue is input after successive inputs of patterns 1 and 2 indicating the start of the bp pattern. The status of each cue is checked and latched in each register, and then inputted from the switch. This is compared to the queue tab of the data. Each of these queue status latches is cleared after a start cell (soc) is input to indicate the start of the next data.

As described above, the present invention has an advantage of preventing the loss of the control signal by monitoring the control signals exchanged between the switch and the router when the switch and the router are remotely connected using a fifo in the asynchronous transmission mode system. .

Claims (6)

In the signaling processing device between the ATM switch and the router in the ATM system, Pappo that temporarily stores pure data, A header conversion unit for analyzing header information from the received data and transmitting the control signal to a control signal control unit, and storing pure data in the packet; The control signal controller which analyzes the control signal from the header converter and informs control information to a control signal generator; And a control signal generation unit for generating an enable signal for controlling a time point at which data is written to and read from the packet, and for generating an internal control signal with the control information from the control signal controller. The method of claim 1, And the control signal is a bottleneck. In the signaling processing device between the ATM switch and the router in the ATM system, The write logic unit analyzes the header information from the data received from the switch and transmits the bottleneck information to the bottleneck information monitoring unit, and writes pure data to the packet. The cover for temporarily storing the pure data; The bottleneck information monitoring unit converting the bottleneck information from the write logic unit into an internal signal form and latching the predetermined time period; A read logic section for reading the data stored in the packet by the internally made start cell, And a logical adder for logically combining the read data from the read logic unit and an internal signal corresponding to the bottleneck information and transmitting the logical signal to the router. In the signaling processing device between the ATM switch and the router in the ATM system, A write logic unit for analyzing the data header information received from the switch and recording the data header information, and transmitting the data header information to a comparator; The cover for temporarily storing the received data; A pattern generator for inputting bottleneck information indicating a state of each queue generated from the router and converting the information into an internal signal form; The header from the write logic unit is analyzed and the internal signal indicating the status of each queue from the pattern generator is compared. If it is determined that the destination queue of the data is the bottleneck, the data can be held in the packet. The comparator for generating a control signal, And the read logic section which reads the data recorded in the packet by the control signal from the comparator and delivers the data to the router. In the signaling processing method between the ATM switch and the router in the ATM system, Classifying bottleneck information and pure data by analyzing header information from data received from the switch; Storing the pure data in a packet; Converting the bottleneck information into an internal signal and latching the predetermined time; Reading the data stored in the packet by the internally created start cell, And logically combining the read data with an internal signal corresponding to the bottleneck information and transmitting the result to the router. In the signaling processing method between the ATM switch and the router in the ATM system, Analyzing and storing the data header information received from the switch in a packet; Converting the bottleneck information indicating the status of each queue from the router into an internal signal; Comparing destination cue information of the data obtained from the header analysis with the internal signal; If the destination queue of the data is determined to be a bottleneck by the comparison, holding the data in the packet for a predetermined time.