KR20010049071A - A duplex controlling apparatus between modules in a Asynchronous Transfer Mode switching system, and control method thereof - Google Patents

Abstract

PURPOSE: A dual control apparatus between modules in an ATM switch system and a control method of the same are provided to prevent a loss of a cell data during a dual switching operation by coinciding a timing of a cell data transferred to each cell transfer module even when an active state of a cell transfer module is switched. CONSTITUTION: A dual control apparatus between modules in an ATM switch system includes first and second cell transfer modules(30,31), a cell receiving module(32) and a switching detection unit(40). The first and second cell transfer modules(30,31) include an active signal generation logic unit(41) for generating an active signal which informs an active state, and a pre-state signal generation logic unit(42) for generating a pre-state signal which pre-informs a dual switching state. The cell receiving module(32) includes first and second input buffers(33,34), first and second FIFO(37,38), first and second output buffers(35,36) and a control logic unit(39). The first and second input buffers(33,34) transfer the cell data inputted from the first and second cell transfer modules(30,31) to the first and second FIFO(37,38) through the cell data transfer line.

Description

A duplex controlling apparatus between modules in a Asynchronous Transfer Mode switching system, and control method

The present invention relates to an apparatus for controlling redundancy between modules in an Asynchronous Transfer Mode switching system and a method of controlling the same. Particularly, in case of transferring cell data between modules to which redundancy is applied in an ATM switching system, the cell data when switching between modules is redundant. The present invention relates to an inter-module redundancy control apparatus and method for controlling the same in an ATM switching system that is suitable for a system requiring a high degree of reliability by preventing the loss.

Recently, with the development of the information industry, the development of communication network technology is accelerating to accommodate the needs of people who want to receive various high quality communication services, but the existing communication network technology is insufficient to satisfy such needs. In order to accommodate the various requirements of users, the development of broadband information communication based on ATM switching system is actively underway.

The ATM switching system divides user information into a certain packet size, adds destination information to the packet header portion, delivers the cell to a fixed size cell, and then returns the original information. To be sent in front of the user information so that the exchange system can easily recognize the user information. After recognizing user information, it is exchanged cell by cell and transmitted to the next destination.

In the ATM switching system, all user information is transmitted in a fixed size cell unit, and the cell exchange is performed by hardware, thereby providing various services from low speed to high speed. In addition, it can flexibly cope with new services and improve network efficiency.

As shown in FIG. 1, the general basic structure of the ATM switching system as described above includes an input module 10, an output module 13, a control unit 12, and a self-routing switch 11. It consists of.

The cell data output from the input module 10 is transferred to the magnetic path selection switch 11 under the control of the controller 12. The magnetic path selection switch 11 receiving the cell data selects one of the two input modules 10 and designates the output path of the cell data of the selected input module 10 to the next output module 13. To pass.

2 is a block diagram showing an intermodule redundancy control structure in a conventional ATM switching system. As shown in FIG. 2, the dual module redundancy control structure in the conventional ATM switching system includes a first cell transmission module 20 and a second cell transmission module 21 for transmitting cell data, and a cell for receiving cell data. It consists of a receiving module 22.

At the output terminal of the first cell transmission module 20 and the second cell transmission module 21, there are two strands of output transmission lines, one of which is a cell data transmission line that outputs cell data. The other is an active signal transmission line for outputting an act signal indicating the active state of the module. Then, the two cell transmission module monitors the state of each other and generates an active signal to the active signal generation logic unit (not shown), which is included according to the result. That is, when the first and second cell transmission modules 20 and 21 monitor the state of each other and any one of the first cell transmission module 20 and the second cell transmission module 21 is active, The active signal generation logic of the active cell transmission module generates an activation signal and inputs it to the buffer selection logic unit 25 of the cell receiving module 22, and does not generate an activation signal in the remaining cell transmission module that is not activated. . However, the cell data output from the first and second cell transmission modules 20 and 21, respectively, may be determined by the first and second buffers 23, 23 of the cell receiving module 22 regardless of whether the cell transmission module is active or not. Are respectively output to (24). The buffer selection logic unit 25 of the cell receiving module 22 receiving the activation signal connects the cell data of the first or second cell transmission module 20 or 21 that has transmitted the activation signal to the cell transmission module. The first or second buffers 23 and 24 of the cell receiving module 22 are selected and output to the next stage.

In other words, if an activation signal is generated in the active signal generation logic unit of the first cell transmission module 20, the activation signal generation logic unit does not generate the activation signal in the second cell transmission module 21 which is monitoring each other. . The buffer selection logic unit 25 of the cell receiving module 22 receives the activation signal of the first cell transmission module 20 through the activation signal transmission line. The buffer selection logic section 25 of the cell receiving module 22 selects the first buffer 23 connected to the first cell transmission module 20 to transfer the cell data to the next stage based on the input signal. Pass cell data to the next stage. At this time, the cell receiving module 22 also receives the cell data from the second cell transmission module 21, but the active signal of the second cell transmission module 21 is not input to the buffer selection logic section 25. The buffer selection logic unit 25 does not select the second buffer 24 that receives the cell data of the second cell transfer module 21, thereby transferring the cell data of the second cell transfer module 21 to the next stage. can not do.

If the activation signal of the second cell transmission module 21 is generated, the second buffer receiving the cell data of the second cell transmission module 21 from the buffer selection logic unit 25 of the cell receiving module 22 ( 24), the cell data of the second cell transmission module 21 is transferred to the next stage. At this time, since the activation signal of the first cell transmission module 20 is not input to the buffer selection logic unit 25, the first buffer 23 connected to the first cell transmission module 20 in the buffer selection logic unit 25. Do not select to not transmit the cell data of the first cell transmission module 20 to the next stage.

In the conventional module-to-module duplex control structure in the ATM switching system as described above, when the active state of the cell transfer module is transferred during cell data transfer, the first and second cell transfer modules 20 and 21 are transferred. Since the timing of the cell data applied to the cell receiving module 22 through the cell data transmission line is not correct and the order of the cell data is not completely matched, at least one of the cell data is broken at the moment of switching. This broken cell is discarded by an error checking unit (not shown) of the next stage, which causes a problem of cell loss in the ATM switching system.

Accordingly, the present invention has been made to solve such a problem, the object of the present invention is that even when the active state of the cell transmission module is switched to match the timing of the cell data transmitted from each cell transmission module at the instant of duplication transfer The present invention provides an apparatus for controlling redundancy between modules in an ATM switching system and a control method thereof to prevent loss of cell data.

1 is a block diagram illustrating a general structure of an ATM switching system.

Fig. 2 is a block diagram showing an intermodule redundancy control structure in a conventional ATM exchange.

3 is a block diagram illustrating an intermodule redundancy control structure in an ATM switching system according to the present invention.

4 is a flowchart illustrating a method for controlling switching between modules in an ATM switching system according to the present invention.

* Description of the symbols for the main parts of the drawings *

20, 30: first cell transmission module 21, 31: second cell transmission module

22, 32: cell receiving module 23: first buffer

24: second buffer 33: first input buffer

34: second input buffer 35: first output buffer

36: second output buffer 37: first FIFO

38: second FIFO 39: control logic unit

40: switching detection unit 41: active signal generating logic portion

42: pre-state signal generation logic section

In order to achieve the above object, the module-to-module redundancy control apparatus of the ATM switching system of the present invention generates an act signal and a prestate signal, and transmits first and second cell data. A cell transmission module; Receives the activation signal, the pre-state signal and the cell data from the first and second cell transmission module, selects and outputs cell data input from one of the first and second cell transmission modules, wherein the pre-state A cell receiving module for completely outputting one cell data being output when the signal is input and selecting and outputting cell data which does not output a pre-state signal of another cell transmission module; And a switching detector configured to detect a redundant switching state of the first and second cell transmission modules in advance and generate a pre-state signal in the cell transmission module to be ablated.

A method for controlling inter-module redundancy in an ATM switching system according to the present invention, the method comprising: detecting a redundancy transfer before a predetermined time while transferring cell data of a first cell transmission module to a next stage; Connecting a second cell transmission module to the next stage while continuing to transmit data of the first cell transmission module to the next stage when receiving a pre-state signal generated by the first cell transmission module; Terminating the transmission of one cell data to the next stage, cutting off the connection between the first cell transmission module and the next stage and transferring the data of the second cell transmission module to the next stage. Intermodule Redundancy Control Method in ATM Switching System.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating an intermodule redundancy control structure in an ATM switching system according to an embodiment of the present invention.

As shown in FIG. 3, an apparatus for controlling redundancy between modules in an ATM switching system according to the present invention includes first and second cell transmission modules 30 and 31, a cell receiving module 32, and a transfer detection unit. It is comprised with 40.

The first and second cell transmission modules 30 and 31 may include an active signal generation logic unit 41 for generating an active signal indicating an active state, and a pre-generation signal for generating a pre-state signal for informing of a redundancy transfer state. A state signal generation logic section (PSG) 42 is provided to output cell data to the cell receiving module 32.

The cell receiving module 32 includes first and second input buffers 33 and 34, first and second first-in first-out (FIFO) 37 and 38, and first and second input buffers. 2 output buffers 35 and 36 and a control logic section 39 are provided.

The first and second input buffers 33 and 34 receive cell data input from the first cell transmission module 30 and the second cell transmission module 31 through respective cell data transmission lines. To the FIFOs 37 and 38. The first and second FIFOs 37 and 38 temporarily store cell data applied from the first and second input buffers 33 and 34, respectively, and then store the first and second output buffers 35, respectively. The first and second output buffers 35 and 36 transmit the cell data output from the respective FIFOs 37 and 38 to the next stage. To provide. The control logic unit 39 receives a pre-state signal from the first and second cell transfer modules 30 and 31, and controls the cell data being output from the first and second input buffers 33 and 34. The first input buffer 33, the second input buffer 34, the first output buffer 35 and the first start buffer (SOC) signal, which is a signal indicating the start of every cell included, are identified , The second output buffer 36, the first FIFO 37, and the second FIFO 38 are controlled.

In addition, the transfer detection unit 40 may transmit the first and second cell transmission modules 30 and 31 according to a reset, a board dismount, a command, or a power detection state of the system before a predetermined time before the transfer occurs. Monitor the redundancy transfer status of When the redundant switching is detected before a predetermined time, the cell transmission module 30, 31 notifies the corresponding state to generate the pre-state signal in the pre-state signal generation logic unit 42 of the cell transfer module to be transferred, The cell receiving module 32 completely transmits one cell data being output to the next stage.

Among the two cell transmission modules 30 and 31, the pre-state signal generation logic unit 42 generates a pre-state signal, which is a preliminary signal, before redundancy switching in an operating module. This signal is generated a certain time, for example, several μ (10 ^-6 ) seconds before the actual redundancy switchover occurs. According to the hernia, command, or power detection state, the redundancy switching is detected in advance before a predetermined time, for example, several μs, and the cell transmission module 30 or 31 is notified of this state, so that the cell transfer module to be redundantly switched ( 30) and 31 generate a pre-state signal. The pre-state signal is input to the control logic unit 39 of the cell receiving module 32. When the pre-state signal generated by the first cell transmission module 30 is input, the control logic unit 39 receives the first output. The second output buffer 36 is operated in a state in which cell data is output to the next stage through the buffer 35, but in a state in which processing of one cell data is completed (processing of one cell is completed within 1 μsec.) ) The first output buffer 35 is stopped and the cell data of the second cell transfer module 31 is output to the next stage through the second output buffer 36. The above operation describes the operation state of the buffer according to the state of the pre-state signal.

That is, when the transfer detection unit 40 detects the redundant transfer of the cell transmission modules 30 and 31, the pre-state signal generation logic unit 42 of the cell transfer module to be transferred generates a pre-state signal, and transfers the transfer. One cell data applied from the cell transmission module to be output is completely output through the output buffer, and then the cell data of the other cell transmission module is output through the other output buffer.

On the other hand, when the control logic unit 39 grasps a start of cell (SOC) signal, which is a signal indicating the start of a cell, among the cell data signals of the first input buffer 33 and the second input buffer 34, At this time, the control logic unit 39 generates a FIFO recording signal (a first FIFO recording signal and a second FIFO recording signal) while counting one cell data to generate a byte corresponding to one cell data previously promised. The first and second FIFOs 37 and 38 are controlled such that the data of the first and second FIFOs 37 and 38 can be recorded. When a cell data is completely filled in the FIFOs 37 and 38, the control logic unit 39 generates a FIFO read signal (a first FIFO read signal and a second FIFO read signal) during one cell data cycle. The cell data of (38) is output. The first input buffer 33 and the second input buffer 34 are always open so that cell data from the first cell transmission module 30 is sent to the first FIFO 37 and from the second cell transmission module 31. Cell data provides a path that can be written to the second FIFO 38.

A method of switching between modules in an ATM switching system according to the present invention will be described with reference to the flowchart of FIG.

First, the two cell transmission modules 30 and 31 output cell data to the cell receiving module 32, respectively. The output cell data is transmitted to the input buffers 33 and 34 of the cell receiving module 32 connected to each of the cell transmitting modules 30 and 31 (step S1). When the cell data input to the input buffers 33 and 34 is output to the FIFOs 37 and 38, the control logic section 39 of the cell data output from the input buffers 33 and 34 is used. By detecting the cell start signal, the cell data output from the input buffers 33 and 34 are counted to determine one complete cell data. At this time, the control logic unit 39 generates a FIFO write signal to the FIFOs 37 and 38 while counting the cell data, and applies it to the FIFOs 37 and 38, and the FIFOs 37 and 38, respectively. When the FIFO recording signal is input to the FIFOs 37 and 38, the FIFOs 37 and 38 temporarily store the cell data applied from the input buffers 33 and 34 (step S2). When storing of the cell data in the FIFOs 37 and 38 ends, the control logic unit 39 generates a FIFO read signal to output the cell data of the FIFOs 37 and 38 to the output modules 35 and 36. (Step S3). The control logic unit 39 connects one of the first and second output buffers 35 and 36 to the next stage to output cell data. The output buffers 35 and 36 are control logics. Under the control of the unit 39, the cell data of the FIFOs 37 and 38 is output to the next stage.

However, while the cell data stored in the FIFOs 37 and 38 are outputted through the output buffers 35 and 36, the cell transfer module 30, (based on the system monitoring information) by the transfer detection unit 40 (( 31, if the redundancy transfer for one of the cells is detected in advance (step S4), the corresponding state is notified to the cell transfer modules 30 and 31, and the pre-state of the cell transfer modules 30 and 31 is detected. The signal generating logic section 42 generates a pre-state signal and transmits it to the control logic section 39 (step S5). At this time, when the pre-state signal is input, the control logic unit 39 continuously outputs the cell data stored in the FIFOs 37 and 38 through the output buffers 35 and 36 (step S6). The other output buffer which does not output cell data among the output buffers 35 and 36 is operated, and is connected to the next stage (step S8). If one cell data being output is completely transferred to the next stage, the output buffer is cut off (step S9). However, if the redundant switching is not detected in advance by the switching detection unit 40, and thus the pre-state signal is not input, the cell data is continuously output through the operating output buffer (step S7).

For example, cell data input from the first and second cell transmission modules 30 and 31 are temporarily stored in each of the FIFOs 37 and 38 via respective cell data paths, and the first When the transfer of the first cell transfer module 30 is detected by the transfer detection unit 40 before a predetermined time while outputting the cell data of the cell transfer module 30 to the next stage through the first output buffer 35. The prestate signal generation logic unit of the first cell transmission module 30 generates a prestate signal and transmits the prestate signal to the control logic unit 39 of the cell receiving module 32. At this time, the control logic unit 39 operates the first output buffer 35 until one cell data of the first cell transfer module 30 being output through the first output buffer 35 is completely transmitted to the next stage. The second output buffer 36 is operated, and when one cell data of the first cell transfer module 30 is outputted, the first output buffer 35 is stopped.

Accordingly, as described above, even if one of the two cell transmission modules is redundantly switched, the cell receiving module receiving the pre-state signal completes transmission of one cell data being output through the transmission path of the cell transmission module to be switched to the next stage. .

As described above, the present invention prevents cell loss that occurs during redundancy switching in an ATM switching system, thereby improving system reliability and eliminating the need for retransmission of lost cells or packets, thereby improving system performance. .

Claims (7)

In the ATM exchange system, First and second cell transmission modules for generating an activation signal and a pre-state signal and transmitting cell data; Receives the activation signal, the pre-state signal and the cell data from the first and second cell transmission module, selects and outputs cell data input from one of the first and second cell transmission modules, wherein the pre-state A cell receiving module for completely outputting one cell data being output upon inputting a signal and then selecting and outputting cell data which does not output a pre-state signal of another cell transmission module; And Inter-module duplication in an ATM switching system, characterized in that it comprises a switch-over detection unit for detecting in advance the redundancy switching state of the first and second cell transmission module to generate a pre-state signal in the cell transfer module to be ablated. Control unit. 2. The cell transmission module of claim 1, wherein the cell transmission module further comprises a pre-state signal generation logic unit for generating a pre-state signal so that the cell reception module completely outputs cell data when duplex switching. Intermodule redundancy control system in the system. The method of claim 1, wherein the cell receiving module, First and second input buffers for transmitting cell data received from the cell transmission module; First and second FIFOs for temporarily storing cell data output from the first and second input buffers; First and second output buffers for outputting cell data received from the first and second FIFOs; The first and second input buffers, the first and second output buffers, and the first and second input buffers by receiving the pre-state signal and identifying a cell start signal of cell data output from the first and second input buffers. 2. The module-to-module redundancy control device of the ATM switching system comprising a control logic unit for controlling the operation of the two FIFO. The cell of claim 1, wherein the control logic unit completely outputs the cell data being output from the cell transmission module to which the redundancy switching is to be generated among the first and second cell transmission modules when the pre-state signal is input, and the cell is not switched. And controlling the first and second output buffers to output cell data of a transmission module. The method of claim 1, wherein the switching detector detects a redundant switching of the first and second cell transmission modules before a predetermined time according to a reset, hernia, command, or power detection state of the system. Dual module redundancy control device in ATM switching system. The method of claim 1, wherein the control logic unit, when outputting the cell data from each input buffer, the cell start signal of the cell data is counted by counting the cell data, the counted cell data is the first and second FIFO A FIFO write signal is generated to be temporarily stored in the FIFO, and when cell data is output from the first and second FIFOs, a FIFO read signal is generated to output cell data of the first and second FIFOs. Dual module redundancy control device in TEM exchange system. In the module-to-module redundancy control method in the ATM exchange system, Detecting a redundancy transfer before a predetermined time while transferring cell data of the first cell transmission module to a next stage; Connecting a second cell transmission module to the next stage while continuing to transmit data of the first cell transmission module to the next stage when receiving a pre-state signal generated by the first cell transmission module; Terminating the transmission of one cell data to the next stage, cutting off the connection between the first cell transmission module and the next stage and transferring the data of the second cell transmission module to the next stage. A method of dual module redundancy control in ATM switching system.