KR100250485B1 - High speed packet switching device of frames between nodes - Google Patents

Abstract

PURPOSE: A high speed packet switch device of a frame between nodes is provided to minimize a transmission delay, and to increase a data transmission rate by performing a non-blocking high speed packet switching between nodes. CONSTITUTION: A non-blocking high speed packet switch(200) performs a path control of frame data inputted through a signal line, and includes two stages in order to perform a path control of an input frame data of a switch module. The non-blocking high speed packet switch(200) is connected to each other with an omega networking way through a signal line of the inside of a module between stages. For this reason, the non-blocking high speed packet switch(200) controls the path control of the frame data by using all output signal lines though a frame is inputted through any input signal line of the first stage.

Description

High speed packet switch device of inter-node frame

The present invention relates to a high speed packet switch apparatus of an inter-node frame, and more particularly to a non-blocking high speed packet switch apparatus capable of exchanging packet frames having a variable length.

Accordingly, the present invention enables the non-blocking fast packet switching between nodes in a single chip to perform high level data link control (HDLC) frames, thereby providing a frame path between nodes. It is an object of the present invention to provide a high speed packet switch apparatus of an inter-node frame that minimizes transmission delay due to switching and improves data transmission rate.

According to the present invention for achieving the above object, a plurality of non-blocking high speed packets are formed in two stages to perform path control on frame data input through a signal line and control a path on input frame data of a switch module. A plurality of module matching devices involved in the switch, the U-link cable signal matching with the outside, the fault detection function for the input signal for fault tolerance, and connected to the plurality of non-blocking fast packet switches; And a path control manager and a maintenance manager connected to the module matching device.

1 is a high-speed packet switch device block diagram of an inter-node frame according to the present invention.

2 is a non-blocking fast packet switch block diagram in accordance with the present invention.

3 is a block diagram of feedback control of a buffer controller, frame buffer and buffer switch of a non-blocking fast packet switch in accordance with the present invention;

<Description of the symbols for the main parts of the drawings>

201: delay 202: address reconfigurer

203: path control manager 100: module matching device

200: non-blocking high speed packet switch

205: buffer controller 206: frame buffer

207: buffer switch

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an inter-node frame switch device according to the present invention. The module matching device 100 is a block for U-link cable signal matching with the outside of the non-blocking fast packet switch device 200 module. It supports standard methods and has fault detection for input signals for fault tolerance.

The non-blocking fast packet switch 200 is a main functional block of the present invention, which performs path control on frame data input through a signal line, and is configured in two stages to enable path control on input frame data of a switch module. do. The non-blocking high speed packet switch 200 between the stages is connected to each other by an omega network using a signal line inside the module, so that all output signal lines of the second stage may be inputted to any input signal line of the first stage. Path can be controlled. In the path control process, the high speed packet switch device of the first stage performs path control on half of an address area of a frame that determines the high speed packet switch device group of the second stage, and the high speed packet switch device of the second stage includes a terminal device outside the module. Alternatively, the path control for each bit may be performed to identify bridge nodes of other networks. The path control function uses address bit-specific path control attribute information input from the path control manager 300 through the signal line when necessary during the start-up or operation of the network system, and the information is used by an external network operator or network through the signal line. It is provided in communication with the maintenance processor.

The maintenance manager device 300 collects failure information in the non-blocking fast packet switch 200 module through a signal line, performs a self-test on a failed frame path if necessary, and checks the corresponding path when the failure is confirmed. Perform overall maintenance functions such as isolation. In addition, control signals are frequently exchanged with network operators through signal lines.

2 is a block diagram of a non-blocking fast packet switch according to the present invention, and is composed of seven types of functional blocks. One high speed packet switch device accommodates up to four node blocks that can be configured as a single chip. The input frame data is delayed and transmitted to the three-phase output controller by the time required to reconstruct the destination address of the frame and perform the path control in the delay unit 201. For the destination address of the frame input from the delayer 201, the address reconstructor 202 checks whether the '0' bit forcedly inserted during communication by the HDLC communication method among the 28 bits of the destination address, and if the corresponding bit exists, By removing up to four forced insertion '0' bits that can be inserted in the address 3 bytes, a pure destination address of 3 bytes is constructed and transmitted to the path controller 204.

The path controller 204 receives various path information related to path control of the corresponding node input from the path control manager 203 external to the switch device, and determines the path opening and closing of the currently input frame, and determines the address of the frame for each input port. It transmits the result of opening / closing the path of the frame input through the signal line to the three-phase output controller through the individual signal line.

The buffer controller 205 is a functional block for switching the frame path so that the frames output from the three-phase output controller are uniformly stored in the various buffers in the frame buffer 206. In this functional block, the corresponding frames are distributed in a multi-round robin manner to handle distributed input frame traffic for each of four frame buffers located in the next stage.

The frame buffer 206 is an output buffer and is composed of a FIFO that facilitates hardware signal control and variable length packet processing. In this HPS high-speed switch, ASIC can be implemented by setting the size of 8 (width) x 512 (depth) as the maximum size of the unit FIFO. It also has a structure that guarantees clock independence for each output port. The round lobby buffer switch 207 is a block that arbitrates packet data bytes from several frame buffers 206 directed to the same output port and outputs them in a predetermined order, and transmits them from each frame buffer 206 in a round robin manner. It is a block in charge of the function of managing the output service of the received frames to transmit the stored frames to the output.

3 is a block diagram of a feedback control connection of a buffer controller, a frame buffer, and a buffer switch of a non-blocking fast packet switch according to the present invention, in which the buffer controller 301 displays the state of each frame buffer 302 in the buffer switch 303. While detecting the state of the current frame buffer 302 through a signal of, when an input frame is received, an empty frame buffer 302 is allocated. The SELOUT1 [8: 0] through SELOUT4 [8: 0] signals indicate the state of the input data and the frame buffer, and are then fed back to the buffer controller with the SELIN1 [8: 0] through SELIN4 [8: 0] signals. The buffer switch 303 checks whether the state of each frame buffer is Idle, Write, Standby, Read, and outputs the standby state in a round robin manner.

In detail, first, the state of each frame buffer is initially in an idle state, and when an input frame is input from the buffer controller 301, the state of the corresponding frame buffer 302 of the input line is checked. If the frame buffer 302 is in an idle state, the buffer controller 301 stores the input frame data in the frame buffer 302. The frame buffer 302 is in write mode at this time, and informs the buffer switch 303 that it is in write mode. The buffer switch 303 returns the state of each frame buffer 302 to the buffer controller through the signals SELOUT1 [8: 0] to SELOUT4 [8: 0]. In this case, when another input frame enters the buffer controller 301, the buffer controller 301 knows the state of the frame buffer 302, and thus selects the frame buffer 302 which is in an idle state by a certain law. . On the other hand, when the input frame is input, the frame buffer 302 sets its state to the standby mode, informs the buffer switch that the standby mode is in the standby mode, and until the buffer switch reads. Wait in Standby mode. The buffer switch 303 periodically monitors the state of each frame buffer 302 and outputs frame data in a round robin manner when the frame buffer is in a standby state. At this time, the buffer switch 303 reads the frame data by giving the signals of the RD-REQ1 to the frame buffer 302, and after reading the stored frame data, the frame buffer returns its state to the idle state again. Set it.

As described above, the present invention enables a frame transmission bus that requires real-time processing by switching a high-speed packet frame of a switch type, and accommodates an existing high-level data transmission control (HIPC) frame type because switching of a variable length packet frame is possible. It can be applied to the communication device to improve the economics, and there is a data converter at each input / output terminal of the high speed packet switch, so that it can be applied to various communication networks by accommodating various input / output signal line widths regardless of the internal structure of the switch. The non-blocking high speed packet switch of the present invention is also a high speed packet switch having a performance of about 1.26 Gbps.

Claims (3)

A plurality of non-blocking fast packet switches configured to perform path control on the frame data input through the signal line and to control the path to the input frame data of the switch module in two stages; A plurality of module matching devices involved in external U-link cable signal matching, having a fault detection function for an input signal for fault tolerance, and connected to the plurality of non-blocking fast packet switches; A path control manager connected to the plurality of non-blocking high speed packet switches and outputting path control attribute information for each bit provided in communication with an external network operator and a network maintenance processor; It is connected to the plurality of non-blocking fast packet switches and collects fault information in the non-blocking fast packet switch module, performs a self-test on a failed frame path if necessary, and isolates the corresponding path when the fault is confirmed. High speed packet switch device of the inter-frame frame, characterized in that comprises a maintenance manager for performing the overall maintenance function. The method of claim 1, And a plurality of non-blocking high speed packet switches formed in the two stages, wherein each stage is interconnected by an omega network using a signal line inside the module. The method of claim 1, The non-blocking fast packet switch comprises a plurality of delays for delaying input frame data; A plurality of address reconstructers constituting a pure destination address among the destination addresses of the frames inputted from the plurality of delayers; Determining path opening and closing of the input frame by receiving path control related attribute information of the corresponding node inputted from the path control manager outside the switch device, and opening or closing the path of the frame input through the address signal line of the frame for each input port. With a plurality of path controllers to determine the, A plurality of three-phase output controllers for receiving signals output from the plurality of address reconstructors and the plurality of path controllers; A plurality of buffer controllers for distributing the frames in a multi-rounding manner to process distributed frame signals output from the plurality of three-phase output controllers; An output buffer for controlling signals input from the plurality of buffer controllers, the plurality of frame buffers configured in a first-in, first-out manner to facilitate variable-length packet processing, and having a structure which ensures clock independence for each output port; And a buffer switch configured to control and output an output service of the frames transmitted from the plurality of frame buffers, and to output the stored frames.

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