KR20020013123A - Fuse box and method for forming the same - Google Patents

Abstract

PURPOSE: A fuse box is provided to easily guarantee thickness uniformity of an interlayer dielectric remaining in a fuse open region, by forming a gate electrode in a portion except the fuse open region so that a polycrystalline silicon layer which is in contact with the gate electrode and is formed in the fuse open region functions as a fuse. CONSTITUTION: The fuse open region(42) which is a fuse cut portion is defined in a substrate(31). A plurality of gate electrodes(32) are formed in the substrate at both sides of the fuse open region. The first interlayer dielectric(33) includes the first contact hole formed on the gate electrode in a portion adjacent to both sides of the fuse open region. The first conductive guard ring(34) prevents penetration of moisture, formed in the first contact hole. A fuse layer is formed on the first interlayer dielectric in a portion adjacent to the fuse open region, electrically connected to the gate electrode through the first guard ring. The first metal layer(37) is formed on the second interlayer dielectric(36) in a portion adjacent to the fuse open region. The third interlayer dielectric(38) including the second contact hole formed on the first metal layer in a portion adjacent to both sides of the fuse open region, is formed on the first metal layer. The second conductive guard ring(39) prevent penetration of moisture, formed in the second contact hole. The second metal layer(40) and a passivation layer(41) are sequentially stacked on the third interlayer dielectric.

Description

Fuse box and method for forming the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a fuse box, and more particularly, a fuse box in which a polycrystalline silicon layer contacted to a gate electrode and formed in a fuse open region serves as a fuse to improve device integration, reliability, and yield. And a method for forming the same.

As semiconductor devices are becoming highly integrated due to the development of general pattern forming technology, in the case of DRAM (Dynamic Random Access Memory (DRAM)) devices, the memory capacity is increased by four times, and the size of the chip is also approximately doubled. Is increased.

Therefore, since the rate of partial defects increases, the yield of a complete chip having no defects in the manufactured chip is reduced, resulting in a decrease in productivity. Thus, an extra memory cell is formed in the chip to replace the defective cell during the manufacturing process. In order to increase the yield of the chip.

After the semiconductor device is completed, the fuse box is opened to repair the circuit in which the defect is generated, and then the corresponding fuse is cut by using a laser.

In such a situation, the repair method using the laser fuse blowing method has an etching problem in that the oxide film is removed from the fuse box to control the oxide film thickness to the extent that the laser penetrates and blows the fuse. In addition, the remaining oxide thickness change during the oxide etching process for opening the fuse box due to the oxide thickness change before opening the fuse box, which is inevitable for each wafer, causes deterioration in fuse blowing during repair.

In the conventional fuse box, as illustrated in FIG. 1, a fuse formed through a gate insulating layer on a semiconductor substrate 11 having a fuse open region 23 defined therein and a semiconductor substrate 11 including the fuse open region 23. A plurality of gate electrodes 12 having a role, a first interlayer insulating layer 13 formed on the semiconductor substrate 11 including the gate electrodes 12, and a first interlayer insulating layer other than the fuse open region 23. 13, a second polycrystalline silicon layer 14, a first insulating layer 15, a first metal layer 16, and a guard ring 20 formed on the first metal layer 16. The second interlayer insulating film 17 and the second metal layer 21 and the passivation layer 22 are sequentially formed on the second interlayer insulating film 17.

However, in the conventional fuse box and its formation method, since the gate etching formed in the fuse open region acts as a fuse, the repair etching amount is increased due to a high structure such as a capacitor formed in the cell region. Since the uniformity of the thickness is difficult to secure and the fuse is not blown, the FTA becomes worse, resulting in deterioration of device integration, reliability, and yield.

The present invention has been made in order to solve the above problems, and a gate electrode is formed in a portion other than the fuse open region, and the polycrystalline silicon layer formed on the fuse open region by contacting the gate electrode serves as a fuse, thus remaining in the fuse region. It is an object of the present invention to provide a fuse box and a method of forming the fuse box for securing the thickness uniformity of the interlayer insulating film.

1 is a structural cross-sectional view showing a conventional fuse box

2 is a structural cross-sectional view showing a fuse box according to an embodiment of the present invention.

3A to 3C are cross-sectional views illustrating a method of forming a fuse box according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

31 semiconductor substrate 32 gate electrode

33: first interlayer insulating film 34: first guard ring

35: third polycrystalline silicon layer 36: second interlayer insulating film

37: first metal layer 38: third interlayer insulating film

39: second guard ring 40: second metal layer

41: passivation layer 42: fuse open area

The fuse box of the present invention includes a substrate in which a fuse open region, which is a fuse cutting region, is defined, a plurality of gate electrodes formed on substrates on both sides of the fuse open region, and formed on a front surface and on the gate electrodes on both sides of the fuse open region. A first interlayer insulating film including a first contact hole formed in the first contact hole, a conductive first guard ring formed in the first contact hole to prevent external moisture from penetrating, and a first interlayer insulating film on a portion adjacent to the fuse open region A fuse layer electrically connected to the gate electrode through the first guard ring, a second interlayer insulating layer formed on a front surface, a first metal layer formed on a second interlayer insulating layer adjacent to the fuse open region, A third interlayer section formed on the first metal layer and including a second contact hole formed on a first metal layer adjacent to both sides of the fuse open region; And a second metal layer and a passivation layer, which are formed in the second contact hole and are electrically stacked on the third interlayer insulating layer, and the second guard ring is formed in the second contact hole to prevent external moisture penetration. do.

In addition, the method of forming a fuse box according to the present invention may include providing a substrate in which a fuse open region, which is a fuse cutting region, is defined, forming a plurality of gate electrodes on a substrate on both sides of the fuse open region, and opening the fuse on a front surface thereof. Forming a first interlayer insulating film including a first contact hole formed on a gate electrode at adjacent portions of the region, forming a first conductive layer in the first contact hole, and forming a first conductive layer in the first contact hole, Forming a fuse layer electrically connected to the gate electrode through the first conductive layer on the first interlayer insulating film, sequentially forming a second interlayer insulating film, a first metal layer, and a third interlayer insulating film on a front surface thereof; Selectively etching a third interlayer insulating layer to form a second contact hole on a first metal layer adjacent to both sides of the fuse open region; Forming a second conductive layer in a second contact hole, forming a second metal layer and a passivation layer on the front surface, and etching a passivation layer, a second metal layer, a third interlayer insulating film, and a first metal layer in the fuse open region. Characterized in that comprises a.

A preferred embodiment of a fuse box and a method of forming the same according to the present invention as described above will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a fuse box according to an exemplary embodiment of the present invention, and FIGS. 3A to 3C are cross-sectional views illustrating a method of forming a fuse box according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the fuse box according to the embodiment of the present invention has a semiconductor substrate 31 having a fuse open region 42 defined as a fuse cutting region, and a semiconductor substrate 31 other than the fuse open region 42. A plurality of gate electrodes 32 formed on the semiconductor substrate 31 including the gate electrodes 32 and the gate electrodes 32 formed through the gate insulating layer, and adjacent to both sides of the fuse open region 42. Is formed on the first interlayer insulating film 33 having the first guard ring 34 for preventing external moisture infiltration, and on the fuse open region 42 and the first interlayer insulating film 33 at the portions adjacent to both sides thereof. A first interlayer insulating layer 33 including a third polycrystalline silicon layer 35 and a third polycrystalline silicon layer 35 electrically connected to each other through the gate electrode 32 and the first guard ring 34 to serve as a fuse. The second interlayer insulating film 36 formed on the The first metal layer 37 is formed on the second interlayer insulating layer 36 adjacent to the open region 42 and the second guard ring 39 is formed on the first metal layer 37 to prevent external moisture penetration. A second metal layer 40 and a passivation layer 41 are formed by being sequentially stacked on the third interlayer insulating film 38 and the third interlayer insulating film 38.

In the method of forming a fuse box according to an exemplary embodiment of the present invention, as shown in FIG. 3A, a semiconductor substrate 31 having a fuse open region defined as a fuse cutting portion is provided.

A plurality of gate electrodes 32 are formed on the semiconductor substrate 31 other than the fuse open region through the gate insulating layer.

Here, the gate electrode 32 is formed of a first polycrystalline silicon layer.

Subsequently, a first interlayer insulating layer 33 and a first photoresist layer R1 are sequentially formed on the semiconductor substrate 31 including the plurality of gate electrodes 32, and then the first photoresist layer R1 is fused. After selectively exposing and developing the first contact hole formed in the gate electrode 32 adjacent to both sides of the open area to be removed only, the selectively exposed and developed first photoresist R1 is masked. The first interlayer insulating layer 33 is selectively etched to form a first contact hole.

As shown in FIG. 3B, after the first photoresist layer R1 is removed, a second polycrystalline silicon layer is formed on the entire surface and etched back to fill the first contact hole so that the first guard ring 34 is formed. Form.

The third polycrystalline silicon layer 35 electrically connected to the gate electrode 32 through the first contact hole serves as a fuse on the first interlayer insulating layer 33 including the first guard ring 34. To form.

After the second photosensitive film R2 is coated on the third polycrystalline silicon layer 35, the second photosensitive film R2 is selectively exposed and developed to remain only in the fuse open region and adjacent portions on both sides thereof. The third polycrystalline silicon layer 35 is selectively etched using the selectively exposed and developed second photosensitive film R2 as a mask.

As shown in FIG. 3C, after the second photosensitive film R2 is removed, the second interlayer insulating film 36 and the first metal layer 37 are formed on the first interlayer insulating film 33 including the third polycrystalline silicon layer 35. ), A third interlayer insulating film 38 and a third photosensitive film are formed.

Here, the first and third interlayer insulating films 33 and 38 may be made of BPSG, Phospho Silicate Glass (PSG), HD Density Plasma (HDP) -oxide film, and UES. It is formed of one of Undoped Silicate Glass (USG).

And selectively exposing and developing the third photoresist film so as to be removed only at a portion where a second contact hole in a portion adjacent to the fuse open region is to be formed, and then using the selectively exposed and developed third photoresist film as a mask. After the interlayer insulating layer 38 is selectively etched to form a second contact hole, the third photoresist layer is removed.

Next, a fourth polycrystalline silicon layer is formed on the entire surface and etched back to fill the second contact hole to form a second guard ring 39.

After the second metal layer 40, the passivation layer 41, and the fourth photoresist film are sequentially formed on the third interlayer insulating film 38 including the second guard ring 39, the fourth photoresist film is fused. After selectively exposing and developing to remove only the region where the open region is to be formed, the passivation layer 41, the second metal layer 40, and the third interlayer insulating film 38 using the selectively exposed and developed fourth photoresist film as a mask. ) Is selectively etched to form the fuse open region 42, and then the fourth photoresist layer is removed.

The passivation layer 41 is formed of one of an HDP-oxide film, a Plasma Enhanced (PE) -nitride film, and a PE-oxide film having excellent etching resistance to wet etching.

The fuse box and the method of forming the same according to the present invention form a gate electrode at a portion other than the fuse open region, and the polycrystalline silicon layer formed on the fuse open region by contacting the gate electrode serves as a fuse, thereby reducing the amount of repair etching. Therefore, it is easy to secure the uniformity of the thickness of the interlayer insulating film remaining in the fuse open area, and thus prevents the defect of the fuse blowing, so that the FTA is good, thereby improving the integration, reliability, and yield of the device.

Claims (2)

A substrate having a fuse open region defined as a fuse cutting region; A plurality of gate electrodes formed on substrates on both sides of the fuse open region; A first interlayer insulating layer formed on a front surface and including a first contact hole formed on a gate electrode of adjacent portions of both sides of the fuse open region; A conductive first guard ring formed in the first contact hole to prevent external moisture from penetrating: A fuse layer formed on the first interlayer insulating layer in the fuse open region and adjacent portions thereof, the fuse layer being electrically connected to a gate electrode through the first guard ring; A second interlayer insulating film formed on the entire surface; A first metal layer formed on a second interlayer insulating film in a portion adjacent to the fuse open region; A third interlayer insulating layer formed on the first metal layer and including a second contact hole formed on a first metal layer adjacent to both sides of the fuse open region; A conductive second guard ring formed in the second contact hole to prevent external moisture from penetrating: And a second metal layer and a passivation layer, which are sequentially stacked on the third interlayer insulating film. Providing a substrate in which a fuse open region, which is a fuse cutting region, is defined; Forming a plurality of gate electrodes on a substrate on both sides of the fuse open region; Forming a first interlayer insulating layer including a first contact hole formed on a gate electrode of a region adjacent to both sides of the fuse open region on a front surface thereof; Forming a first conductive layer in the first contact hole; Forming a fuse layer electrically connected to a gate electrode through the first conductive layer on the first interlayer insulating layer in the fuse open region and an adjacent portion thereof; Sequentially forming a second interlayer insulating film, a first metal layer, and a third interlayer insulating film on the entire surface; Selectively etching the third interlayer insulating layer to form a second contact hole on a first metal layer adjacent to both sides of the fuse open region; Forming a second conductive layer in the second contact hole; Forming a passivation layer and a second metal layer on the front surface; And etching the passivation layer, the second metal layer, the third interlayer insulating layer, and the first metal layer of the fuse open region.