KR20020012863A - Method for manufacturing a contact hole suppressing an overetch of silicon substrate - Google Patents

Method for manufacturing a contact hole suppressing an overetch of silicon substrate Download PDF

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KR20020012863A
KR20020012863A KR1020000046096A KR20000046096A KR20020012863A KR 20020012863 A KR20020012863 A KR 20020012863A KR 1020000046096 A KR1020000046096 A KR 1020000046096A KR 20000046096 A KR20000046096 A KR 20000046096A KR 20020012863 A KR20020012863 A KR 20020012863A
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layer
film
etching
silicon
silicon substrate
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김재우
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윤종용
삼성전자 주식회사
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • H01L21/31138Etching organic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31144Etching the insulating layers by chemical or physical means using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/42Stripping or agents therefor
    • G03F7/427Stripping or agents therefor using plasma means only

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Abstract

PURPOSE: A method for forming a contact hole wherein an over-etch of a silicon substrate is controlled, is provided to increase a carbon component or reduce a fluorine component, by forming a SiN layer or SiON layer on a SiO2 layer formed on the substrate. CONSTITUTION: The silicon substrate(40) is prepared. A pad layer, a silicon oxide layer(44) and an etch selectivity buffer layer are sequentially formed on the silicon substrate. The silicon oxide layer and the etch selectivity buffer layer are patterned by using a photoresist mask. An ashing process is performed in an oxygen atmosphere regarding the structure in which patterned etch selectivity buffer layer and the patterned silicon oxide layer are formed, so that polymer and the photoresist pattern formed on the pad layer are eliminated. The pad layer is plasma-etched by using etch gas including a carbon component and a fluorine component to form a contact hole exposing the silicon substrate.

Description

실리콘 기판의 과도 식각이 억제된 콘택홀을 형성하는 방법{Method for manufacturing a contact hole suppressing an overetch of silicon substrate}Method for manufacturing a contact hole suppressing an overetch of silicon substrate}

본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 특히 실리콘 성분에 대해 높은 선택비를 가지되 실리콘 기판의 과도 식각을 억제할 수 있는 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole having a high selectivity with respect to a silicon component and suppressing excessive etching of a silicon substrate.

반도체 소자의 집적 초기 단계에는 등방성 식각인 습식 식각을 사용하였으나, 등방성 식각에 의한 언더컷의 문제가 반도체 소자가 고집적화됨에 따라 패턴을 충실하게 전사하지 못함에 따라, 습식 식각은 건식 식각법으로 대체되고 있다. 건식 식각은 이방성 식각으로 패턴 전사 충실도가 높고 습식 식각에 비해 독성이 있는 용액을 상당히 적게 사용하므로 취급이 용이한 이점이 있다.In the initial stage of integration of semiconductor devices, wet etching, which is isotropic etching, was used, but wet etching has been replaced by dry etching as the problem of undercut due to isotropic etching cannot be faithfully transferred to the pattern as semiconductor devices become highly integrated. . Dry etching has an advantage in that it is easy to handle because of anisotropic etching, which has high pattern transfer fidelity and considerably less toxic solutions than wet etching.

이러한 건식 식각은 글로우 방전 스퍼터링과 같은 물리적 작용에 기반을 둔 것, 플라즈마 에칭과 같은 화학적 작용에 기반을 둔 것 및 반응성 이온 빔 식각 및 반응성 이온 식각과 같은 물리적 작용과 화학적 작용의 결합에 기반을 둔 것이 있다.Such dry etching is based on physical action such as glow discharge sputtering, chemical action such as plasma etching, and combination of physical and chemical action such as reactive ion beam etching and reactive ion etching. There is.

플라즈마 에칭에 의한 패턴 형성은 대략 6단계를 거치는데, 첫째 플라즈마 상태에서 반응 종(reactive species)이 생성되고, 둘째 반응 종이 식각될 물질의 표면으로 확산하고, 셋째 반응 종이 식각될 물질 표면에서 흡수되고, 넷째 화학 반응이 일어나 휘발성 부산물이 생성되고, 다섯째 부산물이 표면으로부터 방출되고 여섯째 방출된 종이 가스 속으로 확산된다.Pattern formation by plasma etching takes about six steps: first reactive species are produced in the plasma state, second reactive species diffuse to the surface of the material to be etched, and third reactive species are absorbed at the surface of the material to be etched. In the fourth chemical reaction, volatile by-products are produced, the fifth by-product is released from the surface and diffuses into the sixth released paper gas.

실리콘 및 실리콘산화물을 플라즈마 에칭을 이용할 경우에는 통상 식각 가스로 불소 성분이 함유된 CF4, SF6, NF3을 사용하고 있으며, 부산물로 휘발성인 SiF4가 생성된다.In the case of plasma etching of silicon and silicon oxide, CF 4 , SF 6 , and NF 3 containing fluorine components are generally used as etching gases, and volatile SiF 4 is generated as a by-product.

실리콘 기판 및 실리콘 산화막의 플라즈마 에칭 과정을 도 1a 내지 도 1c를 참조하여 설명한다.The plasma etching process of the silicon substrate and the silicon oxide film will be described with reference to FIGS. 1A to 1C.

도 1a에서, 실리콘 기판(10) 상에 패드막인 실리콘질화막(SiN) 또는 실리콘산화질화막(SiON)(12)과 층간 절연막인 실리콘산화막(SiO2)이 순차적으로 형성되어 있다. 다음, SiO2막 상부에 탄소와 산소 및 수소 화합물인 소정의 포토레지스트 패턴(16)이 형성되어 있다. 포토레지스트 패턴(16)을 마스크로 이용하고 CF4가스를 사용하여 층간 절연막인 SiO2를 플라즈마 식각하여 실리콘산화막 패턴(14)과개구부(20)를 형성한다.In FIG. 1A, a silicon nitride film (SiN) or a silicon oxynitride film (SiON) 12 as a pad film and a silicon oxide film (SiO 2 ) as an interlayer insulating film are sequentially formed on the silicon substrate 10. Next, a predetermined photoresist pattern 16 of carbon, oxygen, and hydrogen compounds is formed on the SiO 2 film. The silicon oxide film pattern 14 and the opening 20 are formed by plasma etching the interlayer insulating film SiO 2 using the photoresist pattern 16 as a mask and using CF 4 gas.

식각 메커니즘을 살펴보면, CF4의 일부가 분해되어 CF3 *와 불소 원자가 생성된다. 불소 원자는 SiO2의 실리콘 성분과 반응하여 휘발성인 SiF4를 생성한다. 한편, CF3은 산소와 반응하여 COF2와 불소 원자를 생성하며, COF2는 다시 산소와 반응하여 CO를 생성하고 불소 원자를 생성한다. 즉, 불소 원자의 수는 증가하게 되므로, 실리콘 산화막의 식각은 계속 진행되면서휘발성인 SiF4와 CO 및 CO2가 생성된다. 그런데, 패드막으로 SiN을 사용하는 경우에, 패드막(12)의 표면에는 C-N계 화합물 및 Si-C계 화합물로 이루어진 폴리머(18)이 형성된다. 이런 폴리머(18)는 콘택홀을 가려 오픈 시키지 않게 만든다. 한편, 패드 산화막으로 SiON을 사용한 경우에도 C-N 계 화합물 및 Si-C계 화합물의 폴리머가 생성되어 기판(10)상에 증착되고 산소는 탄소와 반응하여 CO 또는 CO2로 휘발된다.In the etching mechanism, part of CF 4 is decomposed to form CF 3 * and fluorine atoms. The fluorine atom reacts with the silicon component of SiO 2 to produce volatile SiF 4 . On the other hand, CF 3 reacts with oxygen to produce COF 2 and fluorine atoms, and COF 2 again reacts with oxygen to produce CO and fluorine atoms. That is, since the number of fluorine atoms increases, the etching of the silicon oxide film continues to produce volatile SiF 4 , CO, and CO 2 . By the way, in the case of using SiN as the pad film, the polymer 18 made of CN compound and Si-C compound is formed on the surface of the pad film 12. This polymer 18 hides the contact hole and does not open it. On the other hand, even when SiON is used as the pad oxide film, a polymer of a CN compound and a Si-C compound is formed and deposited on the substrate 10, and oxygen reacts with carbon to volatilize to CO or CO 2 .

도 1b에서 폴리머(18)를 제거하기 위해 산소 분위기에서 플라즈마 에슁이나 크리닝 공정을 실시한다. 이때 포토레지스트 패턴(16)도 함께 제거되어 SiO2막(14)이 노출된다.In FIG. 1B, a plasma etching or cleaning process is performed in an oxygen atmosphere to remove the polymer 18. At this time, the photoresist pattern 16 is also removed to expose the SiO 2 film 14.

다음, 도 1c에서 실리콘 기판(10) 상에 위치하는 SiN막(12)을 식각하는 공정을 진행하여 콘택홀(24)을 형성한다. 실리콘 기판(10)에 대해 SiN막(12)이 높은 선택비를 가지면서 식각되되 실리콘 기판의 실질적인 손상을 억제하면서 실리콘 기판(10)을 노출시켜야 한다. 실질적인 손상이란, 기판의 과도 식각에 의해 기판상에 형성되는 소자의 누설 전류가 소자 특성을 열화시킨다거나 콘택 저항을 증가시키는 상태를 말한다. 통상 실리콘 기판을 실질적인 손상없이 노출시키기 위해서는 SiN막(12)이 실리콘 기판(10)의 Si성분에 대해 2:1 이하의 선택비를 가져야 한다. 그런데, 포토레지스트 패턴(도1a의 16참조)이 없는 상태에서 2:1 이하의 선택비를 얻는 것이 곤란하다.Next, the contact hole 24 is formed by etching the SiN film 12 positioned on the silicon substrate 10 in FIG. 1C. The SiN film 12 is etched with a high selectivity with respect to the silicon substrate 10, but the silicon substrate 10 should be exposed while suppressing substantial damage of the silicon substrate. Substantial damage refers to a state in which leakage current of an element formed on the substrate due to excessive etching of the substrate deteriorates device characteristics or increases contact resistance. In general, in order to expose the silicon substrate without substantial damage, the SiN film 12 should have a selectivity of 2: 1 or less relative to the Si component of the silicon substrate 10. By the way, it is difficult to obtain a selectivity of 2: 1 or less in the absence of the photoresist pattern (see 16 in FIG. 1A).

즉, SiN막(12a)의 식각 공정에 의해 패턴(12a)이 형성 될때 실리콘 기판(10)에 실리콘 기판에 형성될 반도체 소자의 특성을 열화시키는 리세스(22)가 형성된다. 포토레지스트 마스크 패턴(16)에는 탄소 성분이 포함되어 있는데, 폴리머(18) 제거 단계 시 포토레지스트 마스크 패턴(16)도 동시에 제거되므로, 포토레지스트 마스크 패턴이 존재하는 경우와 대비하여 도 1c의 콘택홀(24) 형성을 위한 식각 단계에서 제공되는 탄소 성분이 줄어들게 된다. 한편, F/C모델(Flouirine-to-Carbon Rate Model)에 의하면 탄소 성분이 줄어들면 식각률이 증가한다. 따라서, 도 1c에 나타난 바와 같이 기판(10)이 과도 식각되어 리세스(22)가 형성된다.That is, when the pattern 12a is formed by the etching process of the SiN film 12a, a recess 22 is formed in the silicon substrate 10 to deteriorate the characteristics of the semiconductor element to be formed on the silicon substrate. The photoresist mask pattern 16 includes a carbon component, and the photoresist mask pattern 16 is also removed at the time of removing the polymer 18, so that the contact hole of FIG. (24) The carbon content provided in the etching step for formation is reduced. Meanwhile, according to the F / C model (Flouirine-to-Carbon Rate Model), the etching rate increases as the carbon content decreases. Accordingly, as shown in FIG. 1C, the substrate 10 is excessively etched to form the recess 22.

따라서, 본 발명이 이루고자 하는 기술적 과제는 포토레지스트 마스크가 없는 상태에서 콘택홀 형성을 위해 실리콘 기판 상에 형성된 실리콘 질화막 또는 실리콘 질화산화막을 식각할때, 실리콘 기판이 과도 식각되는 것을 억제할 수 있는 콘택홀 형성 방법을 제공하는 것이다.Accordingly, a technical problem to be achieved by the present invention is a contact capable of suppressing excessive etching of a silicon substrate when etching a silicon nitride film or a silicon nitride oxide film formed on a silicon substrate to form a contact hole in the absence of a photoresist mask. It is to provide a hole forming method.

도 1a 내지 도 1c는 종래 기술에 따른 콘택홀 형성 방법을 나타내는 공정 단면도들이다.1A to 1C are cross-sectional views illustrating a method of forming a contact hole according to the related art.

도 2a 내지 도 2c는 본 발명에 따른 콘택홀 형성 방법을 나타내는 공정 단면도들이다.2A to 2C are cross-sectional views illustrating a method of forming a contact hole according to the present invention.

본 발명이 이루고자 하는 기술적 과제를 달성하기 위해서, 실리콘 기판을 준비한다. 실리콘 기판 상면에 패드막인 실리콘 질화막(또는 실리콘질화산화막), 실리콘 산화막 및 식각 선택비 완화막을 순차적으로 형성한다. 식각 선택비 완화막은 실리콘 질화막 또는 실리콘 산화질화막을 사용할 수 있다. 식각 선택비 완화막의 두께는 기판 상면에 형성되는 실리콘 질화막의 두께와 실질적으로 동일하거나 더 두껍게 형성된다. 다음, 실리콘 산화막 및 식각 선택비 완화막을 포토레지스트 마스크를 이용하여 패터닝하고, 패터닝된 식각 선택비 완화막 및 실리콘 산화막이 형성된 결과물을 산소 분위기에서 에슁공정을 실시하여 실리콘 질화막 상에 형성된 폴리머와 포토레지스트 패턴을 제거한다.In order to achieve the technical problem to be achieved by the present invention, a silicon substrate is prepared. A silicon nitride film (or silicon nitride oxide film), a silicon oxide film, and an etch selectivity relief film, which are pad films, are sequentially formed on the silicon substrate. The etching selectivity reducing film may use a silicon nitride film or a silicon oxynitride film. The thickness of the etch selectivity reducing layer is formed to be substantially the same as or thicker than that of the silicon nitride layer formed on the upper surface of the substrate. Next, the silicon oxide film and the etching selectivity reducing film are patterned by using a photoresist mask, and the resultant on which the patterned etching selectivity reducing film and the silicon oxide film are formed is subjected to an etching process in an oxygen atmosphere to form a polymer and a photoresist formed on the silicon nitride film. Remove the pattern.

연이어 실리콘 질화막을 탄소 성분과 불소 성분이 포함된 식각 가스를 이용하여 플라즈마 식각함으로써 실리콘 기판을 노출시키는 콘택홀을 형성한다.Subsequently, the silicon nitride film is plasma-etched using an etching gas containing a carbon component and a fluorine component to form a contact hole exposing the silicon substrate.

이하 도 2a 내지 도 2c를 참고로 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to FIGS. 2A to 2C.

도 2a에서, 실리콘 기판(40) 상에 패드막인 실리콘질화막(SiN) 또는 실리콘산화질화막(SiON)(42), 층간 절연막인 실리콘산화막(SiO2)(44) 및 실리콘질화막(SiN)(46)이 순차적으로 형성되어 있다. 실리콘질화막(SiN)(46)은 콘택홀 형성 시 기판이 과도하게 식각되는 것을 억제하기 위해 제공된 식각 선택비 완화막이다. 식각 선택비 완화용의 상부 SiN막(46)의 두께는 패드막인 하부 SiN막(42)과 실질적으로 같거나 더 두껍게 형성한다. SiN막(46) 상부에 탄소와 산소 및 수소 화합물인 소정의 포토레지스트 패턴(48)이 형성되어 있다. 포토레지스트 패턴(48)을 마스크로 이용하고 CF4가스를 시용하여 SiN(46) 및 SiO2(44)를 플라즈마 식각하여 패턴(46 및 44)과 개구부(52)를 형성한다. 이때에도 도 1a에서와 같이 실리콘 기판(40) 상부에 형성된 SiN막 (42) 상면에 C-N계 화합물 및 Si-C계 화합물로 이루어진 폴리머(50)가 형성된다. 이런 폴리머(50)는 콘택홀을 오픈시키지 않게 만든다. 한편, 패드 산화막으로 SiON을 사용한 경우에도 탄소와 질소 화합물 및 실리콘과 탄소 화합물의 폴리머가 생성되어 기판(40)상에 증착되고 산소는 탄소와 반응하여 CO 또는 CO2로 휘발된다.In FIG. 2A, a silicon nitride film (SiN) or silicon oxynitride film (SiON) 42 as a pad film, a silicon oxide film (SiO 2 ) 44 as an interlayer insulating film, and a silicon nitride film (SiN) 46 are formed on a silicon substrate 40. ) Are formed sequentially. The silicon nitride film (SiN) 46 is an etching selectivity mitigating film provided to suppress excessive etching of the substrate when forming contact holes. The thickness of the upper SiN film 46 for reducing the etching selectivity is formed to be substantially the same as or thicker than the lower SiN film 42 serving as the pad film. A predetermined photoresist pattern 48 of carbon, oxygen, and hydrogen compounds is formed on the SiN film 46. Using photoresist pattern 48 as a mask and CF 4 gas, SiN 46 and SiO 2 44 are plasma-etched to form patterns 46 and 44 and openings 52. In this case, as shown in FIG. 1A, the polymer 50 including the CN compound and the Si—C compound is formed on the upper surface of the SiN film 42 formed on the silicon substrate 40. This polymer 50 does not open the contact hole. On the other hand, even when SiON is used as the pad oxide film, polymers of carbon and nitrogen compounds and silicon and carbon compounds are formed and deposited on the substrate 40, and oxygen reacts with carbon and volatilizes to CO or CO 2 .

도 2b에서, 도 1b에서와 같이 폴리머(50)를 제거하기 위해 산소 분위기에서 플라즈마 에슁이나 크리닝 공정을 실시한다. 이때 포토레지스트 패턴(48)도 함께 제거되어 SiO2막(44) 상부의 SiN막(46)이 노출되고 개구부(52)에 의해 기판(40) 상부에 형성된 SiN막(42)이 노출된다.In FIG. 2B, a plasma etching or cleaning process is performed in an oxygen atmosphere to remove the polymer 50 as in FIG. 1B. At this time, the photoresist pattern 48 is also removed to expose the SiN film 46 on the SiO 2 film 44 and the SiN film 42 formed on the substrate 40 by the opening 52.

다음, 도 2c에서 실리콘 기판(40) 상에 위치하는 SiN막(42)을 식각하는 공정을 진행하여 콘택홀(56)을 형성한다. 이때 상부 SiN막(46) 및 하부 SiN막(42)이 동시에 식각되어, 상부 SiN막의 두께가 얇게 되고 하부 SiN막(42)에는 콘택홀이 형성된다. 상부 콘택홀(56) 형성 시 SiN막(42) 하부의 실리콘 기판(40)도 일부 식각되어 리세스(54)가 형성되나 도 1c의 리세스(22)네 비해 상당히 얇게 형성되어 있다. 따라서, 실리콘 기판(40) 상에 형성될 반도체 소자의 특성에 영향을 줄 정도의 누설 전류가 발생하는 것을 억제할 수 있으며, 양호한 접촉 저항을 확보할 수 있다.Next, a process of etching the SiN film 42 positioned on the silicon substrate 40 in FIG. 2C is performed to form the contact hole 56. At this time, the upper SiN film 46 and the lower SiN film 42 are etched simultaneously, so that the thickness of the upper SiN film becomes thin and a contact hole is formed in the lower SiN film 42. When the upper contact hole 56 is formed, the silicon substrate 40 under the SiN layer 42 is also partially etched to form the recess 54, but is formed to be considerably thinner than the recess 22 of FIG. 1C. Therefore, it is possible to suppress the occurrence of leakage currents that affect the characteristics of the semiconductor element to be formed on the silicon substrate 40, and to ensure good contact resistance.

구체적으로, 콘택홀(56) 형성 과정을 살펴보면, CF4식각 가스를 이용하여플라즈마 식각을 실시한다. 식각 가스인 CF4는 전술한 바와 같이 CF3 *와 불소 원자로 해리되고 불소 원자는 SiO2막(44)를 덮고 있는 SiN막(46)의 실리콘 성분 및 실리콘 기판(40) 상에 형성된 SiN막(42)의 실리콘 성분과 반응하여 휘발성인 SiF4를 생성하면서 SiN막(42 및 46)이 식각되면서, 불휘발성인 C-N계 화합물 및 C-Si계 화합물의 폴리머가 SiN막(42, 46) 상에 형성된다. 그런데, 이런 폴리머는 계속되는 플라즈마 상태의 식각용 래디컬에 의해 그 조직이 파괴되어 탄소 성분이 반응 가스 내로 확산된다. 결과적으로 도 1c의 공정에 비해 식각 가스의 탄소 성분이 증가되며, 식각 선택비가 감소된다.Specifically, referring to the process of forming the contact hole 56, plasma etching is performed using CF 4 etching gas. As described above, CF 4, which is an etching gas, is dissociated into CF 3 * and a fluorine atom, and the fluorine atom is a silicon component of the SiN film 46 covering the SiO 2 film 44 and a SiN film formed on the silicon substrate 40 ( As the SiN films 42 and 46 are etched while reacting with the silicon component of 42) to produce volatile SiF 4 , polymers of nonvolatile CN-based and C-Si-based compounds are deposited on the SiN films 42 and 46. Is formed. However, such a polymer is destroyed by the radicals for etching in the plasma state, and the carbon component diffuses into the reaction gas. As a result, the carbon component of the etching gas is increased and the etching selectivity is reduced compared to the process of FIG. 1C.

한편, 도 1c의 콘택홀 형성 시에는 SiO2막(14)이 식각 가스에 직접 노출되는 반면 도 2c에서는 SiO2막(44)이 식각 가스에 노출되지 않고 SiN막(46)이 노출되어 있다. SiO2막(44)의 산소 성분은 전술한 바와 같이 식각가스의 탄소 성분과 결합하여 궁극적으로 불소 원자 수를 증가시킨다. 따라서 식각선택비가 증가하였다. 그러나 본명의 도 2c에서는 SiN막(46)의 실리콘 성분과 질소 성분은 식각 가스의 탄소 성분과 반응하여 불휘발성의 폴리머를 생성하는 것으로 불소 원자 수를 증가시키지 않는다. 따라서, 도 1c의 콘택홀 공정과 비교하면, 콘택홀 공정 중에 불소 원자 생성이 SiN막(46)에 의해 차단되므로, 불소 원자 수가 상대적으로 적게되어 식각 선택비가 감소하게 된다.Meanwhile, in forming the contact hole of FIG. 1C, the SiO 2 film 14 is directly exposed to the etching gas, while in FIG. 2C, the SiO 2 film 44 is not exposed to the etching gas and the SiN film 46 is exposed. The oxygen component of the SiO 2 film 44 combines with the carbon component of the etching gas as described above and ultimately increases the number of fluorine atoms. Therefore, the etching selectivity increased. However, in FIG. 2C of the real name, the silicon component and the nitrogen component of the SiN film 46 react with the carbon component of the etching gas to generate a nonvolatile polymer, which does not increase the number of fluorine atoms. Accordingly, compared with the contact hole process of FIG. 1C, since the generation of fluorine atoms is blocked by the SiN film 46 during the contact hole process, the number of fluorine atoms is relatively small, thereby reducing the etching selectivity.

이런 현상은 SiO2막(44) 상부에 SiN(46) 대신 SiON을 사용한 경우에도 나타난다. SiN막(46)을 사용한 경우와 다른 점은 막을 구성하는 물질로 산소가 포함되어있으나, SiO2막(14)의 산소 성분이 탄소 성분과 반응하는 반응률에 비해 SiON막의 산소 성분이 탄소 성분과 반응하는 반응률이 작을 것이므로, SiON이 식각 가스에 노출된 경우가 불소 원자의 발생이 상대적으로 적게되어 식각 선택비가 감소하게 된다.This phenomenon occurs even when SiON is used instead of SiN 46 on the SiO 2 film 44. The difference from the case of using the SiN film 46 is that the material constituting the film contains oxygen, but the oxygen component of the SiON film reacts with the carbon component compared to the reaction rate at which the oxygen component of the SiO 2 film 14 reacts with the carbon component. Since the reaction rate will be small, when the SiON is exposed to the etching gas, the generation of fluorine atoms is relatively low, and the etching selectivity is reduced.

본 발명에서는 식각 가스로 CF4로 한정 설명하였으나 탄소 성분과 불소 성분으로 이루어진 각종 가스 CxFy를 사용할 수 있다. 또한, 식각 선택비를 더욱 낮추기 위해 수소 성분을 포함시킬 수 있으며, 나아가 Ar, N2와 같은 비활성 가스를 첨가할 수도 있다.In the present invention, the etching gas is limited to CF 4 , but various gases C x F y including carbon and fluorine may be used. In addition, a hydrogen component may be included to further lower the etching selectivity, and further, an inert gas such as Ar and N 2 may be added.

실리콘 기판을 노출시키는 콘택홀을 형성할때 기판 상에 형성되는 SiO2막 상면에 SiN막 또는 SiON막을 형성하여 플라즈마 식각 공정 시 탄소 성분의 함량을 증가시키고 또는 불소 성분의 함량을 감소시킴으로써, 포토레지스트 마스크 없이 콘택홀을 형성하더라도 기판이 과도 식각되지 않는다.When forming a contact hole exposing a silicon substrate, a SiN film or a SiON film is formed on the upper surface of the SiO 2 film formed on the substrate to increase the carbon content or reduce the fluorine content in the plasma etching process. Even if the contact hole is formed without the mask, the substrate is not excessively etched.

본 발명을 콘택홀을 형성하기 위한 SiN막 또는 SiON막 식각 공정에 대해서만 예를 들어 설명하였으나, 양호한 접촉저항을 확보하기 위한 잔사 처리 공정에도 본 발명이 적용될 수 있다.Although the present invention has been described by way of example only for the SiN film or SiON film etching process for forming contact holes, the present invention can also be applied to a residue treatment process for ensuring good contact resistance.

Claims (3)

실리콘 기판을 준비하는 단계,Preparing a silicon substrate, 상기 실리콘 기판 상면에 패드막, 실리콘 산화막 및 식각 선택비 완화막을 순차적으로 형성하는 단계,Sequentially forming a pad film, a silicon oxide film, and an etch selectivity mitigating film on an upper surface of the silicon substrate; 상기 실리콘 산화막 및 상기 식각 선택비 완화막을 포토레지스트 마스크를 이용하여 패터닝하는 단계,Patterning the silicon oxide layer and the etch selectivity reducing layer using a photoresist mask; 패터닝된 상기 식각 선택비 완화막 및 상기 실리콘 산화막이 형성된 결과물을 산소 분위기에서 에슁공정을 실시하여 상기 패드막 상에 형성된 폴리머와 상기 포토레지스트 패턴을 제거하는 단계, 및Performing an etching process on the patterned etch selectivity reducing layer and the silicon oxide layer on the patterned product to remove the polymer and the photoresist pattern formed on the pad layer; and 상기 패드막을 탄소 성분과 불소 성분이 포함된 식각 가스를 이용하여 플라즈마 식각함으로써 상기 실리콘 기판을 노출시키는 콘택홀을 형성하는 단계를 포함하는 반도체 메모리 소자의 제조 방법.Forming a contact hole exposing the silicon substrate by plasma etching the pad layer using an etching gas containing a carbon component and a fluorine component. 제 1 항에 있어서, 상기 패드막은 실리콘 질화막 또는 실리콘산화질화막으로 이루어지고, 상기 식각 선택비 완화막은 실리콘 질화막 또는 실리콘산화질화막인 반도체 메모리 소자의 제조 방법.The method of claim 1, wherein the pad layer is formed of a silicon nitride layer or a silicon oxynitride layer, and the etching selectivity reducing layer is a silicon nitride layer or a silicon oxynitride layer. 제 1 항에 있어서, 상기 식각 선택비 완화막은 상기 패드막의 두께와 실질적으로 동일하거나 더 두껍게 형성되는 반도체 메모리 소자의 제조 방법.The method of claim 1, wherein the etch selectivity mitigating layer is formed to be substantially the same as or thicker than the thickness of the pad layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107833831A (en) * 2016-09-15 2018-03-23 东京毅力科创株式会社 The method being selectively etched to silica and silicon nitride

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107833831A (en) * 2016-09-15 2018-03-23 东京毅力科创株式会社 The method being selectively etched to silica and silicon nitride

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