KR20020007682A - Semiconductor package - Google Patents

Abstract

PURPOSE: A semiconductor package is provided to improve a heat radiation capacity, by adhering a heat radiation unit having a superior heat conductivity to one surface of a semiconductor chip and a lead so that the heat from the semiconductor chip is easily exhausted to the exterior through the lead and heat radiation unit. CONSTITUTION: A plurality of input/output pads(1c) are formed on the first surface of the first semiconductor chip(1) including the first and second surfaces(1a,1b) which are almost planar. A plurality of leads(4) having the first and second surfaces(4a,4b) are disposed on the outer circumference of the first semiconductor chip. The heat radiation unit(3) is adhered to the first semiconductor chip and the second surface of the lead, including the first and second surfaces(3a,3b) which are almost planar. A plurality of electrical connection units(5) electrically connect the input/output pads of the first semiconductor chip with the leads of the first semiconductor chip. An encapsulating material encapsulates the first semiconductor chip, the lead and the electrical connection unit.

Description

Semiconductor Package {Semiconductor package}

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package having a relatively low cost, maximizing heat dissipation performance of a semiconductor chip, and having a relatively thin thickness using a lead frame.

In general, a multilayer semiconductor package includes a plurality of semiconductor chips vertically in a substrate such as a printed circuit board, a circuit tape, a circuit film, or a lead frame. After lamination, it refers to bonding the stacked semiconductor chips or the semiconductor chips and the substrate with electrical connection means such as conductive wires. Such a multilayer semiconductor package is manufactured in large quantities since it is possible not only to realize high capacity and high performance by mounting a plurality of semiconductor chips inside the body formed of an encapsulant, but also to increase the mounting density of the motherboard. It is becoming a trend.

An example of such a stacked semiconductor package 100 'is shown in FIG.

As shown, first, a conductive circuit pattern including a plurality of bond fingers 3 'is formed on an upper surface of the resin layer 2' and a lower surface of the ball land 4 '. ) Is formed, and the upper and lower circuit patterns are provided with a substrate 1 'interconnected by conductive via holes 5'. Here, the conductive circuit pattern including the bond finger 3 'and the borland 4' is a conventional copper trace.

The first semiconductor chip 10 'is bonded to the center of the upper surface of the substrate 1' by an adhesive means, and the second semiconductor chip 20 is bonded to the upper surface of the first semiconductor chip 10 'by the adhesive means. ') Is glued. Here, the second semiconductor chip 20 'is provided with a smaller one than the size of the first semiconductor chip 10'. In addition, a plurality of input / output pads 10a 'and 20a' are formed on upper surfaces of the first semiconductor chip 10 'and the second semiconductor chip 20'.

Bond fingers 3 'of the substrate 1' are formed by conductive wires 30 'on the input / output pads 10a' and 20a 'of the first semiconductor chip 10' and the second semiconductor chip 20 '. ), A plurality of conductive balls 40 'are fused to the ball lands 4' formed on the lower surface of the substrate 1 '. This conductive ball 40 'is later fused to a predetermined pattern on the motherboard.

The first semiconductor chip 10 ′, the second semiconductor chip 20 ′, and the conductive wire 30 ′ disposed on the upper surface of the substrate 1 ′ are epoxy-molded to be protected from external impact or contact. It is encapsulated with an encapsulant such as an epoxy molding compound or a glove top to form a predetermined body 60 '.

In the figure, reference numeral 6 'is a cover coat coated on the surface of the circuit pattern to protect it from the external environment.

In the semiconductor package 100 ′, electrical signals of the first semiconductor chip 10 ′ and the second semiconductor chip 20 ′ may be input / output pads 10 a ′, 20 a ′, conductive wires 30 ′, and bond fingers 3. '), The conductive via hole (5'), the ball land (4 ') and the conductive ball 40' through the exchange of electrical signals with the motherboard not shown.

However, such a conventional semiconductor package has a problem that the overall price of the semiconductor package is increased by using a substrate such as an expensive printed circuit board, a circuit tape, or a circuit film, thereby lowering the price competitiveness.

In addition, since the entire semiconductor chip mounted on the substrate is sealed by the body formed of the substrate and the sealing material, there is a problem that the heat dissipation performance of the semiconductor chip is reduced.

In addition, the overall thickness of the semiconductor package is increased by sequentially stacking the conductive balls, the substrate, the semiconductor chip, and the body, and thus there is a problem in that the thickness of the electronic product adopting the barrier is increased.

Therefore, the present invention has been made to solve the above-mentioned conventional problems, to provide a semiconductor package using a lead frame relatively inexpensive.

Another object of the present invention is to provide a semiconductor package having excellent heat dissipation performance of a semiconductor chip.

Another object of the present invention is to provide a laminated semiconductor package having a relatively thin thickness.

1 is a cross-sectional view showing a conventional semiconductor package.

2A to 2C are cross-sectional views showing a semiconductor package and a stacked state of a package according to the present invention.

3A and 3B are cross-sectional views illustrating a semiconductor package according to another embodiment of the present invention.

-Description of the main symbols in the drawings-

11,12; Semiconductor package according to the present invention

One; First semiconductor chip 1a; First page 1b; Second page 1c; I / O pad

2; Second semiconductor chip 2a; First side 2b; Second side 2c; I / O pad

3; Heat sink 3a; First page 3b; The second page

4; Lead 4a; First side 4b; Second side 4c; rand

5; Electrical connection means

6a; Solder paste 6b; Solder post

7; Bonding means 8; Body

9; Conductive ball

In order to achieve the above object, the semiconductor package according to the present invention has a first plane and a second plane which are substantially planar, and the first surface comprises: a first semiconductor chip having a plurality of input / output pads; A plurality of leads having a first surface and a second surface and arranged at an outer circumference of the first semiconductor chip; the first semiconductor chip and a second surface of the lead having a first surface and a second surface that are substantially planar; Heat dissipation means bonded to the surface by an adhesive means; A plurality of electrical connection means for electrically connecting the input / output pad and the lead of the first semiconductor chip; It characterized in that it comprises a body formed by encapsulating the first semiconductor chip, the lead and the electrical connection means with an encapsulant.

Preferably, the second surface of the first semiconductor chip and the second surface of the lead are located on the same plane.

At least one land exposed to the outside of the body may be further formed in a predetermined region of the first surface of each lead.

The thickness of the lead including the land is preferably formed thicker than the lead thickness of the remaining portion.

Solder may be plated on lands of the leads exposed to the outside of the body.

The heat radiating means may have a circumference further extended to the outer circumferential side of the lead.

A conductive ball may be further fused to the land.

Solder posts may be formed on the first surface of the heat dissipation means further extended toward the outer circumference of the lead to be thicker than the thickest thickness of the lead.

A second semiconductor chip having substantially first and second surfaces on a first surface of the first semiconductor chip is further bonded to the second surface, and a plurality of input / output pads are formed on the second surface of the first semiconductor chip. The and leads can be interconnected by electrical connection means.

The heat dissipation means may be formed larger than the width of the first semiconductor chip and smaller than the width of the lead.

The semiconductor package may be stacked in a plurality of lands with conductive balls interposed therebetween, and the conductive balls of one semiconductor package may be connected to the second surface of a lead of another semiconductor package positioned below the semiconductor package.

As described above, according to the semiconductor package according to the present invention, a semiconductor package having a cost down as a whole can be obtained by using a relatively inexpensive lead.

In addition, since the heat dissipation means having excellent thermal conductivity is attached to one surface of the semiconductor chip and the lead, heat of the semiconductor chip is easily dissipated to the outside through the leads and the heat dissipation means, thereby obtaining a semiconductor package having improved heat dissipation performance.

In addition, the specific semiconductor chip is located between the lead and the lead, so that the thickness of the semiconductor chip is offset by the lead thickness, thereby obtaining a semiconductor package of even thinner thickness.

Finally, the semiconductor package as described above can be stacked in a large number, thereby increasing the capacity and function, but not increasing the mounting density.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

2A to 2C are cross-sectional views showing the semiconductor package 11 and the stacked state of the package according to the present invention.

First, as shown in FIGS. 2A and 2B, the first surface 1a and the second surface 1b are substantially planar, and a plurality of input / output pads 1c are provided on the first surface 1a (lower surface). Is provided with a first semiconductor chip (1).

The second semiconductor chip 2 is attached to the second surface 1b of the first semiconductor chip 1 by an electrically non-conductive and thermally conductive bonding means 7.

The second semiconductor chip 2 also has a first surface 2a and a second surface 2b, and a plurality of input / output pads 2c are formed on the first surface 2a (lower surface). Of course, the size of the second semiconductor chip 2 is larger than that of the first semiconductor chip 1, so that the input / output pad 2c of the second semiconductor chip 2 is the second surface of the first semiconductor chip 1. It does not interfere with (1b).

A plurality of leads 4 having a first surface 4a and a second surface 4b are arranged at the outer circumference of the first semiconductor chip 1 and the second semiconductor chip 2. Here, the second surface 4b of the lead 4 and the second surface 2b of the second semiconductor chip 2 form the same plane.

In addition, the second surfaces 2b and 4b of the second semiconductor chip 2 and the lead 4 have a first surface 3a and a second surface 3b which are also substantially planar as the bonding means 7. The heat radiating means 3 is adhere | attached. The heat dissipation means 3 is preferably a material having excellent heat dissipation, such as metallic (Cu), iron (Fe), aluminum (Al) series and the like.

Here, in order to prevent electrical short between the lead 4 and the heat dissipation means 3, the adhesive means between the lead 4 and the heat dissipation means 3 must be electrically insulating (for example, epoxy Adhesive or double-sided adhesive tape, etc.) shall be used.

In addition, as is well known, the lead 4 is an iron (Fe) -based or copper (Cu) -based metal, and is located in an area of the first surface 4a of the lead 4 that is later connected by electrical connection means. A silver (Ag) plating layer (not shown) may be formed.

Further, lands 4c that are approximately twice as thick as the thickness of the remaining leads 4 are formed on the first surface 4a of each lead 4. That is, the land 4c thicker than the thickness of the remaining leads 4 is formed by protruding substantially in a direction perpendicular to the first surface 4a of the lead 4. The land 4c is formed by a half etching method in which only about half of the lead 4 is removed by etching with a chemical solution during the manufacturing process.

Subsequently, the input / output pads 1c and 2c of the first semiconductor chip 1 and the second semiconductor chip 2 and the first surface 4a of the lead 4 are made of aluminum wire or gold wire. Electrical connection means 5 such as Au Wire, that is, interconnected by conductive wires.

In the connection state, the input and output pads 1c and 2c of the first semiconductor chip 1 and the second semiconductor chip 2 are connected to the same lead 4 or to each of the different leads 4. Conductive wires).

Here, the electrical connecting means 5 is connected to the silver plating layer formed on the first surface 4a of the lid 4, thereby making the connection more smoothly and the connecting force also improved.

In addition, the first semiconductor chip 1, the second semiconductor chip 2, the lead 4 and the electrical connection means 5 is an encapsulant such as an epoxy molding compound or a glop top. It is encapsulated in the form of a predetermined body 8, the land 4c of the lid 4 is exposed to the outside of the body (8).

In addition, a conductive ball 9 such as a solder ball is fused to the land 4c formed on the first surface 4a of the lead 4. The conductive ball 9 is later mounted on a specific pattern of the motherboard.

In addition, the entire second surface 3b of the heat dissipation means 3 and the entire side surface thereof are exposed to the outside of the body 8, thereby improving heat dissipation performance of the semiconductor chips 1 and 2. That is, the heat of the first semiconductor chip 1 and the second semiconductor chip 2 is not only dissipated to the outside air through the heat dissipation means 3, but also to the outside through the lead 4 to dissipate overall heat. Performance is maximized.

Meanwhile, as shown in FIG. 2B, the heat dissipation means 3 may be larger than the width of the first semiconductor chip 1 and the second semiconductor chip 2 and smaller than the total width of the lead 4. When the heat dissipation means 3 is smaller than the width of the entire lead 4 as described above, a plurality of heat dissipation means 3 may be stacked as shown in FIG. 2C. That is, the conductive balls 9 are fused to the lands 4c of the semiconductor package, and the second surface 4b of the lead 4 of the other semiconductor package is connected to the lower portion of the conductive balls 9 so that a plurality of semiconductor packages are connected. Can be laminated. In this way, more semiconductor packages can be mounted in the same mounting area.

3A and 3B are cross-sectional views showing a semiconductor package 12 according to another embodiment of the present invention.

First, a semiconductor chip 1 having a first surface 1a and a second surface 1b which are substantially planar, and on which a plurality of input / output pads 1c are formed is provided on the first surface 1a (lower surface). .

A plurality of leads 4 having a first surface 4a and a second surface 4b are arranged on the outer circumference of the semiconductor chip 1, and the second surface 4b of the lead 4 and the semiconductor are arranged. The second surface 1b of the chip 1 is coplanar.

In addition, the heat dissipating means 3 having the first and second surfaces, which are also substantially planar, is bonded to the second surfaces 1b and 4b of the semiconductor chip 1 and the lead 4 by the bonding means 7. have. As described above, the heat dissipation means 3 is metallic such as copper (Cu), iron (Fe), and aluminum (Al).

In addition, as described above, the lead 4 is an iron (Fe) -based or copper (Cu) -based metal, and is located in a region of the first surface 4a of the lead 4 that is connected by a later electrical connection means. A silver (Ag) plating layer (not shown) is formed.

In addition, lands 4c, which are approximately twice as thick as the thickness of the remaining leads 4, are formed on the first surface 4a of each of the leads 4, and the lands 4c are formed during the manufacturing process. Only about half of 4) is formed by the half etching method, which is removed by etching with chemical solution.

Subsequently, the input / output pad 1c of the semiconductor chip 1 and the first surface 4a of the lead 4 are electrically connected to each other 5 such as aluminum wire or gold wire. And interconnected by conductive wires.

The semiconductor chip 1, the lead 4, and the electrical connection means 5 are encapsulated with an encapsulant such as an epoxy molding compound or a glop top to form a predetermined body 8. The land 4c of the lid 4 is exposed to the outside of the body 8.

A solder paste 6a having a predetermined thickness is fused to the land 4c formed on the first surface 4a of the lead 4. The solder paste 6a serves to be connected to a specific pattern of the motherboard when the semiconductor package 12 is later mounted on the motherboard.

In addition, the entire second surface and the entire side surface of the heat dissipation means 3 are exposed to the outside of the body 8, so that the heat dissipation performance of the semiconductor chip 1 is improved. That is, the heat of the semiconductor chip 1 is not only dissipated to the outside air through the heat dissipation means 3, but also to the outside through the lead 4 to maximize the overall heat dissipation performance.

On the other hand, the heat dissipation means 3 can be expanded larger than the total area of the lead 4 located on the outer periphery of the semiconductor chip 1 as shown, and thus, the heat dissipation performance can be further improved. In addition, a plurality of solder posts 6b having a predetermined thickness are bonded to the first surface of the heat dissipation means 3, which is the outer circumference of the lead 4, to be fused to a specific pattern of the motherboard so that the semiconductor package 12 has a more rigid mounting structure. Formed. Here, the solder post 6b also serves to transfer the heat of the heat dissipation means 3 toward the motherboard, thereby further improving the overall heat dissipation performance of the semiconductor package 12.

In addition, as shown in FIG. 3B, the conductive balls 9 may be further fused to the lands 4c of the leads 4 so that the mounting work on the motherboard may be facilitated. At this time, the thickness of the solder post (6b) is made thicker in consideration of the thickness of the conductive ball (9).

As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modifications may be made without departing from the scope and spirit of the present invention.

According to the semiconductor package according to the present invention as described above, it is possible to obtain a semiconductor package having a total cost down by using a relatively inexpensive lead.

In addition, since the heat dissipation means having excellent thermal conductivity is adhered to one surface of the semiconductor chip and the lead, the heat of the semiconductor chip is easily dissipated to the outside through the lead and the heat dissipation means to obtain a semiconductor package with improved heat dissipation performance. There is.

In addition, since the specific semiconductor chip is located between the lead and the lead, the thickness of the semiconductor chip is canceled by the lead thickness, and thus there is an effect that a semiconductor package having a thinner thickness can be obtained.

Finally, the semiconductor package as described above can be stacked in a large number, thereby increasing the capacity and function, but not increasing the mounting density.

Claims (10)

A first semiconductor chip having a first plane and a second plane which are substantially planar, and having a plurality of input / output pads formed thereon; A plurality of leads having a first surface and a second surface and arranged on an outer circumference of the first semiconductor chip; Heat dissipation means having a first plane and a second surface which are substantially planar, and adhered to said second surface of said first semiconductor chip and said lead by an adhesive means; A plurality of electrical connection means for electrically connecting the input / output pad and the lead of the first semiconductor chip; And a body formed by encapsulating the first semiconductor chip, the lead and the electrical connection means with an encapsulant. The semiconductor package of claim 1, wherein at least one land further exposed to the outside of the body is further formed in a predetermined region of the first surface of each lead. The semiconductor package of claim 2, wherein a thickness of the lead including the lands is thicker than a thickness of the remaining portions of the leads. The semiconductor package of claim 3, wherein a solder is plated on lands of the leads exposed to the outside of the body. The semiconductor package of claim 1, wherein the heat dissipation means has a circumference extending further toward an outer circumferential side of the lead. The semiconductor package of claim 2, wherein a conductive ball is further fused to the land. 6. The semiconductor package according to any one of claims 5 to 7, wherein a solder post is formed on the first surface of the heat dissipation means further extended toward the outer circumference of the lead, the solder post being thicker than the thickest thickness of the lead. The second semiconductor chip of claim 1, wherein the first semiconductor chip has a first surface and a second surface, and a second semiconductor chip having a plurality of input / output pads is further bonded to the second surface. A semiconductor package, wherein the input / output pads and leads of the two semiconductor chips are interconnected by electrical connection means. The semiconductor package according to any one of claims 1 to 8, wherein the heat dissipation means is larger than the width of the first semiconductor chip and smaller than the width of the lead. The semiconductor package of claim 9, wherein a plurality of the semiconductor packages are stacked with conductive balls interposed in a land, and the conductive balls of one semiconductor package are connected to a second surface of a lead of another semiconductor package located under the semiconductor package. Semiconductor package characterized in that the.