KR20020002976A - Semiconductor device capable of improving adhesion characteristic between upper electrode and interlayer insulating layer and method for forming the same - Google Patents

Abstract

PURPOSE: A method of fabricating a semiconductor memory device for improving an adhesive strength between an upper electrode and an interlayer insulating layer is provided to prevent an unfastening effect of each layer by enhancing an adhesive strength between an upper electrode and an interlayer insulating layer. CONSTITUTION: A lower adhesive layer(12), a lower electrode layer(13), a ferroelectric layer(14), an upper electrode layer(15), and a hard mask layer are formed on an interlayer insulating layer(11) of a semiconductor substrate(10). An upper electrode layer pattern is formed by etching the upper electrode layer(15). A pattern is formed by etching selectively the ferroelectric layer(14) and the lower electrode layer(13). A metal oxide layer(16A) is formed by oxidizing the hard mask layer. An interlayer insulating layer(17) is formed on a whole surface of the above structure. The upper electrode layer(15) is exposed by etching selectively the interlayer insulating layer(17) and the metal oxide layer(16A). A contact hole is formed on a sidewall of the exposed electrode layer(15).

Description

Semiconductor device capable of improving adhesion characteristic between upper electrode and interlayer insulating layer and method for forming the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor memory device manufacturing, and more particularly, to a method of manufacturing a semiconductor memory device capable of improving the adhesion between the upper electrode and the interlayer insulating film.

By using a ferroelectric material in a capacitor in a semiconductor memory device, development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a conventional dynamic random access memory (DRAM) device has been in progress. A ferroelectric random access memory (FeRAM) device is a nonvolatile memory device that not only stores stored information even when a power supply is cut off, but also has an operation speed comparable to that of a conventional DRAM.

Ferroelectric materials, such as SrBi ₂ Ta ₂ O ₉ or Pb (ZrTi _x ) O ₃ , are used as storage materials for FeRAM devices. Ferroelectrics have dielectric constants ranging from hundreds to thousands at room temperature, and have two stable remnant polarization states, making them thinner and enabling their application to nonvolatile memory devices. Nonvolatile memory devices using a ferroelectric thin film use the principle of inputting a signal by adjusting the direction of polarization in the direction of an applied electric field and storing digital signals 1 and 0 by the direction of residual polarization remaining when the electric field is removed. .

Since the process of forming the ferroelectric capacitor of the FeRAM device involves a high temperature heat treatment process, the upper and lower electrodes of the capacitor are formed of Pt, Ir, Ru, oxides or mixtures thereof having excellent oxidation resistance. However, such a material has a poor adhesion property with a silicon oxide film which is widely used as a lower insulator, so that the film is lifted in a subsequent heat treatment process. In order to prevent such a film lifting, a glue layer is formed of metal oxides such as TiO ₂ , Al ₂ O ₃ , Ta ₂ O _5, and the like between the lower electrode and the interlayer insulating film. On the other hand, since the adhesive layer is not formed between the upper electrode and the interlayer insulating film covering the upper electrode, the cleaning solution is impregnated into the interface between the upper electrode and the interlayer insulating film in the cleaning process performed after the formation of the contact hole exposing the upper electrode. There is a problem that occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor memory capable of effectively preventing film jamming by improving adhesion between an upper electrode and an interlayer insulating film.

1 to 3 is a cross-sectional view of the FeRAM device manufacturing process according to an embodiment of the present invention.

* Description of reference numerals for the main parts of the drawings *

13: lower electrode film 14: ferroelectric film

15: upper electrode film 16: hard mask

16A: metal oxide film

In order to achieve the above object, the present invention provides a capacitor including a lower electrode film, a dielectric film, and an upper electrode film stacked on an upper surface of a semiconductor substrate, and oxidizes a hard mask, which is an etching mask for patterning the upper electrode film, to form an adhesive layer. A first step of forming a metal oxide film used as; A second step of forming an interlayer insulating film on the entire structure in which the first step is completed, and contacting a part of the interlayer insulating film with the metal oxide film; And selectively etching the interlayer dielectric layer and the metal oxide layer to expose the upper electrode on a bottom surface thereof, and forming contact holes on the sidewalls of the interlayer dielectric layer and the metal oxide layer. Provide a method.

According to the present invention, a metal oxide film serving as an adhesive layer is formed by oxidizing a hard mask for forming an upper electrode pattern, an interlayer insulating film is formed on the entire structure, and the sidewall insulating film and the metal oxide film are etched to form sidewalls thereof. By forming a contact hole for exposing the metal oxide film and the interlayer insulating film on the bottom and exposing the upper electrode on the bottom surface, it is characterized in that the adhesion between the interlayer insulating film and the upper electrode is weakened in the wet cleaning process performed after the contact hole is formed. . As such, the adhesive layer between the upper electrode and the interlayer insulating film prevents the cleaning liquid from penetrating in the cleaning process and effectively prevents the lifting of the film. Thus, an etchant having a higher cleaning ability may be used during the cleaning process. In addition, the present invention has the advantage of forming an adhesive layer coinciding with the upper electrode without additional pattern forming process by oxidizing the hard mask layer as an adhesive layer.

Hereinafter, a method of manufacturing a FeRAM device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

First, as shown in FIG. 1, the lower adhesive layer 12, the lower electrode layer 13, and the ferroelectric are formed on the interlayer insulating film 11 covering the semiconductor substrate 10 on which the substructure (not shown) including the transistor and the like is completed. After the film 14 and the upper electrode film 15 are formed and the hard mask 16 is formed on the upper electrode film 15, the hard electrode is used as an etching mask and the upper electrode film 15 is formed. The upper electrode film 15 is etched to form a pattern, and the ferroelectric film 14 and the lower electrode film 13 are selectively etched to form a pattern. The hard mask 16 is formed by depositing TiN, TaN, WN, etc. by metal organic chemical vapor deposition or atomic layer deposition. The upper electrode film 15 is formed of Pt, Ir, Ru, or an oxide film or a mixed film thereof.

Then, as shown in FIG. 2, the hard mask 16 is oxidized while performing heat treatment for restoring the deteriorated ferroelectric characteristics to form a metal oxide film 16A to be used as an adhesive film. The heat treatment is performed at 400 ° C. to 1000 ° C. under an oxygen atmosphere containing at least one of O ₂ , N ₂ , Ar, O ₃ , He, Ne, or Kr.

Next, as shown in FIG. 3, the interlayer insulating film 17 is formed on the entire structure, and the interlayer insulating film 17 and the metal oxide film 16A are selectively etched to form the upper electrode film 15 on the bottom thereof. A contact hole for exposing the interlayer insulating film 18 and the metal oxide film portion 16A is formed on the sidewall thereof.

Thereafter, a general FeRAM manufacturing process such as a process of forming a metal wiring connected to the capacitor through the contact hole is performed.

In the above-described embodiment of the present invention, an example of forming the metal oxide layer 16A by oxidizing the hard mask 16 during the heat treatment process for recovering ferroelectric layer characteristics is described. It may be formed according to the same process.

That is, the metal oxide film 16A may be formed by oxidizing the hard mask 16 by performing plasma treatment using O ₂ and N ₂ O gas before or after etching the upper electrode film 15. In addition, the metal oxide film 16A may be formed by oxidizing the hard mask 16 by performing O ₃ treatment before or after etching the upper electrode film 15. The metal heat treatment in an oxygen atmosphere containing at least one of O ₂ , N ₂ O, N ₂ , O ₃ , Ar, He, Ne, or Kr before or after etching the upper electrode layer 15. The metal oxide film 16A may be formed by performing a thermal process to oxidize the hard mask 16.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention made as described above effectively oxidizes the hard mask used as an etch mask when forming the upper electrode pattern and uses it as an adhesive layer between the upper electrode and the interlayer insulating film, thereby effectively preventing the cleaning solution from seeping into the interface between the upper electrode and the interlayer insulating film in the wet process. can do. Accordingly, the lifting of the membrane can be effectively suppressed, and a cleaning liquid with a stronger cleaning power can be used. As a result, a decrease in contact resistance can be expected.

Claims (9)

In the semiconductor memory device manufacturing method, Forming a capacitor including a lower electrode film, a dielectric film, and an upper electrode film stacked on the semiconductor substrate, wherein a hard mask, which is an etching mask for patterning the upper electrode film, is oxidized to form a metal oxide film used as an adhesive layer; A second step of forming an interlayer insulating film on the entire structure in which the first step is completed, and contacting a part of the interlayer insulating film with the metal oxide film; And Selectively etching the interlayer dielectric layer and the metal oxide layer to form a contact hole exposing the upper electrode on a bottom surface thereof and exposing the interlayer dielectric layer and the metal oxide layer on sidewalls thereof; Semiconductor memory device manufacturing method comprising a. The method of claim 1, After the third step, And a fourth step of performing a wet cleaning process. The method of claim 2, The hard mask, A method of manufacturing a semiconductor memory device, characterized in that it is formed of TiN, TaN or WN. The method according to any one of claims 1 to 3, The first step, Stacking a lower electrode film, a ferroelectric material, and an upper electrode film stacked on the semiconductor substrate, and forming a hard mask on the upper electrode film; Etching the upper electrode layer using the hard mask as an etching mask; And Patterning the ferroelectric film and the lower electrode film; And the metal oxide film is formed by oxidizing the hard mask while performing the ferroelectric film characteristic recovery heat treatment. The method according to any one of claims 1 to 3, The first step, Stacking a lower electrode layer, a dielectric layer, and an upper electrode layer stacked on the semiconductor substrate, and forming a hard mask on the upper electrode layer; Etching the upper electrode layer using the hard mask as an etching mask; And And patterning the dielectric layer and the lower electrode layer. The method of claim 5, After the fifth or sixth step, And an eighth step of forming the metal oxide layer by performing the hard mask oxidation process. The method of claim 6, In the eighth step, A method of manufacturing a semiconductor memory device, characterized in that the metal oxide film is formed by subjecting the hard mask to plasma treatment using O ₂ and N ₂ O gases. The method of claim 6, In the eighth step, The metal oxide film is formed by performing an O ₃ process to oxidize the hard mask. The method of claim 6, In the eighth step, By performing a metal thermal treatment process in an oxygen atmosphere containing at least one of O ₂ , N ₂ O, N ₂ , O ₃ , Ar, He, Ne or Kr to oxidize the hard mask. And forming the metal oxide film.