KR20020002828A - Structure of 2-port sram cell - Google Patents

Abstract

PURPOSE: A structure of two port SRAM is provided to achieve a reduction in chip area by decreasing a number of transistors used and thereby to reduce load and improve operating speed. CONSTITUTION: Two port SRAM includes a write unit(100) and a read unit(200), each having four transistors. The write unit(100) has the first active transistor(N9) switching a write bit line(WBLT) and the first storage node(Nd5) when a write word line(WWL) is enabled, the first inverter composed of PMOS and NMOS transistors(P4,N11) and inverting a signal of the first storage node(Nd5), and a PMOS transistor(P3) supplying Vcc to the first storage node(Nd5) when output signal of the inverter is low. The read unit(200) has the second inverter composed of PMOS and NMOS transistors(P5,N12) and inverting a signal of the first storage node(Nd5), an NMOS transistor(N13) switching a voltage of the first storage node(Nd5) to Vss when a signal of the second storage node(Nd7), and the second active transistor(N10) sending a signal of the second storage node(Nd7) to a read bit line(RBLT) when a read word line(RWL) is enabled.

Description

2-port SRAM cell structure {STRUCTURE OF 2-PORT SRAM CELL}

The present invention relates to a two-port SRAM cell structure. In particular, the two-port SRAM cell structure is reduced to eight by using 10 conventional transistors, thereby reducing the cell area. The present invention relates to a two-port SRAM cell structure that can reduce chip area and thereby reduce loading load, thereby improving operation speed.

1 is a circuit diagram of a two-port SRAM cell according to the prior art, and is composed of a write operation unit 10 and a read operation unit 20.

As shown, the write operation unit 10 includes a first active transistor N1 having a gate connected to the write word line WWL and connected between the write bit line WBLT and the first storage node Nd1. A second active transistor N2 connected to the write word line WWL and connected between the write bit line bar WBLTB and the second storage node Nd2, and the second storage node Nd2; The PMOS transistor P1 switches the power supply voltage Vcc to the first storage node Nd1 by a voltage of V2, and the power supply voltage Vcc is controlled by the voltage of the first storage node Nd1. PMOS transistor P2 for switching to node Nd2 and NMOS transistor N3 for switching the voltage of first storage node Nd1 to ground voltage Vss by the voltage of second storage node Nd2. And the first storage node Nd1. The NMOS transistor N4 switches the voltage of the second storage node Nd2 to the ground voltage Vss by a voltage.

The read operation unit 20 is connected to the NMOS transistor N5 and the read word line RWL which switch between the read bit line RBLT and the third storage node Nd3 by a read word line RWL. The voltage of the third storage node Nd3 is controlled by the voltage of the NMOS transistor N6 and the second storage node Nd2 that switches between the read bit line bar RBLTB and the fourth storage node Nd4. NMOS transistor N7 for switching to ground voltage Vss and NMOS transistor N8 for switching the voltage of fourth storage node Nd4 to ground voltage Vss by the voltage of first storage node Nd1. It is composed of

First, in order to read the data of the cell, precharge the read bit line (RBIT, RBITB) voltage to the power supply voltage (Vcc), and then increase the read word lines (RBLT, RBLTB) to the power supply voltage (Vcc). Transistors N5 and N6 are turned on. Thereafter, the NMOS transistors N7 and N8 operate according to the data states of the first storage node Nd1 and the second storage node Nd2 to change the data states of the read bit line RBLT and the read bit line bar RBLTB. Decide

If the first storage node Nd1 is 'high' data, the NMOS transistor N8 is turned on to make the potential of the read bit line bar RBLTB the ground voltage Vss. At this time, since the NMOS transistor N7 is turned off in the read bit line RBLT, 'high' data stored in the third storage node Nd3 is transferred to the read bit line RBLT through the NMOS transistor N5. .

Therefore, the read bit line RBIT is the power supply voltage Vcc, and the read bit line bar RBLTB is the ground voltage Vss, and the sense amplifier operates according to these two voltage differences.

In the write mode, when the write bit line WBLT is the power supply voltage Vcc and the write bit line bar WBLTB (or BIT) is the ground voltage Vss, the write word line WWL is grounded. The active transistors N1 and N2 are turned on from the voltage Vss to the power supply voltage Vcc to thereby turn on the active transistors N1 and N2, thereby storing data contained in the write bit line WBLT and the write bit line bar WBLTB. The data is stored in the nodes Nd1 and Nd2, respectively.

As shown in the drawing, a conventional two-port SRAM cell has a structure in which a write address and a read address exist differently so that writing and reading can be performed simultaneously.

The conventional two-port SRAM cell is composed of two parts of the write operation unit 10 and the read operation unit 20, and one cell is composed of ten transistors more than a conventional cell composed of six transistors. As a result, the increase of the cell area increases the area of the chip, and also increases the operation speed due to the increase in the load.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to reduce the chip area by reducing the cell area by configuring the two-port SRAM cell using eight transistors to eight. This reduces the loading load to provide a two-port SRAM cell structure that can improve the operating speed.

In order to achieve the above object, the two-port SRAM cell structure of the present invention,

A first active transistor for switching the write bit line and the first storage node when the write word line is activated, a first inverter inputting a signal of the first storage node and outputting an inverted signal, and a first inverter Write operation means comprising a PMOS transistor for supplying a power supply voltage to the first storage node by an output signal;

A second inverter for inputting a signal of the first storage node and outputting an inverted signal to a second storage node, and an NMOS transistor for switching a voltage of the first storage node to a ground voltage by a signal of the second storage node; And a read operation means composed of a second active transistor which emits a signal of the second storage node to a read bit line when the read word line is activated.

In the two-port SRAM cell structure of the present invention, the first and second active transistors are NMOS transistors.

In the two-port SRAM cell structure of the present invention, the first and second inverters are configured by PMOS transistors and NMOS transistors, respectively.

In order to achieve the above object, another two-port SRAM cell structure of the present invention,

A first write active transistor for switching the write bit line and the first storage node when the write word line is activated,

A second write active transistor for switching a write bit line bar and a second storage node when the write word line is activated;

A first PMOS transistor configured to switch a power supply voltage to the first storage node by a voltage of the second storage node;

A second PMOS transistor configured to switch a power supply voltage to the second storage node by a voltage of the first storage node;

A first NMOS transistor for switching a voltage of the first storage node to a ground voltage by a voltage of the second storage node;

A second NMOS transistor for switching a voltage of the second storage node to a ground voltage by a voltage of the first storage node;

A first lead active transistor for switching a read bit line and the first storage node when a read word line is activated;

And a second lead active transistor configured to switch a write bit line bar and a second storage node when the read word line is activated.

In the two-port SRAM cell structure of the present invention, the first and second write active transistors are NMOS transistors.

In the two-port SRAM cell structure of the present invention, the first and second lead active transistors are NMOS transistors.

1 is a circuit diagram of a conventional two port SRAM cell

2 is a circuit diagram of a two port SRAM cell according to the present invention.

3 is an operation timing diagram showing a simulation result of FIG.

4 is a circuit diagram of a two port SRAM cell according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10, 100: light operation unit 20, 200: lead operation unit

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.

2 is a circuit diagram of a two-port SRAM cell according to the present invention, and includes a write operation unit 100 and a read operation unit 200 each composed of four transistors.

The write operation unit 100 includes an active transistor N9 for switching the write bit line WRLT and the first storage node Nd5 when the write word line WWL is activated, and the first storage node Nd5. A first inverter including a PMOS transistor (P4) and an NMOS transistor (N11) for inputting an inverted signal and outputting an inverted signal, and the first storage node when the output signals of the inverters (P4 and N11) are 'low'. Nd5) and a PMOS transistor P3 for supplying a power supply voltage Vcc.

The read operation unit 200 includes a PMOS transistor P5 and an NMOS transistor N12 that input a signal of the first storage node Nd5 and output an inverted signal to the second storage node Nd7. NMOS transistor N13 for switching the voltage of the first storage node Nd5 to the ground voltage Vss when the signals of the second inverters P5 and N12 and the second storage node Nd7 are 'high'. And an active transistor N10 which outputs a signal of the second storage node Nd7 to the read bit line RBLT when the read word line RWL is activated.

The operation by the above configuration will be described with reference to the operation timing shown in FIG.

First, when the write bit line WBLT data is 'high', the first storage node Nd5 is 'high' and the outputs of the first inverters P4 and N11 are 'low' to input the PMOS transistor P3. Is applied to maintain the 'high' data of the first storage node (Nd5). In this case, the second storage node Nd7 maintains 'low' data by the NMOS transistors N12 of the second inverters P5 and N12.

When the write bit line WBIT data is 'low', the first storage node Nd5 is in a 'low' state, and since the signals passed through the second inverters P5 and N12 are 'high', the NMOS transistor N13 is turned off. When turned on, the first storage node Nd5 keeps the 'low' data.

Meanwhile, when the read word line RWL is enabled, data of the second storage node Nd7 is loaded on the read bit line RBIT to perform normal operation.

The 2-port SRAM cell of the present invention differs from the conventional 2-bit line write and read operations in that it operates 1 write and read bit lines.

4 is a circuit diagram of a two port SRAM cell according to another embodiment of the present invention.

As shown, an active transistor N14 that switches the write bit line WRLT and the first storage node Nd8 when the write word line WWL is activated, and the write word line WWL is activated. An active transistor N15 for switching the write bit line bar WBLTB and the second storage node Nd9, and a power supply voltage Vcc is applied to the first storage node Nd8 by the voltage of the second storage node Nd9. PMOS transistor (P6) for switching to the second, PMOS transistor (P7) for switching the power supply voltage (Vcc) to the second storage node (Nd9) by the voltage of the first storage node (Nd8), and the second The NMOS transistor N18 switches the voltage of the first storage node Nd8 to the ground voltage Vss by the voltage of the storage node Nd9 and the second by the voltage of the first storage node Nd8. Before Storage Node (Nd9) NMOS transistor N19 for switching voltage to ground voltage Vss, and active transistor N16 for switching read bit line RBLT and first storage node Nd8 when read word line WWL is activated. And an active transistor N17 for switching the write bit line bar RBLTB and the second storage node Nd9 when the read word line RWL is activated.

Referring to the operation by the above configuration, in order to read the data of the cell, after precharging the read bit line (RBIT, RBITB) voltage to the power supply voltage (Vcc), the read word line (RWL) is supplied to the power supply voltage (Vcc). ), The access transistors N16 and N17 are turned on. Thereafter, the NMOS transistors N18 and N19 operate according to the data states of the first storage node Nd8 and the second storage node Nd9 to change the data states of the read bit line RBLT and the read bit line bar RBLTB. Decide

If the first storage node Nd8 is 'high' data, the NMOS transistor N19 is turned on to make the potential of the read bit line bar RBLTB the ground voltage Vss.

Therefore, the read bit line RBIT is the power supply voltage Vcc, and the read bit line bar RBLTB is the ground voltage Vss, and the sense amplifier operates according to these two voltage differences.

In the write mode, assuming that the write bit line WBLT is the power supply voltage Vcc and the write bit line bar WBLTB is the ground voltage Vss, the write word line WWL is connected to the ground voltage Vss. By turning on the active transistors N14 and N15 by activating the power supply voltage Vcc at, the data contained in the write bit line WBLT and the write bit line bar WBLTB is stored in the first and second storage nodes Nd8, Nd9).

As described above, according to the two-port SRAM cell structure according to the present invention, unlike the conventional configuration by operating from 10 transistors to 8 transistors to reduce the area of the cell chip This results in a reduction in area, an increase in net die, and a reduction in the area of the chip, resulting in a reduction in loading RC on the chip, thereby reducing the loading load during write and read cycles to speed up operation.

In addition, by using one lead bit line, the bit line cross coupling effect occurring in the existing two bit lines is reduced, thereby reducing noise characteristics.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (6)

In a semiconductor memory device, A first active transistor for switching the write bit line and the first storage node when the write word line is activated, a first inverter inputting a signal of the first storage node and outputting an inverted signal, and a first inverter Write operation means comprising a PMOS transistor for supplying a power supply voltage to the first storage node by an output signal; A second inverter for inputting a signal of the first storage node and outputting an inverted signal to a second storage node, and an NMOS transistor for switching a voltage of the first storage node to a ground voltage by a signal of the second storage node; And read operation means composed of a second active transistor which outputs a signal of the second storage node to a read bit line when a read word line is activated. The method of claim 1, And said first and second active transistors are NMOS transistors. The method of claim 1, And said first and second inverters each comprise a PMOS transistor and an NMOS transistor. In a semiconductor memory device, A first write active transistor for switching the write bit line and the first storage node when the write word line is activated, A second write active transistor for switching a write bit line bar and a second storage node when the write word line is activated; A first PMOS transistor configured to switch a power supply voltage to the first storage node by a voltage of the second storage node; A second PMOS transistor configured to switch a power supply voltage to the second storage node by a voltage of the first storage node; A first NMOS transistor for switching a voltage of the first storage node to a ground voltage by a voltage of the second storage node; A second NMOS transistor for switching a voltage of the second storage node to a ground voltage by a voltage of the first storage node; A first lead active transistor for switching a read bit line and the first storage node when a read word line is activated; And a second lead active transistor for switching a write bit line bar and a second storage node when the read word line is activated. The method of claim 4, wherein And said first and second write active transistors are NMOS transistors. The method of claim 4, wherein And the first and second lead active transistors are NMOS transistors.