KR20020002809A - Method of fabricating triple-well enabling to adjust characteristics individually in semiconductor device - Google Patents
Method of fabricating triple-well enabling to adjust characteristics individually in semiconductor device Download PDFInfo
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- KR20020002809A KR20020002809A KR1020000037120A KR20000037120A KR20020002809A KR 20020002809 A KR20020002809 A KR 20020002809A KR 1020000037120 A KR1020000037120 A KR 1020000037120A KR 20000037120 A KR20000037120 A KR 20000037120A KR 20020002809 A KR20020002809 A KR 20020002809A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 39
- 238000005468 ion implantation Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims description 16
- 239000005368 silicate glass Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 230000002093 peripheral effect Effects 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 description 5
- 230000001105 regulatory effect Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 230000005465 channeling Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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Abstract
Description
본 발명은 삼중-웰 구조의 반도체소자에 관한 것으로, 보다 구체적으로는 삼중-웰(WELL) 구조 반도체소자에 포함되는 페리(PERI)-PMOS 및 NMOS, 셀(CELL)-NMOS의 동작전압 조절을 위한 이온주입공정을 실시함에 있어서, 별도의 마스크 공정없이 독립적으로 웰 형성 및 농도조절이 가능하게 한, 독립적 특성조절이 가능한 반도체소자의 삼중-웰 형성방법에 관한 것이다.The present invention relates to a semiconductor device having a triple-well structure, and more particularly, to control operating voltages of PERI-PMOS and NMOS and CELL-NMOS included in a triple-well semiconductor device. In performing the ion implantation process, it relates to a triple-well formation method of a semiconductor device capable of independently adjusting characteristics, which enables the well formation and concentration control independently without a separate mask process.
삼중-웰(Triple WELL) 구조는 주회로인 셀영역과 주변회로에 포함되는 MOSFET(Metal Oxide Semiconductor FET ; 이하 'MOS'라 함)의 웰(WELL), 일예로 셀영역에 포함된 웰과 주변회로에 포함된 같은 형(TYPE)의 웰을 구분하기 위한 구조이다. 이러한 구조는 반도체소자의 보다 정확한 동작을 위해 도입된 것이다. 그리고 일반적으로 삼중-웰 구조의 반도체소자는 NMOS(페리-NMOS) 및 PMOS(페리-PMOS)를 포함하고 있으며, 이러한 NMOS 또는 PMOS안에 셀(Cell)을 위한 또다른 MOS(셀-MOS)를 포함하고 있다.Triple-Well structure is a well (WELL) of the MOSFET (Metal Oxide Semiconductor FET; hereinafter referred to as a "MOS") included in the cell region and the peripheral circuit of the main circuit, the well and the surrounding in the cell region, for example It is a structure to distinguish wells of the same type included in the circuit. This structure is introduced for more accurate operation of the semiconductor device. In general, a semiconductor device having a triple-well structure includes an NMOS (ferry-NMOS) and a PMOS (ferry-PMOS), and in the NMOS or PMOS, another MOS (cell-MOS) for a cell is included. Doing.
종래의 삼중-웰 반도체소자는, 동작전압(Vt; Threshold Voltage, 이하 'Vt'라 함)을 조절하기 위하여 N채널 Vt 마스크 공정 후, 셀-NMOS 및 페리-NMOS의 Vt를 조절하는 이온주입을 각각 실시하여 각 Vt의 농도를 조절한다. 이후 P채널 Vt 마스크 공정후, 페리-PMOS와 셀-NMOS의 Vt를 조절하기 위해서, 2단계 이상의 감광막과 이온주입 공정을 실시한다. 이러한 공정에 의한 종래의 반도체소자는 페리-PMOS, 페리-NMOS, 셀-NMOS의 Vt가 서로 유기적인 관계에 있다.The conventional triple-well semiconductor device, after the N-channel Vt mask process to control the operating voltage (Vt; Threshold Voltage, referred to as 'Vt'), the ion implantation to adjust the Vt of the cell-NMOS and Perry-NMOS. Each is carried out to adjust the concentration of each Vt. After the P-channel Vt mask process, in order to control the Vt of the Peri-PMOS and the cell-NMOS, two or more steps of photoresist and ion implantation are performed. In the conventional semiconductor device by this process, Vt of Peri-PMOS, Peri-NMOS, and Cell-NMOS has an organic relationship with each other.
이러한 종래 삼중-웰 반도체소자는 셀영역의 P-웰과, 이 셀을 제외한 주변회로의 P-웰의 웰 농도를 다르게 할 수 있으므로, 소자 제작을 위한 기판이 다르고 동작특성도 다른 독립된 MOSFET를 제작하는 특징이 있다.Since the conventional triple-well semiconductor device can vary the well concentration of the P-well of the cell region and the P-well of the peripheral circuit except this cell, an independent MOSFET having a different substrate and different operating characteristics for fabrication of the device is fabricated. There is a characteristic.
그러나, 전술한 종래 삼중-웰 구조의 반도체소자는 소자제작에 있어서 많은문제점들을 가지고 있다. 즉 각 MOSFET의 전기적 특성을 독립적으로 형성시키기 위해서는, 각각의 MOSFET 특성에 해당하는 웰 영역과 동작전압을 얻기 위한 별도의 Vt 농도조절 공정이 추가되어야 하는 문제점이 있다. 또한, 종래 삼중-웰 반도체소자의 제작공정은 페리-PMOS, 페리-NMOS, 셀-NMOS의 농도조절을 위한 공정이 상호 영향을 미치는 문제가 있다. 이 때문에, 페리-PMOS의 농도조절을 위한 이온주입은 셀-NMOS Vt 농도에 영향을 주게 된다. 따라서, 각 MOSFET의 동작전압을 독립적으로 조절할 수 없으며, 이를 해결하기 위해서는 별도의 감광막 및 마스크 공정 등이 추가되어야 하는 문제점이 있다.However, the conventional triple-well structured semiconductor device described above has many problems in device fabrication. That is, in order to independently form the electrical characteristics of each MOSFET, there is a problem in that a separate Vt concentration control process for obtaining a well region and an operating voltage corresponding to each MOSFET characteristic must be added. In addition, the manufacturing process of the conventional triple-well semiconductor device has a problem that the process for the concentration control of Peri-PMOS, Peri-NMOS, cell-NMOS affects each other. For this reason, ion implantation for the concentration control of Peri-PMOS affects the cell-NMOS Vt concentration. Therefore, the operating voltage of each MOSFET cannot be adjusted independently. In order to solve this problem, a separate photoresist film and a mask process need to be added.
따라서 전술한 문제점을 해결하기 위한 본 발명의 목적은, 페리-PMOS, 페리-NMOS, 셀-NMOS의 Vt 조절 이온주입공정을 실시함에 있어서, 별도의 마스크 공정이 필요하지 않도록 산화막을 선별적으로 이용하여 이온주입 등의 공정을 실시함으로써, 각 MOSFST의 전기적 특성을 독립적으로 조절할 수 있는, 독립적 특성조절이 가능한 반도체소자의 삼중-웰 형성방법을 제공하는 데 있다.Accordingly, an object of the present invention for solving the above problems is to selectively use an oxide film so as not to require a separate mask process in performing the Vt-controlled ion implantation process of Peri-PMOS, Peri-NMOS, and Cell-NMOS. By performing a process such as ion implantation, to provide a triple-well formation method of a semiconductor device capable of independently controlling the characteristics, which can independently control the electrical characteristics of each MOSFST.
도 1 내지 도 5는 본 발명의 일실시예에 따른, 반도체소자의 삼중-웰 형성방법에 따른 제작공정을 설명하기 위한 도면.1 to 5 are views for explaining a manufacturing process according to the triple-well forming method of a semiconductor device, according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
101 : 기판 102 : 필드산화막101: substrate 102: field oxide film
103 : 증착산화막 104 : 희생산화막103: deposited oxide film 104: sacrificial oxide film
105, 107 : N-웰 마스크 106 : N-웰 영역105, 107: N-well mask 106: N-well region
108 : P-웰 마스크 109 : P-웰 영역108: P-well mask 109: P-well area
110 : R-웰 영역110: R-well area
본 발명에 따른 독립적 특성조절이 가능한 반도체소자의 삼중-웰 형성방법은, 삼중-웰 반도체 소자의 제작에 있어서,The triple-well formation method of a semiconductor device capable of controlling independent characteristics according to the present invention, in the manufacture of a triple-well semiconductor device,
상기 삼중-웰 반도체소자를 위한 기판 상부에, 소정 영역으로 분리하기 위한 필드산화막을 형성하는 제1단계; 상기 형성된 필드산화막을 중심으로 상기 기판 상부에 제1 및 제2산화막으로 각각 구분하여 선별적으로 이용하기 위한 산화막을 형성하는 제2단계; 상기 제1산화막 하부의 소정영역에 이온주입하여 제1형-웰 영역을형성하는 제3단계; 상기 제1산화막을 제거하는 제4단계; 상기 제3단계에서 형성된 제1형-웰 영역 내부에 셀형-웰이 포함되도록 형성하기 위해, 상기 셀형-웰 영역을 제외한 상기 제1형-웰 영역의 이온농도를 변화시키는 제5단계; 상기 제2산화막의 특성을 고려하여 상기 셀형-웰 영역에 이온주입하는 제6단계; 상기 제2형-웰 영역 상부의 제2산화막을 제거하는 제7단계; 및, 상기 셀형-웰 영역 및 상기 제거된 제2산화막 하부에 제2형-웰 영역에 이온주입하여, 서로 다른 특성을 갖도록 조절된 제2형-웰 및 셀형-웰을 형성하는 제8단계를 포함한다.A first step of forming a field oxide film on the substrate for the triple-well semiconductor device to be separated into a predetermined region; A second step of forming an oxide film for selectively using each of the first and second oxide films on the substrate, based on the formed field oxide film; A third step of forming a first type well region by ion implantation into a predetermined region under the first oxide layer; A fourth step of removing the first oxide film; A fifth step of changing an ion concentration of the first type-well region excluding the cell-well region to form a cell-well within the first type-well region formed in the third step; A sixth step of implanting ions into the cell-well region in consideration of characteristics of the second oxide film; A seventh step of removing the second oxide film over the second type-well region; And an eighth step of implanting ions in a second type well region under the cell-well region and the removed second oxide layer to form second type wells and cell type wells adjusted to have different characteristics. Include.
이하 도면들을 참조하여 본 발명의 바람직한 실시예를 자세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 5는 본 발명의 일실시예에 따른, 반도체소자의 삼중-웰 형성방법에 따른 제작공정을 설명하기 위한 도면들이다.1 to 5 are diagrams for explaining a manufacturing process according to a triple-well forming method of a semiconductor device according to an embodiment of the present invention.
도 1에 도시한 바와 같이, 본 실시예에 따른 본 발명은 기판(101)상부에 필드산화막(102, Field OXide ; FOX)을 형성하고, 그 상부에 산화막(103, 104)을 증착한다. 이 산화막(103, 104)은 향후 진행되는 제작공정에서 선별적으로 이용되므로, 필드산화막(102)을 중심으로 증착산화막(103)과 희생산화막(104)으로 구분하여 설명한다. 또한 후술하겠지만, 증착산화막(103)의 하부에는 N-웰 영역과 셀영역이 형성되고, 희생산화막(104)의 하부에는 P-웰 영역이 형성된다. 그리고 이 두 산화막(103, 104)은 USG(Undoped Silicate Glass)나 PSG(Phosphrous Silicate Glass) 모두 가능하다. 또한 이 두 산화막(103, 104)은, 이후 진행되는 제작공정에서 채널링현상(channeling effect)을 방지할 뿐만 아니라, Vt 조절 이온주입시 선택적 이온장벽 산화막으로 작용하게 된다.As shown in FIG. 1, the present invention according to the present embodiment forms a field oxide film 102 (FOX) on the substrate 101 and deposits oxide films 103 and 104 thereon. Since the oxide films 103 and 104 are selectively used in production processes going on in the future, the oxide films 103 and 104 will be described by dividing them into the deposition oxide film 103 and the sacrificial oxide film 104 around the field oxide film 102. In addition, as will be described later, an N-well region and a cell region are formed under the deposition oxide film 103, and a P-well region is formed under the sacrificial oxide film 104. The two oxide films 103 and 104 may be made of both USG (Undoped Silicate Glass) and PSG (Phosphrous Silicate Glass). In addition, the two oxide films 103 and 104 not only prevent channeling effects in subsequent manufacturing processes, but also act as selective ion barrier oxide films during Vt-regulated ion implantation.
이 후 도 2에 도시한 바와 같이, 희생산화막(104)의 상부에 첫 번째 형태의 N-웰 마스크(105)를 형성한다. 그리고 이 제1형의 N-웰 마스크(105)를 통해 인(P)을 이온주입하여 N-웰 영역(106)을 깊게 형성한다. N-웰 영역(106) 내부에는 셀-영역을 위한 P-웰이 형성되어야 하므로 일반적인 웰보다 깊게 형성한다. 이러한 이온 주입시 증착산화막(103)은 이온주입에 의한 고에너지의 영향으로 피폭결함이 발생하고, 주입되는 인(P)이온에 의해 인-도핑 증착산화막(Phosphorus Silicate Glass ; PSG)화 된다.Thereafter, as shown in FIG. 2, an N-well mask 105 of the first type is formed on the sacrificial oxide film 104. Phosphorus (P) is ion implanted through the N-well mask 105 of the first type to form the N-well region 106 deeply. Since the P-well for the cell-region has to be formed inside the N-well region 106, it is formed deeper than a general well. During the ion implantation, the deposition oxide film 103 is exposed to defects under the influence of high energy by ion implantation, and the phosphorus-doped deposition oxide film (Phosphorus Silicate Glass; PSG) is implanted by the implanted phosphorus (P) ion.
이 후 도 3과 같이, 감광막 제거공정에 의하여, 페리-NMOS 형성영역인 P-웰 상부의 희생산화막(104)만 남기고, N-웰 영역 상부의 증착산화막(103)은 제거한다. 그 다음 제2형의 N-웰 마스크(107)를 통한 이온주입을 실시한다. 이때의 이온주입은 셀-NMOS를 위한 R-웰 영역(도 4, 110)을 제외하고, 순수한 N-웰만의 웰형성과 P-채널 Vt 조절을 위한 농도조절을 동시에 실시하기 위한 것이다. 후술하겠지만 이 R-웰 영역(도 4, 110)은 실제 P형-웰로서 P-웰 영역(도 4, 109)와 구분하기 위해 R-웰로 명명한 것이다.Thereafter, as shown in FIG. 3, only the sacrificial oxide film 104 in the upper portion of the P-well, which is the ferry-NMOS formation region, is left, and the deposition oxide film 103 in the upper portion of the N-well region is removed by the photoresist removal process. Then, ion implantation is performed through the N-well mask 107 of the second type. In this case, except for the R-well region (FIGS. 4 and 110) for the cell-NMOS, the ion implantation is performed to simultaneously perform well-formation of pure N-well and concentration control for P-channel Vt control. As will be described later, these R-well regions (FIGS. 4 and 110) are actually named P-wells as R-wells to distinguish them from P-well regions (FIGS. 4 and 109).
이 후 도 4와 같이, 제2형 N-웰 마스크(107) 제거한다. 그리고 순수한 N-웰 영역(106)만을 차단하는 P-웰 마스크(108)를 형성한다. 이 공정은 P-웰 영역(109)과, 셀-NMOS를 위한 R-웰 영역(110)을 형성하기 위한 것일 뿐만 아니라, 셀-NMOS 동작전압을 조절하기 위한 1차 셀/페리 Vt 조절 이온주입을 위한 것이다. 이때 P-웰 영역(109)은 희생산화막(104)에 차단되어 셀-NMOS가 형성되는 R-웰 영역(110)에만 이온이 주입된다. 즉, P-웰 영역(109)과 R-웰 영역(110)은 동일한 P-웰마스크(108)에 의해 영향을 받지만, 셀-NMOS의 R-웰 영역(110)에만 이온이 주입되므로, 셀-NMOS와 페리-NMOS의 Vt 도핑농도를 선택적으로 조절할 수 있다.Thereafter, as shown in FIG. 4, the second type N-well mask 107 is removed. And forming a P-well mask 108 that blocks only the pure N-well region 106. This process is not only for forming the P-well region 109 and the R-well region 110 for the cell-NMOS, but also the primary cell / ferry Vt-regulated ion implantation for regulating the cell-NMOS operating voltage. It is for. At this time, the P-well region 109 is blocked by the sacrificial oxide film 104 and ions are implanted only in the R-well region 110 in which the cell-NMOS is formed. That is, the P-well region 109 and the R-well region 110 are affected by the same P-well mask 108, but since ions are implanted only in the R-well region 110 of the cell-NMOS, You can selectively adjust the Vt doping concentrations for NMOS and Perry-NMOS.
이 후 도 5에 도시한 바와 같이, 에칭(etching)을 실시하여 P-웰 영역(109) 상부의 희생산화막(104)을 제거한다. 본 실시예에서는 기존 감광막보다 두꺼운 약 2.5 ㎛이상의 감광막을 사용하기 때문에 Vt 조절 이온주입 에너지인 50 KeV이하 에너지에 대한 장벽 역할에는 문제가 없다. 이후 셀/페리 NMOS Vt 농도 조절을 위한 2차 셀/페리 NMOS Vt 조절 이온주입을 실시한다. 이 때 P-웰 영역(109)상부의 희생산화막을 제거하였으므로, 셀-NMOS를 위한 R-웰 영역(110)과, 페리-NMOS를 위한 P-웰 영역(109) 모두에 이온이 주입된다. 아울러, 셀-NMOS와 페리-NMOS의 Vt 농도조절을 위한 나머지 잔류이온을 추가적으로 주입함으로써, 셀-NMOS 및 페리-NMOS의 Vt 농도를 각각 독립적으로 조절할 수 있다.Thereafter, as shown in FIG. 5, etching is performed to remove the sacrificial oxide film 104 on the P-well region 109. In the present embodiment, since the photosensitive film of about 2.5 μm or more thicker than the conventional photosensitive film is used, there is no problem in the role of a barrier to energy of 50 KeV or less, which is the Vt-regulated ion implantation energy. Subsequently, secondary cell / ferry NMOS Vt control ion implantation is performed to control the cell / ferry NMOS Vt concentration. At this time, since the sacrificial oxide film on the P-well region 109 is removed, ions are implanted into both the R-well region 110 for the cell-NMOS and the P-well region 109 for the Peri-NMOS. In addition, by additionally injecting the remaining residual ions for the Vt concentration control of the cell-NMOS and Perry-NMOS, the Vt concentration of the cell-NMOS and Perry-NMOS can be independently controlled.
따라서 전술한 공정들에 의해 본 발명은 추가적인 마스크공정 및 관련공정없이 삼중-웰 구조에 포함되는 셀-NMOS, 페리-NMOS, 페리-PMOS의 웰 및 Vt의 농도를 각각 독립적으로 조절함으로써 각 MOSFET의 전기적 특성을 조절할 수 있다. 아울러 본 발명에 의한 반도체소자의 삼중-웰 형성방법은 타입이 다른, 예를 들어 n형과 p형이 서로 바뀌는 형태의 삼중-웰 구조에도 적용할 수 있다.Therefore, by the above-described processes, the present invention can independently control the concentrations of the wells and Vt of the cell-NMOS, peri-NMOS, and peri-PMOS included in the triple-well structure without additional masking and related processes. Electrical characteristics can be adjusted. In addition, the triple-well formation method of the semiconductor device according to the present invention may be applied to a triple-well structure having a different type, for example, an n-type and a p-type.
전술한 바와 같이, 본 발명에 따른 반도체소자의 삼중-웰 형성방법은, 별도의 마스크 및 관련공정을 추가하지 않고도 동작전압과 관련되는 웰 농도를 독립적으로 조절함으로써, 반도체 소자의 전기적 특성을 개선하는 효과가 있다.As described above, the triple-well formation method of the semiconductor device according to the present invention improves the electrical characteristics of the semiconductor device by independently adjusting the well concentration associated with the operating voltage without adding a separate mask and related processes. It works.
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