KR20020002735A - Method for forming a gate electrode of a semiconductor device - Google Patents
Method for forming a gate electrode of a semiconductor device Download PDFInfo
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- KR20020002735A KR20020002735A KR1020000037021A KR20000037021A KR20020002735A KR 20020002735 A KR20020002735 A KR 20020002735A KR 1020000037021 A KR1020000037021 A KR 1020000037021A KR 20000037021 A KR20000037021 A KR 20000037021A KR 20020002735 A KR20020002735 A KR 20020002735A
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 42
- 239000010937 tungsten Substances 0.000 claims abstract description 42
- 230000004888 barrier function Effects 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 229910008807 WSiN Inorganic materials 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000003647 oxidation Effects 0.000 claims abstract description 9
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000006243 chemical reaction Methods 0.000 claims description 14
- 239000007789 gas Substances 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 239000012495 reaction gas Substances 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 24
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910008938 W—Si Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000010406 interfacial reaction Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 게이트 전극 형성 방법에 관한 것으로, 특히, 폴리실리콘층과 금속층의 사이에 베리어층(Barrier Layer)이 형성된 구조를 갖는 금속 게이트 전극 형성 방법에 관한 것이다.The present invention relates to a method for forming a gate electrode of a semiconductor device, and more particularly, to a method for forming a metal gate electrode having a structure in which a barrier layer is formed between a polysilicon layer and a metal layer.
일반적으로 반도체 소자가 고집적화됨에 따라 패턴의 크기 및 패턴간의 간격이 미세화되고, 이에 따라 전극 또는 배선의 자체저항이 증가된다. 예를들어, 게이트 전극의 폭이 0.13㎛ 이하로 감소되면 4μΩ/㎠ 이하의 저항값을 유지해야 한다.In general, as the semiconductor device is highly integrated, the size of the pattern and the spacing between the patterns become smaller, thereby increasing the resistance of the electrode or the wiring. For example, if the width of the gate electrode is reduced to 0.13 mu m or less, the resistance value of 4 mu m / cm 2 or less should be maintained.
그래서 전극 또는 배선의 자체저항을 감소시킬 수 있는 새로운 물질을 이용하는 공정기술이 개발중인데, 그러면 금속을 이용한 종래 반도체 소자의 게이트 전극 형성 방법을 설명하면 다음과 같다.Therefore, a process technology using a new material that can reduce the self-resistance of an electrode or a wiring is being developed. Then, a method of forming a gate electrode of a conventional semiconductor device using metal will be described.
도 1a 및 도 1b는 종래 반도체 소자의 게이트 전극 형성 방법을 설명하기 위한 소자의 단면도이다.1A and 1B are cross-sectional views of a device for explaining a gate electrode forming method of a conventional semiconductor device.
도 1a는 게이트 절연막(2)이 형성된 반도체 기판(1)상에 폴리실리콘층(3) 및 결정성 베리어층(4)을 순차적으로 형성한 후 상기 결정성 베리어층(4)상에 텅스텐층(5)을 형성한 상태의 단면도로서, 상기 결정성 베리어층(4)은 게이트 전극의 비저항을 감소시키기 위한 목적으로 형성되며, WN, TiN, Si3N4와 같은 금속-질화막(Metal-Nitride)계의 결정성 막으로 형성된다.FIG. 1A illustrates that a polysilicon layer 3 and a crystalline barrier layer 4 are sequentially formed on a semiconductor substrate 1 on which a gate insulating film 2 is formed, and then a tungsten layer is formed on the crystalline barrier layer 4. 5) is a cross-sectional view of the crystalline barrier layer (4) is formed for the purpose of reducing the resistivity of the gate electrode, and metal-nitride film (Metal-Nitride) such as WN, TiN, Si 3 N 4 It is formed by the crystalline film of the system.
도 1b는 상기 폴리실리콘층(3)과 텅스텐층(5)이 계면 결합을 이루도록 열처리한 상태의 단면도인데, 상기 텅스텐층(5)과 결정성 베리어층(4)의 계면 부위에만 텅스텐 반응층(4a)이 형성된다.1B is a cross-sectional view of a state in which the polysilicon layer 3 and the tungsten layer 5 are heat treated to form an interfacial bond, and a tungsten reaction layer (only at an interface portion of the tungsten layer 5 and the crystalline barrier layer 4) 4a) is formed.
상기 결정성 베리어층(4)을 이루는 WN, TiN, Si3N4는 원자간의 결합(Bonding)이 매우 안정된 상태로 유지된다. 그러므로 계면에서의 반응이 어려워 상기 결정성 베리어층(4)의 상부만 텅스텐(W)과 결합을 이루게 된다. 즉, 상기 결정성 베리어층(4)이 Si3N4로 형성된 경우 상기 텅스텐층(5)과 결정성 베리어층(4)의 계면 부위에만 WSiN의 3원계가 형성되고, 하부는 Si3N4상태가 그대로 유지된다. 이러한 현상은 하기 반응식 1을 통해 열역학적으로 설명되듯이, Si3N4가 매우 안정된 결합을 이루고 있어 N과 Si의 분해가 쉽게 일어나지 않기 때문에 발생된다. 그러므로 3원계 반응에 의한 베리어층이 형성되도록 하기 위해서는 고온의 열처리가 필요하다.WN, TiN, and Si 3 N 4 forming the crystalline barrier layer 4 are maintained in a very stable state of bonding between atoms. Therefore, since the reaction at the interface is difficult, only the upper portion of the crystalline barrier layer 4 forms a bond with tungsten (W). That is, when the crystalline barrier layer 4 is formed of Si 3 N 4 , a ternary system of WSiN is formed only at an interface between the tungsten layer 5 and the crystalline barrier layer 4, and the lower portion of Si 3 N 4 is formed. The state remains the same. This phenomenon occurs because Si 3 N 4 has a very stable bond, and thus, decomposition of N and Si does not occur easily, as described thermodynamically through Scheme 1 below. Therefore, in order to form a barrier layer by ternary reaction, high temperature heat treatment is required.
따라서 상기 텅스텐층(5)과 결정성 베리어층(4)의 계면 부위에만 WSiN이 형성되는 경우 잔류된 Si3N4가 절연막으로 작용하여 캐패시턴스(Capacitance)가 증가되고, 이에 따라 게이트 전극의 전기적 특성이 열화된다.Therefore, when WSiN is formed only at the interface between the tungsten layer 5 and the crystalline barrier layer 4, the remaining Si 3 N 4 acts as an insulating film, thereby increasing capacitance and thus the electrical characteristics of the gate electrode. This is deteriorated.
한편, 상기 결정성 베리어층(4)을 WN으로 형성하면 내열성이 불충분한 WN가 후속 열처리 과정에서 부분적으로 실리사이드화(Silicidation)되기 때문에 패턴 형성을 위한 후속 식각 과정에서 과도 식각되어 게이트 산화막에 영향을 미치게 된다.On the other hand, when the crystalline barrier layer 4 is formed of WN, since WN having insufficient heat resistance partially silicides in a subsequent heat treatment process, it is excessively etched in a subsequent etching process for pattern formation, thereby affecting the gate oxide layer. Go crazy.
또한, 상기와 같이 결정성 베리어층(4)상에 텅스텐(W)이 증착되는 경우 텅스텐(W)의 성장에 영향을 미쳐 텅스텐(W)의 그레인(Grain) 크기가 도 3a에 도시된 바와 같이 감소되기 때문에 전극의 자체저항이 증가된다.In addition, when tungsten (W) is deposited on the crystalline barrier layer (4) as described above, the growth of tungsten (W) affects the grain size of tungsten (W) as shown in FIG. 3A. Because of the decrease, the self-resistance of the electrode is increased.
따라서 본 발명은 질소(N)의 함유량이 낮고 실리콘(Si)의 함유량이 높은 비결정성의 실리콘 리치 SiN막을 폴리실리콘층과 텅스텐층의 사이에 형성하고 후속 산화 과정에서 텅스텐(W)과의 반응에 의해 실리콘 리치 SiN막이 WSiN막으로 변화되도록 하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 게이트 전극 형성 방법을 제공하는 데 그 목적이 있다.Therefore, the present invention forms an amorphous silicon rich SiN film having a low content of nitrogen (N) and a high content of silicon (Si) between a polysilicon layer and a tungsten layer and reacting with tungsten (W) in a subsequent oxidation process. It is an object of the present invention to provide a method for forming a gate electrode of a semiconductor device which can solve the above disadvantages by causing the silicon rich SiN film to be changed to a WSiN film.
도 1a 및 도 1b는 종래 반도체 소자의 게이트 전극 형성 방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a gate electrode forming method of a conventional semiconductor device.
도 2a 및 도 2b는 본 발명에 따른 반도체 소자의 게이트 전극 형성 방법을 설명하기 위한 소자의 단면도.2A and 2B are cross-sectional views of a device for explaining a method of forming a gate electrode of a semiconductor device according to the present invention.
도 3a 및 도 3b는 텅스텐층의 결정 구조를 도시한 평면도.3A and 3B are plan views showing the crystal structure of the tungsten layer.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1 및 11: 반도체 기판 2 및 12: 게이트 절연막1 and 11: semiconductor substrates 2 and 12: gate insulating film
3 및 13: 폴리실리콘층 4: 결정성 베리어층3 and 13: polysilicon layer 4: crystalline barrier layer
4a 및 14a: 텅스텐 반응층 5 및 15: 텅스텐층4a and 14a: tungsten reaction layer 5 and 15: tungsten layer
14: 비결정성 베리어층14: amorphous barrier layer
본 발명에 따른 반도체 소자의 게이트 전극 형성 방법은 게이트 절연막이 형성된 반도체 기판상에 폴리실리콘층 및 비결정성 베리어층을 순차적으로 형성한 후 비결정성 베리어층상에 텅스텐층을 형성하는 단계와, 텅스텐층, 비결정성 베리어층, 폴리실리콘층 및 게이트 절연막을 순차적으로 패터닝한 후 반도체 기판 및 폴리실리콘층의 노출된 표면에 산화막이 성장되도록 하는 동시에 텅스텐과의 반응에 의해 비결정성 베리어층이 텅스텐 반응층으로 변화되도록 산화 공정을 실시하는 단계로 이루어진다.The method of forming a gate electrode of a semiconductor device according to the present invention includes the steps of sequentially forming a polysilicon layer and an amorphous barrier layer on a semiconductor substrate on which a gate insulating film is formed, and then forming a tungsten layer on the amorphous barrier layer, a tungsten layer, After the amorphous barrier layer, the polysilicon layer, and the gate insulating film are sequentially patterned, an oxide film is grown on the exposed surfaces of the semiconductor substrate and the polysilicon layer, and the amorphous barrier layer is changed into a tungsten reaction layer by reaction with tungsten. Performing an oxidation process if possible.
상기 비결정성 베리어층은 실리콘 리치 SiN막이며, 상기 텅스텐 반응층은WSiN막이다.The amorphous barrier layer is a silicon rich SiN film, and the tungsten reaction layer is a WSiN film.
종래에는 3 원계의 베리어층(WSiN)을 형성하기 위하여 하부의 폴리실리콘층으로부터 실리콘(Si)을 공급받고, WN 또는 Si3N4막으로부터 N을 공급받아 상부의 텅스텐(W)과의 반응에 의해 베리어층이 형성되도록 하였는데, 이때의 반응 에너지는 하기의 식 2 및 식 3과 같이 계산된다. 참고로, WN의 반응은 열역학적인 데이터가 없기 때문에 텅스텐(W)과 유사한 Mo를 반응에 이용하였다.Conventionally, silicon (Si) is supplied from a lower polysilicon layer to form a ternary barrier layer (WSiN), and N is supplied from a WN or Si 3 N 4 film to react with tungsten (W) at the top. The barrier layer was formed, and the reaction energy at this time is calculated as in Equations 2 and 3 below. For reference, since the reaction of WN has no thermodynamic data, tungsten (W) -like Mo was used for the reaction.
상기의 식 2 및 식 3을 통해 W-N, W-Si는 매우 높은 반응성을 갖고 있음을 알 수 있다.Equations 2 and 3 it can be seen that W-N, W-Si has a very high reactivity.
따라서 본 발명은 상기와 같은 원리를 이용하여 실리콘 리치(Silicon Rich) SiN(이하, SRSiN이라 함.)를 베리어층으로 이용한다.Therefore, the present invention uses silicon rich SiN (hereinafter referred to as SRSiN) as a barrier layer using the above principle.
그러면 이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Next, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 및 도 2b는 본 발명에 따른 반도체 소자의 게이트 전극 형성 방법을 설명하기 위한 소자의 단면도이다.2A and 2B are cross-sectional views of devices for explaining a gate electrode forming method of a semiconductor device according to the present invention.
도 2a는 게이트 절연막(12)이 형성된 반도체 기판(11)상에 폴리실리콘층(13)및 비결정성 베리어층(14)을 순차적으로 형성한 후 상기 비결정성 베리어층(14)상에 텅스텐층(15)을 형성한 상태의 단면도로서, 상기 비결정성 베리어층(14)은 게이트 전극의 비저항을 감소시키기 위한 목적으로 형성하며, PECVD 또는 LPCVD 방식으로 실리콘(Si)의 함유량이 10% 이하인 실리콘 리치 SiN막을 수십 Å의 두께로 증착하여 형성한다.FIG. 2A illustrates that a polysilicon layer 13 and an amorphous barrier layer 14 are sequentially formed on a semiconductor substrate 11 on which a gate insulating layer 12 is formed, and then a tungsten layer is formed on the amorphous barrier layer 14. 15) is a cross-sectional view of the amorphous barrier layer 14 formed for the purpose of reducing the resistivity of the gate electrode, silicon-rich SiN having a silicon (Si) content of 10% or less by PECVD or LPCVD method The film is formed by depositing a thickness of tens of micrometers.
상기 SRSiN를 PECVD 방식으로 증착하는 경우 0.01 내지 10Torr의 압력 조건에서 플라즈마 생성을 위해 13.56MHz 또는 100 내지 1MHz의 고주파 또는 2.54GHz의 초고주파 전력을 0 내지 5000와트(W) 공급하되, 양 전극간의 거리가 100 내지 900mils 정도 되도록 한다. 그리고 반응 기체(~ 50sccm의 NH3및 ~ 100sccm의 SiH4)와 분위기 기체(~ 4000sccm의 N2및 ~ 4000sccm의 Ar) 의 혼합비를 조절하며, 반도체 기판의 온도를 100 내지 500℃로 유지시킨다. 이때, 상기 분위기 기체대신 Ne, He 등과 같은 불활성 기체를 단일 또는 혼합하여 사용할 수 있으며, 이때 공급량은 0 내지 10000sccm이 되도록 한다.When the SRSiN is deposited by PECVD, a high frequency power of 13.56 MHz or 100 to 1 MHz or ultra high frequency power of 2.54 GHz is supplied at 0 to 5000 watts (W) for plasma generation under a pressure condition of 0.01 to 10 Torr, but the distance between the two electrodes 100 to 900 mils. The mixing ratio of the reaction gas (NH 3 of ˜50 sccm and SiH 4 of ˜100 sccm) and the atmosphere gas (N 2 of ˜4000 sccm and Ar of ˜4000 sccm) is controlled, and the temperature of the semiconductor substrate is maintained at 100 to 500 ° C. In this case, an inert gas such as Ne, He or the like may be used instead of the atmosphere gas or may be used in combination, and the supply amount may be 0 to 10000 sccm.
또한, 상기 SRSiN를 LPCVD 방식으로 증착하는 경우 800℃ 이하의 온도 및 수 Torr의 압력 조건에서 ~ 100slm의 N2, ~ 1000slm의 NH3, ~100slm의 SiH2Cl2가 혼합된 기체를 이용한다.In addition, when the SRSiN is deposited by LPCVD, a mixture of ~ 100 slm of N 2 , ~ 1000 slm of NH 3 , and ~ 100 slm of SiH 2 Cl 2 is used at a temperature of 800 ° C. or below and a pressure of several Torr.
도 2b는 상기 텅스텐층(15), 비결정성 베리어층(14), 폴리실리콘층(13) 및 게이트 절연막(12)을 순차적으로 패터닝한 후 500 내지 1000℃의 온도에서 선택적 산화 공정을 실시하여 상기 반도체 기판(11), 게이트 절연막(12) 및폴리실리콘층(13)의 노출된 표면에 산화막(16)이 성장되도록 한 상태의 단면도로서, 상기 산화 과정에서 상기 텅스텐(15)층과 비결정성 베리어층(14)의 계면 반응에 의해 상기 비결정성 베리어층(14)이 텅스텐 반응층(14a) 즉, WSiN막으로 변화된다. 이때, 비결정성의 실리콘 리치 SiN막은 텅스텐과 쉽게 반응된다.FIG. 2B illustrates a step of sequentially patterning the tungsten layer 15, the amorphous barrier layer 14, the polysilicon layer 13, and the gate insulating layer 12, and then performing a selective oxidation process at a temperature of 500 to 1000 ° C. A cross-sectional view of the oxide film 16 being grown on the exposed surfaces of the semiconductor substrate 11, the gate insulating film 12 and the polysilicon layer 13, wherein the tungsten 15 layer and the amorphous barrier in the oxidation process By the interfacial reaction of the layer 14, the amorphous barrier layer 14 is changed into a tungsten reaction layer 14a, that is, a WSiN film. At this time, the amorphous silicon rich SiN film easily reacts with tungsten.
상기한 바와 같이 본 발명은 질소(N)의 함유량이 낮고 실리콘(Si)의 함유량이 높은 비결정성의 실리콘 리치 SiN막을 폴리실리콘층과 텅스텐층의 사이에 형성한다. 그리고 후속 산화 과정에서 텅스텐(W)과의 반응에 의해 실리콘 리치 SiN막이 WSiN막으로 변화되도록 한다.As described above, the present invention forms an amorphous silicon rich SiN film having a low content of nitrogen (N) and a high content of silicon (Si) between the polysilicon layer and the tungsten layer. In the subsequent oxidation process, the silicon rich SiN film is changed into a WSiN film by reaction with tungsten (W).
그러므로 WSiN막의 생성에 의해 폴리실리콘층과의 계면 접착력이 향상되며, 텅스텐층의 실리사이드화가 방지되고, 게이트 전극의 비저항이 감소된다. 그리고 상기와 같은 비결절성의 박막(실리콘 리치 SiN막)상에 텅스텐(W)이 증착되기 때문에 도 3b에 도시된 바와 같이 그레인의 크기가 증가되며, 이에 따라 텅스텐층의 자체저항이 감소된다.Therefore, the generation of the WSiN film improves the interfacial adhesion with the polysilicon layer, prevents silicideization of the tungsten layer, and reduces the resistivity of the gate electrode. And since the tungsten (W) is deposited on the non-nodal thin film (silicon rich SiN film) as described above, the grain size is increased as shown in Figure 3b, thereby reducing the self-resistance of the tungsten layer.
따라서 본 발명을 이용하면 신뢰성이 우수한 고집적 및 고속의 반도체 소자 제조가 가능해진다.Therefore, the use of the present invention enables the fabrication of highly integrated and high speed semiconductor devices with excellent reliability.
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