KR20020002734A - Test pattern for measuring a contact resistance and a method for manufacturing the same - Google Patents
Test pattern for measuring a contact resistance and a method for manufacturing the same Download PDFInfo
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- KR20020002734A KR20020002734A KR1020000037020A KR20000037020A KR20020002734A KR 20020002734 A KR20020002734 A KR 20020002734A KR 1020000037020 A KR1020000037020 A KR 1020000037020A KR 20000037020 A KR20000037020 A KR 20000037020A KR 20020002734 A KR20020002734 A KR 20020002734A
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- active region
- contact resistance
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000000926 separation method Methods 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 abstract 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 2
- 239000002019 doping agent Substances 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 238000005259 measurement Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
본 발명은 콘택저항 측정용 테스트 패턴 및 그의 제조 방법에 관한 것으로,특히, 활성영역과 살리사이드(Salicide)층의 콘택저항을 측정하기 위한 체인 형태의 콘택저항 측정용 테스트 패턴 및 그의 제조 방법에 관한 것이다.The present invention relates to a test pattern for measuring contact resistance and a method of manufacturing the same, and more particularly, to a test pattern for measuring contact resistance in a chain form for measuring contact resistance between an active region and a salicide layer and a method for manufacturing the same. will be.
일반적으로 반도체 소자는 여러 단계의 공정을 통해 제조된다. 각 단계의 공정은 제품 생산이 가능하도록 개발 단계에서 미리 테스트되는데, 이중 활성영역과 전도성 배선의 콘택저항을 측정하는 과정이 포함된다.In general, semiconductor devices are manufactured through a multi-step process. Each stage of the process is pre-tested during the development phase to enable product production, including measuring the contact resistance of the double active region and the conductive wiring.
종래에는 활성영역과 전도성 배선의 콘택저항을 측정하기 위하여 도 1에 도시된 바와 같이 체인 형태의 테스트 패턴을 형성한다.Conventionally, a test pattern in the form of a chain is formed as shown in FIG. 1 to measure the contact resistance of the active region and the conductive wiring.
반도체 기판(1)에 형성된 각 활성영역(2)은 소자분리막(3)에 의해 전기적으로 분리되며, 각 활성영역(2)의 양측 콘택부(4)에는 각각 전도성 배선(5)이 연결된다. 이때, 인접하는 두개의 활성영역(2)이 하나의 전도성 배선(5)으로 연결된다. 즉, 하나의 소자분리막(3) 양측에 형성된 활성영역(2)이 하나의 전도성 배선(5)에 의해 서로 연결된다.Each active region 2 formed on the semiconductor substrate 1 is electrically separated by an isolation layer 3, and conductive wires 5 are connected to both contact portions 4 of each active region 2. In this case, two adjacent active regions 2 are connected to one conductive wire 5. That is, the active regions 2 formed at both sides of one device isolation film 3 are connected to each other by one conductive wire 5.
그러면 상기와 같이 체인 형태로 이루어진 테스트 패턴을 이용하여 활성영역(2)과 전도성 배선(5)의 콘택저항을 측정하는 방법을 설명하면 다음과 같다.Next, a method of measuring the contact resistance of the active region 2 and the conductive wiring 5 using the test pattern formed in a chain form as described above will be described.
먼저, 상기 테스트 패턴의 양측 종단부에 각각 형성된 패드(6a 및 6b)를 통해 일정 전압을 인가하여 상기 전도성 배선(5), 콘택부(4) 및 활성영역(2)을 통해 전류가 흐르도록 한 후 전류의 량과 전압을 측정한다. 그리고 이를 이용하여 활성영역(2)과 전도성 배선(5)의 콘택저항을 산출한다.First, a constant voltage is applied through pads 6a and 6b formed at both ends of the test pattern, respectively, so that current flows through the conductive wiring 5, the contact portion 4, and the active region 2. After that, measure the amount of current and voltage. The contact resistance of the active region 2 and the conductive wiring 5 is calculated using the same.
그런데 도 2에 도시된 바와 같이 콘택저항을 감소시키기 위해 살리사이드 공정을 채택한 경우, 즉 반도체 기판(11)에 형성된 소자분리막(13)에 의해 전기적으로 분리되는 각 활성영역(12)의 표면부에 살리사이드층(14)이 형성되고, 상기 살리사이드층(14)의 양측부에 콘택부(16)가 형성된 경우에는 각 패드(17a및 17b)에 일정 전압을 인가하면 전도성 배선(15), 콘택부(16) 및 살리사이드층(14)을 통해 전류가 흐르기 때문에 상기 전도성 배선(15)과 살리사이드층(14)의 콘택저항만 측정되고, 활성영역(12)과 전도성 배선(15)의 콘택저항은 측정할 수 없게 된다.However, as shown in FIG. 2, when the salicide process is adopted to reduce contact resistance, that is, the surface portion of each active region 12 electrically separated by the device isolation film 13 formed on the semiconductor substrate 11. When the salicide layer 14 is formed and the contact portions 16 are formed at both sides of the salicide layer 14, a predetermined voltage is applied to each of the pads 17a and 17b to form the conductive wiring 15 and the contact. Since current flows through the portion 16 and the salicide layer 14, only the contact resistance of the conductive wiring 15 and the salicide layer 14 is measured, and the contact between the active region 12 and the conductive wiring 15 is measured. Resistance will not be measurable.
그러므로 살리사이드 공정을 채택한 경우 활성영역과 전도성 배선의 콘택저항을 측정할 수 있는 새로운 형태의 테스트 패턴이 필요하다.Therefore, the salicide process requires a new type of test pattern that can measure the contact resistance of the active region and the conductive wiring.
따라서 본 발명은 분리패턴을 이용하여 활성영역의 양측부를 노출시킨 후 노출된 활성영역의 표면부에 살리사이드층을 형성하고 각 살리사이드층이 직렬로 연결되도록 체인 형태의 전도성 배선을 형성하므로써 상기한 단점을 해소할 수 있는 콘택저항 측정용 테스트 패턴 및 그의 제조 방법을 제공하는 데 그 목적이 있다.Therefore, the present invention is formed by exposing both sides of the active region using a separation pattern, and then forming a salicide layer on the exposed surface of the active region and forming a chain-shaped conductive wiring such that each salicide layer is connected in series. It is an object of the present invention to provide a test pattern for measuring contact resistance and a method of manufacturing the same that can solve the disadvantages.
도 1 및 도 2는 종래의 콘택저항 측정용 테스트 패턴을 설명하기 위한 단면도.1 and 2 are cross-sectional views for explaining a conventional test pattern for contact resistance measurement.
도 3a 내지 도 3d는 본 발명에 따른 콘택저항 측정용 테스트 패턴 제조 방법을 설명하기 위한 단면도.3A to 3D are cross-sectional views illustrating a method for manufacturing a test pattern for measuring contact resistance according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1, 11 및 21: 반도체 기판 2, 12 및 22: 활성영역1, 11 and 21: semiconductor substrates 2, 12 and 22: active region
3, 13 및 23: 소자분리막 4, 16: 콘택부3, 13, and 23: device isolation layers 4 and 16: contact portions
5, 15 및 26: 전도성 배선 6a, 6b, 17a, 17b, 27a 및 27b: 패드5, 15, and 26: conductive wirings 6a, 6b, 17a, 17b, 27a, and 27b: pads
14 및 25: 살리사이드층 24: 분리패턴14 and 25: salicide layer 24: separation pattern
본 발명에 따른 콘택저항 측정용 테스트 패턴은 반도체 기판에 형성되며 소자분리막에 의해 전기적으로 분리되는 다수의 활성영역과, 각 활성영역 양측의 표면부에 각각 형성되며 분리패턴에 의해 소정거리 이격되는 살리사이드층과, 인접하는 두개의 살리사이드층에 연결된 전도성 패턴과, 양측 종단부의 전도성 패턴에 각각 형성된 패드를 포함하여 이루어진다.The test pattern for measuring contact resistance according to the present invention is formed on a semiconductor substrate and is formed on a plurality of active regions electrically separated by a device isolation film, and is formed on the surface portions of both sides of each active region and is spaced apart by a predetermined distance by a separation pattern. And a pad formed on the side layer, a conductive pattern connected to two adjacent salicide layers, and a conductive pattern on both ends.
또한, 본 발명에 따른 콘택저항 측정용 테스트 패턴 제조 방법은 소자분리막이 형성된 반도체 기판에 불순물 이온을 주입하여 활성영역을 형성하는 단계와, 활성영역의 양측부가 노출되도록 반도체 기판상에 분리패턴을 각각 형성하는 단계와, 금속을 증착한 후 열처리하여 활성영역의 노출된 표면부에 살리사이드층이 형성되도록 하는 단계와, 반응하지 않고 잔류된 금속을 제거한 후 살리사이드층이 직렬로 연결되도록 체인 형태의 전도성 배선을 형성하는 단계를 포함하여 이루어진다.In addition, the method for manufacturing a test pattern for contact resistance measurement according to the present invention comprises the steps of forming an active region by implanting impurity ions into the semiconductor substrate on which the device isolation film is formed, and separating the separation pattern on the semiconductor substrate to expose both sides of the active region Forming a metal layer, depositing a metal, and performing a heat treatment to form a salicide layer on an exposed surface of the active region; and removing a metal remaining without reaction and forming a chain form so that the salicide layer is connected in series. Forming a conductive wiring.
상기 분리패턴은 산화막 또는 질화막으로 이루어지며, 양측 종단부의 상기 전도성 배선에 패드가 각각 형성된다.The separation pattern may be formed of an oxide film or a nitride film, and pads may be formed on the conductive lines at both ends.
그러면 이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Next, the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3d는 본 발명에 따른 콘택저항 측정용 테스트 패턴 제조 방법을 설명하기 위한 소자의 단면도이다.3A to 3D are cross-sectional views of devices for explaining a method of manufacturing a test pattern for measuring contact resistance according to the present invention.
도 3a는 소자분리막(23)이 형성된 반도체 기판(21)에 불순물 이온을 주입하여 활성영역(22)을 형성한 상태의 단면도로서, 이때 상기 활성영역(22)을 엘리베이티드(Elevated) 구조로 형성할 수 있다.FIG. 3A is a cross-sectional view of the active region 22 formed by implanting impurity ions into the semiconductor substrate 21 on which the device isolation layer 23 is formed, wherein the active region 22 is formed in an elevated structure. can do.
도 3b는 상기 활성영역(22)의 양측부가 일부 노출되도록 상기 반도체 기판(21)상에 분리패턴(24)을 각각 형성한 상태의 단면도로서, 상기 분리패턴(24)은 산화막 또는 질화막으로 형성된다.3B is a cross-sectional view of the isolation patterns 24 formed on the semiconductor substrate 21 to partially expose both sides of the active region 22. The separation patterns 24 are formed of an oxide film or a nitride film. .
도 3c는 Ti, Co 등과 같은 금속을 증착하고 열처리하여 상기 활성영역(22)의노출된 표면부에 살리사이드층(25)이 형성되도록 한 상태의 단면도로서, 상기 분리패턴(24) 양측부의 노출된 활성영역(22)의 표면부에 살리사이드층(25)이 형성된 상태가 도시된다.FIG. 3C is a cross-sectional view of a salicide layer 25 being formed on the exposed surface of the active region 22 by depositing and thermally treating a metal such as Ti or Co, and exposing both sides of the separation pattern 24. The salicide layer 25 is formed in the surface part of the active region 22 which is shown.
도 3d는 상기 금속이 제거될 수 있는 식각제를 사용하여 반응하지 않고 잔류된 금속을 제거한 후 상기 살리사이드층(25)이 직렬로 연결될 수 있도록 체인 형태의 전도성 배선(26)을 형성한 상태의 단면도로서, 이때, 상기 전도성 배선(26)은 다음과 같이 형성된다.FIG. 3D illustrates a state in which a conductive wire 26 in a chain form is formed so that the salicide layer 25 may be connected in series after removing the remaining metal without reacting using an etchant capable of removing the metal. As a cross-sectional view, the conductive wiring 26 is formed as follows.
상기 반도체 기판(21)상에 절연막(도시않됨)을 형성한 후 상기 살리사이드층(25)이 노출되도록 상기 절연막에 콘택홀을 형성하고 상기 콘택홀내에 전도성 물질로 플러그를 형성한다. 그리고 상기 절연막상에 전도성층을 형성한 후 패터닝하여 상기 플러그가 연결되도록 전도성 배선(26)을 형성한다.After forming an insulating film (not shown) on the semiconductor substrate 21, a contact hole is formed in the insulating film to expose the salicide layer 25, and a plug is formed of a conductive material in the contact hole. In addition, a conductive layer is formed on the insulating layer and then patterned to form a conductive line 26 to connect the plug.
상기와 같이 이루어진 테스트 패턴을 이용하는 경우 상기 활성영역(22)과 전도성 배선(26)의 콘택저항을 측정하기 위하여 양측 종단부의 상기 전도성 배선(26)에 각각 형성된 패드(27a 및 27b)에 일정 전압을 인가하여 상기 전도성 배선(26), 살리사이드층(25) 및 활성영역(22)을 통해 전류가 흐르도록 한 후 전류의 량과 전압을 측정한다. 그리고 이를 이용하여 활성영역(22)과 전도성 배선(26)의 콘택저항을 산출한다.In the case of using the test pattern as described above, in order to measure the contact resistance of the active region 22 and the conductive wiring 26, a predetermined voltage is applied to the pads 27a and 27b formed on the conductive wiring 26 at both ends. The current is allowed to flow through the conductive wiring 26, the salicide layer 25, and the active region 22, and then the amount and voltage of the current are measured. The contact resistance of the active region 22 and the conductive wiring 26 is calculated using the same.
상술한 바와 같이 본 발명은 종래의 테스트 패턴으로 측정할 수 없었던 살리사이드 공정을 적용한 소자의 활성영역과 전도성 배선의 콘택저항을 용이하게 측정할 수 있도록 한다. 이를 위해 본 발명은 각 활성영역의 양측부가 소정 부분 노출되도록 분리패턴을 형성한 후 살리사이드 공정을 진행하여 노출된 활성영역 양측부에 살리사이드층이 형성되도록 하고 상기 살리사이드층이 직렬로 연결되도록 체인 형태의 전도성 배선을 형성한다. 그러므로 본 발명은 콘택저항을 감소시키기 위해 살리사이드 공정을 채택하는 차세대 반도체 소자의 개발 단계에서 신뢰성있는 콘택저항의 측정이 이루어지도록 하므로써 소자의 구조 및 콘택 형성 방법에 따른 콘택저항 데이터를 지속적으로 피드백(Feed Back)할 수 있도록 하며, 이로 인해 소자의 수율 향상 및 개발 기간의 단축 등 많은 효과가 기대된다.As described above, the present invention makes it possible to easily measure the contact resistance of the active region and the conductive wiring of the device to which the salicide process is applied, which could not be measured by the conventional test pattern. To this end, the present invention forms a separation pattern so that both sides of each active region are exposed to a predetermined portion, and then a salicide process is performed to form salicide layers on both sides of the exposed active region, and the salicide layers are connected in series. To form a conductive wiring in the form of a chain. Therefore, the present invention provides continuous feedback of contact resistance data according to the structure of the device and the method of forming a contact by allowing the reliable contact resistance to be measured at the development stage of the next-generation semiconductor device employing the salicide process to reduce the contact resistance. Feed Back), which is expected to have many effects, such as improved device yield and shorter development period.
Claims (8)
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| KR1020000037020A KR20020002734A (en) | 2000-06-30 | 2000-06-30 | Test pattern for measuring a contact resistance and a method for manufacturing the same |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101035592B1 (en) * | 2003-07-22 | 2011-05-19 | 매그나칩 반도체 유한회사 | Semiconductor device comprising interconnection part for contact holes and another interconnection part for viaholes aligned on the same line |
| KR101035594B1 (en) * | 2003-07-22 | 2011-05-19 | 매그나칩 반도체 유한회사 | Integrated semiconductor device comprising interconnection part for contact holes and another interconnection part for via holes aligned vertically each other |
| US20220077008A1 (en) * | 2020-09-04 | 2022-03-10 | Changxin Memory Technologies, Inc. | Semiconductor device and method for manufacturing same |
-
2000
- 2000-06-30 KR KR1020000037020A patent/KR20020002734A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101035592B1 (en) * | 2003-07-22 | 2011-05-19 | 매그나칩 반도체 유한회사 | Semiconductor device comprising interconnection part for contact holes and another interconnection part for viaholes aligned on the same line |
| KR101035594B1 (en) * | 2003-07-22 | 2011-05-19 | 매그나칩 반도체 유한회사 | Integrated semiconductor device comprising interconnection part for contact holes and another interconnection part for via holes aligned vertically each other |
| US20220077008A1 (en) * | 2020-09-04 | 2022-03-10 | Changxin Memory Technologies, Inc. | Semiconductor device and method for manufacturing same |
| US11961774B2 (en) * | 2020-09-04 | 2024-04-16 | Changxin Memory Technologies, Inc. | Semiconductor device and method for manufacturing same |
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