KR20020002631A - A method for forming a word line of a semiconductor device - Google Patents
A method for forming a word line of a semiconductor device Download PDFInfo
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- KR20020002631A KR20020002631A KR1020000036857A KR20000036857A KR20020002631A KR 20020002631 A KR20020002631 A KR 20020002631A KR 1020000036857 A KR1020000036857 A KR 1020000036857A KR 20000036857 A KR20000036857 A KR 20000036857A KR 20020002631 A KR20020002631 A KR 20020002631A
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- South Korea
- Prior art keywords
- hard mask
- mask layer
- word line
- wordline
- film
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 239000010409 thin film Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 27
- 238000005530 etching Methods 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체소자의 워드라인 형성방법에 관한 것으로, 특히 금속 게이트전극 형성 공정후 실시되는 식각공정시 하드마스크층이 경사식각되는 현상을 방지하기 위한 기술에 관한 것이다.The present invention relates to a method of forming a word line of a semiconductor device, and more particularly, to a technique for preventing the hard mask layer from being inclined etched during an etching process performed after a metal gate electrode forming process.
워드라인 형성공정은, 라인 크기가 축소됨에 따라 감광막 두께의 감소는 피할 수 없는 현상이다.In the word line forming process, as the line size is reduced, the decrease in the thickness of the photoresist film is inevitable.
따라서, 종래와 같이 감광막을 이용하여 하드마스크층을 식각하기 위해서는하드마스크층의 두께를 낮추어야 하거나, 감광막에 대한 선택비가 우수한 장비의 개발이 필수적이다.Therefore, in order to etch the hard mask layer using the photosensitive film as in the prior art, it is necessary to reduce the thickness of the hard mask layer or to develop a device having excellent selectivity to the photosensitive film.
그러나, 하드마스크층의 두께를 낮추는 문제는 후속공정인 자기정렬적인 콘택공정시 마진을 확보하기 어렵기 때문에 불가능하다.However, the problem of lowering the thickness of the hard mask layer is impossible because it is difficult to secure a margin in a subsequent self-aligned contact process.
또한, 금속을 워드라인 재료로 사용함에 따라 워드라인 재료에 대한 하드마스크의 선택비는 더욱 떨어지기 때문에 하드마스크의 두께를 더욱 크게 가져 가야할 필요성까지 대두되고 있다.In addition, as the metal is used as the word line material, the selection ratio of the hard mask to the word line material is further lowered, thereby increasing the necessity of bringing the thickness of the hard mask to be larger.
이러한 문제를 해결하기 위하여 폴리실리콘등의 재료등을 하드마스크층 상부에 사용하여 하드마스크층의 식각 장벽으로 사용하고자 하는 시도가 있으나 이는 폴리실리콘의 측면식각 특성이 강하여 경사식각 프로파일이 형성되며 선택비 측면에서도 우수하지 않아 공정의 신뢰성을 저하시키는 문제점이 있다.In order to solve this problem, there is an attempt to use a material such as polysilicon on the hard mask layer as an etch barrier of the hard mask layer, but this has a strong side etching characteristic of polysilicon to form an inclined etch profile. There is also a problem in that it is not excellent in terms of lowering the reliability of the process.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 워드라인의 하드마스크층인 질화막의 식각공정시 산화막을 식각장벽층으로 사용하며 상기 산화막의 식각장벽층으로 감광막을 사용하여 실시함으로써 낮은 감광막을 이용하여 워드라인을 형성할 수 있도록 하는 반도체소자의 워드라인 형성방법을 제공하는데 그 목적이 있다.In order to solve the problems of the prior art described above, a low photosensitive film is formed by using an oxide film as an etch barrier layer during the etching process of a nitride film, which is a hard mask layer of a word line, and using a photosensitive film as an etch barrier layer of the oxide film. It is an object of the present invention to provide a word line forming method of a semiconductor device capable of forming word lines using the same.
도 1a 내지 도 1d 는 본 발명의 실시예에 따른 반도체소자의 워드라인 형성방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a word line forming method of a semiconductor device in accordance with an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11 : 반도체기판 13 : 텅스텐막, 워드라인 물질11: semiconductor substrate 13: tungsten film, word line material
15 : 제1하드마스크층 17 : 제2하드마스크층15: first hard mask layer 17: second hard mask layer
19 : 감광막패턴19: photosensitive film pattern
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 워드라인 형성방법은,In order to achieve the above object, the word line forming method of the semiconductor device according to the present invention,
반도체기판에 워드라인용 금속박막을 증착하는 공정과,Depositing a metal thin film for a word line on a semiconductor substrate;
상기 워드라인용 금속박막 상부에 제1하드마스크층과 제2하드마스크층의 적층구조를 형성하되, 상기 제1하드마스크층과 제2하드마스크층은 식각선택비 차이를 갖는 서로 다른 절연막으로 형성되는 공정과,A stack structure of a first hard mask layer and a second hard mask layer is formed on the word line metal thin film, and the first hard mask layer and the second hard mask layer are formed of different insulating layers having different etching selectivity. Process and
상기 제2하드마스크층 상부에 워드라인 마스크를 이용하여 감광막패턴을 형성하는 공정과,Forming a photoresist pattern on the second hard mask layer using a word line mask;
상기 감광막패턴을 마스크로 하여 상기 제2하드마스크층과 제1하드마스크층을 순차적으로 패터닝하는 공정과,Patterning the second hard mask layer and the first hard mask layer sequentially using the photoresist pattern as a mask;
상기 패터닝된 제2하드마스크층과 제1하드마스크층을 마스크로하여 상기 워드라인용 금속박막을 패터닝하는 공정과,Patterning the metal thin film for the word line using the patterned second hard mask layer and the first hard mask layer as a mask;
상기 제1,2하드마스크층을 남은 부분을 제거하여 워드라인을 형성하는 공정을 포함하는 것을 특징으로한다.And removing the remaining portions of the first and second hard mask layers to form a word line.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d 는 본 발명의 실시예에 따른 반도체소자의 워드라인 형성방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a word line forming method of a semiconductor device in accordance with an embodiment of the present invention.
먼저, 반도체기판(11) 상부에 활성영역을 정의하는 소자분리막(도시안됨)을 형성한다.First, an isolation layer (not shown) defining an active region is formed on the semiconductor substrate 11.
그리고, 상기 반도체기판(11) 상부에 워드라인용 텅스텐막(13)을 증착한다.A tungsten film 13 for word line is deposited on the semiconductor substrate 11.
그리고, 상기 텅스텐막(13) 상부에 제1하드마스크층(15)과 제2하드마스크층(17) 적층구조를 형성한다.A first hard mask layer 15 and a second hard mask layer 17 are stacked on the tungsten film 13.
이때, 상기 제1하드마스크층(15)과 제2하드마스크층(17)은 식각선택비 차이를 갖는 서로 다른 절연물질로 형성한다.In this case, the first hard mask layer 15 and the second hard mask layer 17 are formed of different insulating materials having different etching selectivity.
여기서, 상기 제1하드마스크층(15)은 산화막, 질화막 또는 산화질화막으로 형성하고 제2하드마스크층(17)은 산화막질화막, 산화질화막으로 형성하되, 상기 제2하드마스크층(17)을 상기 제1하드마스크층(15)의 1/2 - 1/10 의 두께로 형성한다.The first hard mask layer 15 may be formed of an oxide film, a nitride film, or an oxynitride film, and the second hard mask layer 17 may be formed of an oxide film nitride film or an oxynitride film, and the second hard mask layer 17 may be formed in the second hard mask layer 17. It is formed to a thickness of 1/2-1/10 of the first hard mask layer 15.
그 다음, 상기 제2하드마스크층(17) 상부에 감광막패턴(19)을 형성한다. (도 1a)Next, a photoresist pattern 19 is formed on the second hard mask layer 17. (FIG. 1A)
그리고, 상기 감광막패턴(19)을 마스크로 하여 상기 제2하드마스크층(17)을 패터닝한다.The second hard mask layer 17 is patterned using the photoresist pattern 19 as a mask.
그리고, 상기 감광막패턴(19)을 제거하고 세정공정을 실시한다. (도 1b)Then, the photoresist pattern 19 is removed and a cleaning process is performed. (FIG. 1B)
그 다음, 상기 패터닝된 제2하드마스크층(17)을 마스크로 하여 상기 제1하드마스크층(15)을 식각한다.Next, the first hard mask layer 15 is etched using the patterned second hard mask layer 17 as a mask.
이때, 상기 제2하드마스크층(17)도 일정두께 식각된다. (도 1c)At this time, the second hard mask layer 17 is also etched by a predetermined thickness. (FIG. 1C)
그 다음, 상기 제1하드마스크층(15)과 그 상부에 남은 상기 제2하드마스크층(17)을 마스크로 하여 상기 텅스텐막(13)을 식각한다. (도 1d)Next, the tungsten film 13 is etched using the first hard mask layer 15 and the second hard mask layer 17 remaining thereon as a mask. (FIG. 1D)
후속공정으로 상기 제1하드마스크층(15)을 제거하고 상기 텅스텐막(13)으로 형성되는 워드라인을 형성한다.In a subsequent process, the first hard mask layer 15 is removed to form a word line formed of the tungsten film 13.
본 발명의 다른 실시예는 상기 제2하드마스크층의 상부 또는 하부에 50 - 500 Å 두께의 절연막을 형성하는 것이다.Another embodiment of the present invention is to form an insulating film having a thickness of 50-500 에 on or above the second hard mask layer.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 워드라인 형성방법은, 두 개의 하드마스크층을 이용하여 워드라인을 패터닝함으로써 감광막의 두께를 감소시킬 수 있어 예정된 크기의 패턴을 용이하게 형성할 수 있도록 하고 그에 따른 소자의 특성 및 신뢰성을 향상시키고 반도체소자의 수율 및 생산성을 향상시키는 효과를 제공한다.As described above, the word line forming method of the semiconductor device according to the present invention can reduce the thickness of the photoresist layer by patterning word lines using two hard mask layers so that a pattern having a predetermined size can be easily formed. And thereby improving the characteristics and reliability of the device and improving the yield and productivity of the semiconductor device.
Claims (2)
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| KR1020000036857A KR20020002631A (en) | 2000-06-30 | 2000-06-30 | A method for forming a word line of a semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100939109B1 (en) * | 2002-12-26 | 2010-01-28 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100939109B1 (en) * | 2002-12-26 | 2010-01-28 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |