KR20020002161A - Method for forming isolation layer of semiconductor device - Google Patents
Method for forming isolation layer of semiconductor device Download PDFInfo
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- KR20020002161A KR20020002161A KR1020000036643A KR20000036643A KR20020002161A KR 20020002161 A KR20020002161 A KR 20020002161A KR 1020000036643 A KR1020000036643 A KR 1020000036643A KR 20000036643 A KR20000036643 A KR 20000036643A KR 20020002161 A KR20020002161 A KR 20020002161A
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- nitride
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- 238000000034 method Methods 0.000 title claims abstract description 55
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000002955 isolation Methods 0.000 title claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 6
- 230000001590 oxidative effect Effects 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 18
- 238000011065 in-situ storage Methods 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 6
- 239000001301 oxygen Substances 0.000 abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 abstract description 6
- 230000000149 penetrating effect Effects 0.000 abstract description 2
- 238000007517 polishing process Methods 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 230000035515 penetration Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 229920001220 nitrocellulos Polymers 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000009834 vaporization Methods 0.000 description 1
- 230000008016 vaporization Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Plasma & Fusion (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체 소자 분리막 형성 방법에 관한 것으로서, 특히 샐로우 트렌치 소자분리(Shallow Trench Isolation)방법을 개선하여 고집적화 소자에서 요구하는 전기적 특성을 만족시킬 수 있는 반도체 소자 분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device isolation layer, and more particularly, to a method of forming a semiconductor device isolation layer by improving a shallow trench isolation method to satisfy electrical characteristics required by a high integration device.
종래 소자간 분리 기술에서 가장 널리 사용되고 있는 기술은 샐로우 트렌치 소자분리 기술이다. 반도체 고집적화에 따라 반도체의 기본 척도로 제시되는 디자인 룰(design rule)은 약 0.25㎛ 이하의 기본구조를 요구하고 있으며, 기술 발전의 추이는 그 이하의 고집적화를 이루어야만 현재의 반도체공정을 만족하는 단계로 들어서고 있다.The most widely used technique in the conventional isolation between devices is a shallow trench device isolation technology. The design rule proposed as a basic measure of semiconductors according to the high integration of semiconductors requires a basic structure of about 0.25 μm or less, and the progress of technology is required to satisfy the current semiconductor process only when high integration is achieved. Entering into.
기존의 트렌치구조의 방식을 구현할 경우, 고집적화에 따른 활성영역의 감소와 후속 열공정 시의 산소분자 침투 및 스트레스에 의한 전기적 특성의 열화를 가져와 이를 해결하기 위해 여러 방식의 샐로우 트렌치 구조의 소자분리를 사용하여 디자인 룰의 감소에 따른 문제점을 해결해 나가고 있다.In case of implementing the conventional trench structure method, it is possible to reduce the active area due to the high integration and to deteriorate the electrical characteristics due to oxygen molecular penetration and stress during the subsequent thermal process. By using to solve the problem caused by the reduction of design rules.
종래의 반도체 소자 분리막 형성 방법을 도 1내지 도 5를 참조하여 설명하면 다음과 같다.A conventional method of forming a semiconductor device isolation layer is described with reference to FIGS. 1 to 5 as follows.
도 1 내지 도 5는 종래 반도체 소자 분리막 형성 방법을 설명하기 위해 도시된 수직 단면도들이다.1 to 5 are vertical cross-sectional views illustrating a conventional method of forming a semiconductor device isolation layer.
우선 도 1에 도시된 바와 같이, 반도체 기판(10) 상부에 패드 산화막(20) 및 질화막(30)을 적층하고 포토레지스트 패턴(도시하지 않음)을 형성한 후, 이 패턴으로 플라즈마 식각을 수행하여 질화막(30) 및 패드 산화막(20)을 순차적으로 식각하면서 반도체 기판의 소정 깊이까지 식각하여 샐로우 트렌치부(T)를 형성한다.First, as shown in FIG. 1, the pad oxide layer 20 and the nitride layer 30 are stacked on the semiconductor substrate 10, and a photoresist pattern (not shown) is formed, followed by plasma etching using the pattern. The nitride trench 30 is formed by sequentially etching the nitride film 30 and the pad oxide film 20 to a predetermined depth of the semiconductor substrate.
이어서 도 2에 도시된 바와 같이, 상기 공정의 포토레지스트 패턴을 제거하고 이어서 후식각공정으로 샐로우 트렌치부(T)의 형성시 발생하는 실리콘손상(Si damage)을 제거한다. 이 때, 후식각공정 대신 열 산화 공정을 진행한 후에 식각해내는 방법도 있다. 후식각공정은 3:1의 비율로 섞은 CF4와 O2혼합가스를 이용하여 챔버 내에서 플라즈마 방식에 의해 이루어진다.Subsequently, as shown in FIG. 2, the photoresist pattern of the process is removed, and then silicon damage generated during the formation of the shallow trench portion T by a post etching process is removed. At this time, there is also a method of etching after the thermal oxidation process instead of the post etching process. The post-etching process is performed by plasma method in the chamber using a mixture of CF 4 and O 2 mixed at a 3: 1 ratio.
그 다음 도 3에 도시된 바와 같이, 코너 산화(corner oxidation)를 실시한다. 그러면 후속공정 시, 샐로우 트렌치부(T)의 실리콘 계면과 질화 라이너막(40) 또는 갭필 산화막(gap fill oxide)(50)의 계면에서의 트랩 사이트(trap site)를 감소시키는 효과가 있다.Then, corner oxidation is performed as shown in FIG. Then, in a subsequent process, there is an effect of reducing the trap site at the interface between the silicon trench of the shallow trench portion T and the nitride liner film 40 or the gap fill oxide film 50.
그리고 도 4에 도시된 바와 같이, 질화 라이너막(Nitride Liner)(40)을 증착한다.As shown in FIG. 4, a nitride liner 40 is deposited.
마지막으로 도 5에 도시된 바와 같이, 갭필 산화막(50)으로 상기 샐로우 트렌치부(T)를 채우고 화학적 기계적 연마 공정을 실시하여 평탄화를 진행시킨다.Finally, as illustrated in FIG. 5, the gap trench oxide 50 is filled with the trench trench portion T, and a chemical mechanical polishing process is performed to planarize.
도 6은 종래 반도체 소자 분리막의 형성 방법 중에서 트렌치부를 형성하고 코너 산화를 시행한 후에 질화 라이너막을 증착하지 않고 갭필 산화막을 증착시킨후 관찰되는 트렌치 내부의 스트레스 분포도이다.FIG. 6 is a diagram illustrating stress distribution inside a trench observed after depositing a gapfill oxide film without depositing a nitride liner film after forming a trench and performing corner oxidation in a conventional method of forming a semiconductor device isolation film.
도 6에 나타나 있듯이 샐로우 트렌치부(T) 모서리 부분에 스트레스가 집중되어 있는 것을 볼 수 있다. 질화 라이너막(40)은 이러한 스트레스를 완화시켜 갭필 산화막의 팽창으로 스트레스가 증가되어 발생하는 전기적 특성의 열화를 억제한다.As shown in Figure 6 it can be seen that the stress is concentrated in the corner portion of the shallow trench (T). The nitride liner film 40 relieves such stresses and suppresses deterioration of electrical characteristics caused by stress increase due to expansion of the gapfill oxide film.
또한 후식각공정과 코너산화공정에 의한 샐로우 트렌치부(T) 위쪽의 모트(moat)발생과 갭필 산화막(50)의 산소 분자(O2)가 반도체 기판(10)에 침투하는 것을 방지한다.In addition, the moat generated above the shallow trench portion T by the post etching process and the corner oxidation process and the oxygen molecules O 2 of the gap fill oxide film 50 are prevented from penetrating into the semiconductor substrate 10.
이 때, 질화 라이너막(40)대신 CVD(Chemical Vaporization Deposition)산화막을 써도 좋다.In this case, a CVD (Chemical Vaporization Deposition) oxide film may be used instead of the nitride liner film 40.
하지만 상기와 같은 종래 기술에서는 후식각공정과 코너 산화로 인하여 활성 영역의 손실(active region loss)이 생겨나고, 고집적 소자에서는 질화 라이너막(40)의 증착 공정으로 인해 샐로우 트렌치부(T) 넓이가 줄어들어 갭필 산화막 증착 시 보이드(void)가 발생하여 전기적 특성에 문제점이 생긴다.However, in the prior art as described above, an active region loss occurs due to the post etching process and the corner oxidation, and in the highly integrated device, the width of the shallow trench portion T is due to the deposition process of the nitride liner layer 40. As a result, voids are generated when the gapfill oxide film is deposited, which causes problems in electrical characteristics.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여, 반도체 소자 분리막 형성시 트렌치부가 형성된 기판에 질화막을 증착하고 산화시켜 질산화막을 형성시킴으로서, 활성 영역을 줄이지 않고 트렌치부의 넓이를 증가시켜 갭필 산화막 증착 시 보이드의 생성을 방지함으로서 고집적소자에서 요구하는 전기적 특성을 만족시킴과 동시에 산화질화막이므로 계면특성 또한 개선되며, 산소분자의 침투를 방지하고, 산화막의 팽창에 의한 스트레스를 감소시킬 수 있는 반도체 소자 분리막 형성 방법을 제공하는데 있다.An object of the present invention is to form a nitride film by depositing and oxidizing a nitride film on a substrate formed with a trench when forming a semiconductor device isolation layer, in order to solve the problems of the prior art as described above, by increasing the width of the trench without reducing the active area gap fill It prevents the formation of voids during the deposition of oxide film, which satisfies the electrical characteristics required by high-integration devices, and also improves the interfacial properties as it is an oxynitride film, prevents penetration of oxygen molecules, and reduces stress due to expansion of the oxide film. The present invention provides a method of forming an isolation layer.
도 1내지 도 5는 종래 반도체 소자 분리막 형성 방법을 설명하기 위해 도시된 수직 단면도들이다.1 to 5 are vertical cross-sectional views illustrating a conventional method of forming a semiconductor device isolation layer.
도 6은 종래 반도체 소자 분리막 형성 방법 중에서, 트렌치부를 형성하고 코너 산화를 시행한 후에 질화라이너막을 증착하지 않고 갭필 산화막을 증착시킨 후 관찰되는 트렌치 내부의 스트레스 분포도이다.FIG. 6 is a diagram illustrating stress distribution inside a trench observed after depositing a gap fill oxide film without depositing a nitride liner film after forming a trench and performing corner oxidation in a conventional method of forming a semiconductor device isolation film.
도 7내지 도 11은 본 발명에 따른 반도체 소자 분리막 형성 방법을 설명하기 위해 도시된 수직 단면도들이다.7 to 11 are vertical cross-sectional views illustrating a method of forming a semiconductor device isolation film in accordance with the present invention.
도 12는 본 발명에 따른 반도체 소자 분리막 형성 방법 중에서, 질화 라이너막의 산화 공정시 쓰이는 인-시튜 스팀 제너레이션의 공정도이다.12 is a process diagram of in-situ steam generation used in the oxidation process of the nitride liner film in the method of forming a semiconductor device isolation film according to the present invention.
＊도면의 주요 부분에 대한 부호의 명칭＊＊ Name of code for main part of drawing ＊
10: 실리콘 기판 20: 패드 산화막10 silicon substrate 20 pad oxide film
30: 질화막 40: 질화 라이너막30: nitride film 40: nitrided liner film
50: 갭필 산화막 60: 질산화막50: gap fill oxide film 60: nitric oxide film
T: 트렌치부T: trench
상기 목적을 달성하기 위하여 본 발명은 반도체 기판 상에 패드 산화막과 질화막을 차례로 적층하는 단계와, 상기 질화막 위에 포토레지스트 패턴을 형성하고 상기 포토레지스트 패턴을 식각마스크로 식각공정을 시행하여 반도체 기판 내에 샐로우 트렌치부를 형성하고 상기 포토레지스트를 제거하는 단계와, 상기 결과물에 후식각공정을 실시하여 실리콘 손상을 제거하는 단계와, 상기 결과물에 질화 라이너막을 증착한 후 상기 질화 라이너막을 산화시키는 단계와, 상기 트렌치부를 갭필 산화막으로 채우고 화학적 기계적 연마를 이용하여 평탄화 공정을 시행하는 단계와, 상기 공정 이후 상기 질화막을 제거하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention comprises the steps of laminating a pad oxide film and a nitride film on a semiconductor substrate in turn, forming a photoresist pattern on the nitride film, and etching the photoresist pattern with an etching mask. Forming a low trench and removing the photoresist, performing a post-etching process on the resultant to remove silicon damage, depositing a nitride liner layer on the resultant, and oxidizing the nitride liner layer; Filling the trench with a gapfill oxide film and performing a planarization process using chemical mechanical polishing; and removing the nitride film after the process.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 7 내지 도 11은 본 발명에 따른 반도체 소자의 분리막의 형성 방법을 설명하기 위해 도시된 수직 단면도들이다.7 to 11 are vertical cross-sectional views illustrating a method of forming a separator of a semiconductor device according to the present invention.
우선 도 7에 나타난 바와 같이, 반도체 기판(10) 상부에 패드 산화막(20) 및 질화막(30)을 적층하고 포토레지스트 패턴(도시하지 않음)을 형성한 후, 이 패턴으로 플라즈마 식각을 수행하여 상기 질화막(30) 및 패드 산화막(20)을 순차적으로식각하면서 기판의 소정 깊이까지 식각하여 샐로우 트렌치부(T)를 형성한다.First, as shown in FIG. 7, the pad oxide layer 20 and the nitride layer 30 are stacked on the semiconductor substrate 10, a photoresist pattern (not shown) is formed, and plasma etching is performed using the pattern. The nitride trench 30 is formed by sequentially etching the nitride film 30 and the pad oxide film 20 to a predetermined depth of the substrate.
이어서, 도 8에 도시된 바와 같이 후식각공정으로 상기 샐로우 트렌치부(T)의 형성시 발생하는 실리콘손상을 제거한다. 이 때, 후식각공정 대신 열 산화 공정을 진행한 후에 식각해내는 방법도 있다. 후식각공정은 3:1의 비율로 섞은 CF4와 O2혼합가스를 이용하여 챔버 내에서 플라즈마 방식에 의해 이루어진다.Subsequently, as illustrated in FIG. 8, silicon damage generated when the shallow trench portion T is formed by a post etching process is removed. At this time, there is also a method of etching after the thermal oxidation process instead of the post etching process. The post-etching process is performed by plasma method in the chamber using a mixture of CF 4 and O 2 mixed at a 3: 1 ratio.
그 다음 도 9에 도시된 바와 같이, 저압 화학 기상 증착(Low Pressure- Chemical Vapor Deposition)방법으로 10∼200Å정도 두께의 질화 라이너막(40)을 형성한다.Next, as illustrated in FIG. 9, a nitride liner film 40 having a thickness of about 10 to about 200 kPa is formed by a low pressure chemical vapor deposition method.
그 후에 도 10에 도시된 바와 같이, 인-시튜 스팀 제너레이션(In-Situ Steam Generation) 방식을 이용하여 상기 질화 라이너막(40)을 산화시켜 질산화막(60)을 형성한다.Thereafter, as illustrated in FIG. 10, the nitride liner layer 40 is oxidized using an in-situ steam generation method to form the nitride oxide layer 60.
인-시튜 스팀 제너레이션은 본래 고품질의 게이트 산화막(Gate oxide)을 형성할 때 사용되는 공정으로, 본 발명에서는 이를 이용하여 질화막을 산화시키게 된다.In-situ steam generation is a process originally used to form a high quality gate oxide, and in the present invention, the nitride film is oxidized using the same.
인-시튜 스팀 제너레이션에 의한 질화막의 산화 원리를 도 12를 참조하여 설명하면 다음과 같다.The principle of oxidation of the nitride film by in-situ steam generation will be described with reference to FIG. 12.
수소와 산소가스를 이용한 10 Torr 이하의 저압에서 이루어지는 공정으로 챔버 내에서 수소와 산소가스는 아래와 같은 반응을 보인다.The process is performed at low pressure below 10 Torr using hydrogen and oxygen gas.
H2+ O2→ 2OHH 2 + O 2 → 2OH
H2+ O2→ H2O + HH 2 + O 2 → H 2 O + H
O2+ H → OH + OO 2 + H → OH + O
H2+ O → OH + OH 2 + O → OH + O
위와 같은 반응으로 생성된 산소 원자와 수산화기가 반도체 기판(10)에 공급되어 상기 질화 라이너막(40)을 산화시킨다. 이 때 산화 정도는 증착된 상기 질화 라이너막(40)을 전부 산화시키고 반도체 기판(10)까지 소정 깊이 산화시켜 상기 질화 라이너막(40)과 실리콘 계면 사이의 댕글링 결합(dangling bond)을 제거할 수 있도록 한다. 이렇게 형성된 질산화막(60)은 후속 공정에 의한 산소 분자의 반도체 기판에의 침투를 억제하고, 이후 갭필 산화막 증착시 발생되는 스트레스의 완충역할을 한다. 또한 질산화막(60) 형성으로 계면 특성이 개선되고, 활성 영역을 줄이지 않고 샐로우 트렌치부(T)의 넓이를 증가시켜 갭필 산화막 증착 시 생성되는 보이드를 방지함으로서 전기적 특성을 개선할 수 있다.Oxygen atoms and hydroxyl groups generated by the above reaction are supplied to the semiconductor substrate 10 to oxidize the nitride liner layer 40. At this time, the degree of oxidation is to oxidize all the deposited nitride liner film 40 and to oxidize the semiconductor substrate 10 to a predetermined depth to remove dangling bonds between the nitride liner film 40 and the silicon interface. To help. The nitride oxide film 60 formed as described above suppresses the penetration of oxygen molecules into the semiconductor substrate by a subsequent process, and then acts as a buffer for stress generated during deposition of the gapfill oxide film. In addition, the interfacial properties are improved by forming the nitric oxide layer 60, and the electrical properties may be improved by increasing the width of the shallow trench portion T without reducing the active region, thereby preventing voids generated during deposition of the gapfill oxide layer.
마지막으로 도 11에 도시된 바와 같이, 갭필 산화막(50)을 형성하고 화학적 기계적 연마를 한 후 상기 질화막(30)을 제거하여 본 발명에 따른 반도체 소자 분리막을 형성한다.Finally, as shown in FIG. 11, after forming the gap fill oxide film 50 and performing chemical mechanical polishing, the nitride film 30 is removed to form a semiconductor device isolation film according to the present invention.
상기와 같이 본 발명은, 반도체 소자 분리막 형성 시 반도체 기판에 트렌치부를 형성하고 질화 라이너막을 증착하고 산화시켜 질산화막을 형성함으로서, 후속산화 공정 및 열 공정에 의한 산소 분자의 반도체 기판에의 침투 억제와 갭필 산화막 증착 시 발생되는 스트레스를 완화시킬 수 있다.As described above, the present invention forms a trench in the semiconductor substrate when the semiconductor device isolation layer is formed, and deposits and oxidizes a nitride liner film to form a nitrate film, thereby suppressing the penetration of oxygen molecules into the semiconductor substrate by a subsequent oxidation process and a thermal process and gap fill. The stress generated during the deposition of the oxide film can be alleviated.
또한 질산화막 형성으로 계면 특성이 개선되고 활동 영역의 손실 없이 샐로우 트렌치부의 넓이를 증가시켜 갭필 산화막 증착 시 보이드 생성을 방지하여 전기적 특성 효과를 개선할 수 있는 이점이 있고, 게이트 산화막 형성시 사용하는 장비를 소자분리막을 형성할 때 이용함으로서 원가 절감과 수율 향상의 효과를 얻을 수 있다.In addition, the formation of nitric oxide improves the interfacial properties and increases the width of the shallow trench without loss of the active area, thereby preventing voids during deposition of the gap fill oxide, thereby improving the effect of electrical properties. By using the equipment to form a device isolation film it is possible to reduce the cost and improve the yield.
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| KR100460770B1 (en) * | 2002-07-19 | 2004-12-09 | 주식회사 하이닉스반도체 | Method for forming trench type isolation layer in semiconductor device |
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| US5763315A (en) * | 1997-01-28 | 1998-06-09 | International Business Machines Corporation | Shallow trench isolation with oxide-nitride/oxynitride liner |
| US5780346A (en) * | 1996-12-31 | 1998-07-14 | Intel Corporation | N2 O nitrided-oxide trench sidewalls and method of making isolation structure |
| KR20000003489A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Device separation film forming method for semiconductor device |
| KR20000019032A (en) * | 1998-09-08 | 2000-04-06 | 윤종용 | Isolation method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5780346A (en) * | 1996-12-31 | 1998-07-14 | Intel Corporation | N2 O nitrided-oxide trench sidewalls and method of making isolation structure |
| US5763315A (en) * | 1997-01-28 | 1998-06-09 | International Business Machines Corporation | Shallow trench isolation with oxide-nitride/oxynitride liner |
| KR20000003489A (en) * | 1998-06-29 | 2000-01-15 | 김영환 | Device separation film forming method for semiconductor device |
| KR20000019032A (en) * | 1998-09-08 | 2000-04-06 | 윤종용 | Isolation method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100460770B1 (en) * | 2002-07-19 | 2004-12-09 | 주식회사 하이닉스반도체 | Method for forming trench type isolation layer in semiconductor device |
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