KR20020001229A - Manufacturing method of pMOSFET - Google Patents
Manufacturing method of pMOSFET Download PDFInfo
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- KR20020001229A KR20020001229A KR1020000035640A KR20000035640A KR20020001229A KR 20020001229 A KR20020001229 A KR 20020001229A KR 1020000035640 A KR1020000035640 A KR 1020000035640A KR 20000035640 A KR20000035640 A KR 20000035640A KR 20020001229 A KR20020001229 A KR 20020001229A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 125000006850 spacer group Chemical group 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- -1 oxygen ions Chemical class 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000005036 potential barrier Methods 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
Description
본 발명은 p형 모스 전계효과 트랜지스터(Metal Oxide Semiconductor FieldEffect Transistor; 이하 pMOS BET라 칭함)의 제조방법에 관한 것으로서, 특히 버리듯 채널(buried channel;이하 BC라 칭함) pMOSFET의 채널 하부에 산소를 이온 주입하여 채널과 기판의 N웰을 분리시켜 p채널과 N웰 및 P+ 소오스/드레인영역이 만나는 부분을 제거하여 오프 누설전류의 통로를 차단시켜 포텐셜 베리어의 감소를 방지하여 BC-pMOSFET 의 오프상태 누설전류 특성을 향상시킬 수 있는 pMOSFET의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for manufacturing a p-type MOS field effect transistor (hereinafter referred to as pMOS BET), in which oxygen is implanted into a lower portion of a channel of a buried channel pMOSFET. The N well of the channel and the substrate is separated to remove the portion where the p channel and the N well and the P + source / drain region meet to block the passage of off leakage current to prevent the reduction of potential barrier to prevent the BC-pMOSFET off-state leakage current. It relates to a method of manufacturing a pMOSFET that can improve the characteristics.
반도체소자가 고집적화 되어 감에 따라 소자의 크기를 감소시키기 위하여 MOSFET의 게이트전극이나 소오스/드레인영역 및 이들과의 콘택튼 공정 전반의 디자인 룰이 감소되고 있으나, 게이트전극의 폭과 전기저항은 비례 관계에 있어 폭이 N배 줄어들면 전기 저항이 N배 증가되어 반도체소자의 동작 속도를 떨어뜨리는 문제점이 있다. 따라서 게이트전극의 저항을 감소시키기 위하여 가장 안정적인 MOSFET 특성을 나타내는 폴리실리콘층/산화막 계면의 특성을 이용하여 폴리실리콘층과 실리사이드의 적층 구조인 폴리사이드가 저 저항 게이트로서 사용하기도 한다.As semiconductor devices become more integrated, the design rules of the gate electrode, source / drain regions, and contacton processes with MOSFETs are reduced to reduce the size of the device, but the width and electrical resistance of the gate electrode are proportional to each other. When the width is reduced by N times, the electrical resistance is increased by N times, which causes a problem of lowering the operation speed of the semiconductor device. Therefore, in order to reduce the resistance of the gate electrode, the polysilicon, which is a laminated structure of the polysilicon layer and the silicide, may be used as the low resistance gate by using the characteristics of the polysilicon layer / oxide layer interface having the most stable MOSFET characteristics.
또한 p 또는 n형 반도체기판에 n 또는 p형 불순물로 형성되는 pn 접합은 불순물을 반도체기판에 이온 주입한 후, 열처리로 활성화시켜 확산영역을 형성한다. 따라서 채널의 폭이 감소된 반도체소자에서는 확산영역으로부터의 측면 확산에 의한 짧은채널효과(short channel effect)를 방지하기 위하여 접합깊이를 얕게 형성하여야 하며, 드레인으로의 전계 집중에 의한 접합 파괴 방지와 열전하효과에 의한 문턱전압 변화를 방지하기 위하여 소오스/드레인 영역을 저농도 불순물 영역을 갖는 엘.디.디(lightly doped drain; 이하 LDD라 칭함) 구조로 형성하는 등의 방법이사용된다.In addition, a pn junction formed of n or p type impurities on a p or n type semiconductor substrate is ion implanted into the semiconductor substrate and then activated by heat treatment to form a diffusion region. Therefore, in the semiconductor device with reduced channel width, the junction depth should be shallow to prevent short channel effect due to side diffusion from the diffusion region. In order to prevent the threshold voltage change caused by the lowering effect, a method such as forming a source / drain region into a lightly doped drain (LDD) structure having a low concentration impurity region is used.
종래의 기술에 따른 BC-pMOSFET의 제조방법을 도 1을 참조하여 살펴보면 다음과 같다.Looking at the manufacturing method of the BC-pMOSFET according to the prior art with reference to FIG.
먼저, p형 실리콘 웨이퍼 반도체 기판(10)상에 얕은 트랜치 소자분리막(12)을 형성하고, N웰, p채널필드스톱, 깊은 p채널 Vt 조절등의 이온주입을 실시하고, 반도체기판(10) 상에 게이트산화막(14)과 게이트전극(16)을 형성한 후, p형 불순물로 LDD 이온주입을 실시하여 저농도 불순물영역(18)을 형성한다. (도 1a 참조).First, a shallow trench isolation film 12 is formed on the p-type silicon wafer semiconductor substrate 10, and ion implantation such as N well, p-channel field stop, and deep p-channel Vt control is performed, and then the semiconductor substrate 10 is formed. After the gate oxide film 14 and the gate electrode 16 are formed on the LDD ion implantation with p-type impurities, a low concentration impurity region 18 is formed. (See FIG. 1A).
그다음 상기 게이트전극(16)의 측벽에 산화막으로 스페이서(20)를 형성하고, 다시 p형 불순물을 고농도로 이온주입하여 소오스 및 드레인영역(22,24)을 형성한다. (도 1b 참조).A spacer 20 is then formed on the sidewall of the gate electrode 16 with an oxide film, and ion source is implanted at a high concentration to form source and drain regions 22 and 24. (See FIG. 1B).
상기와 같이 형성된 종래 기술에 따른 BC-pMOSFET는 도 2에 도시된 바와 같이, 소오스영역(20)에 0V, 드레인영역(22)에 -2V, 게이트전극(16)에 0V의 전압이 인가될 때, 도면과 같은 오프 누설전류 경로를 가지게 된다.In the conventional BC-pMOSFET formed as described above, when a voltage of 0V is applied to the source region 20, -2V to the drain region 22, and 0V to the gate electrode 16, as shown in FIG. In this case, the leakage current path of FIG.
여기서 드레인영역(24)의 포켓 부분 ⓐ에 경로가 형성됨을 알 수 있다.It can be seen that a path is formed in the pocket portion ⓐ of the drain region 24.
도 3은 수직 깊이에 따른 수평 방향 포텐셜의 위치별 변화 그래프로서, n웰과 포켓 및 P+ 소오스/드레인영역이 만나는 부분에서 수평 포텐셜 베리어가 감소되어, 오프상태 누설전류가 증가되고, 이에 따라 파워소모가 증가되어 소자의 동작속도를 떨어뜨리며, 전체적으로 소자의 신뢰성과 품질을 저해하게 된다.FIG. 3 is a graph of the positional change of the horizontal potential according to the vertical depth, and the horizontal potential barrier is reduced at the portion where the n well and the pocket and the P + source / drain region meet, thereby increasing the off-state leakage current, and thus power consumption. This increases the operating speed of the device, and reduces the reliability and quality of the device as a whole.
즉 BC-pMOSFET의 제오프상태 누설전류는That is, the off-state leakage current of BC-pMOSFET
Ioff= kT/q * log10[1+(εiX1+ εsd)/εi(X2+ X3)] 로 표시된다.I off = kT / q * log 10 [1+ (ε i X 1 + ε s d) / ε i (X 2 + X 3 )].
상기 εi는 절연체의 퍼미티비티(permitivity), εs는 반도체 퍼미티비티, d 는 게이트산화막 두께, X1은 게이트필드 디프리션 크기, X2는 p채널영역의 디프리션 크기, X3는 N웰영역의 디프리션 크기이다.Ε i is the permittivity of the insulator, ε s is the semiconductor permission, d is the gate oxide thickness, X 1 is the gate field diffusion size, X 2 is the depth of p channel region, X 3 is the distortion size of the N well region.
여기서 X1과 d는 표면 포텐셜 및 게이트산화막 두께에 관련된 것으로서, 소자의 신뢰성과의 관계를 고려할 때, 이들을 줄이는 것은 기술적으로 매우 어려우므로, p채널과 n웰의 불순물 농도와 관계되는 X2와 X3를 줄여야 하나, p채널을 더욱 얕고 급경사지게 만드는 것은 양산단계에서 적용할 수 있을 정도로 검증된 기술이 없어 어려운 실정이다.Where X 1 and d are related to the surface potential and the gate oxide thickness, and considering the relationship with the reliability of the device, it is technically very difficult to reduce them, so X 2 and X are related to the impurity concentrations of the p-channel and n-well. Although 3 must be reduced, making the p-channel shallower and steep is difficult because there is no proven technology that can be applied in mass production.
상기와 같은 종래 기술에 따른 BC-pMOSFET의 제조방법은 소자의 고집적화에 따른 채널 폭 감소에 대한 얕은 채널 형성에 한계가 있으며, 게이트전압이 0V일 때 오프전류 특성이 열악하여 어느정도 이하의 채널폭을 가지는 pMOSFET의 제조가 불가능하여 소자의 고집적화를 저해하는 문제점이 있다.In the conventional BC-pMOSFET fabrication method, there is a limitation in forming a shallow channel for reducing the channel width due to the high integration of the device. Since the pMOSFET cannot be manufactured, there is a problem of inhibiting high integration of the device.
또한 n웰과 포켓 및 P+ 소오스/드레인영역이 만나는 부분에서 수평 포텐셜 베리어가 감소 → 오프상태 누설전류가 증가 → 파워소모가 증가 → 소자의 동작속도를 저하시키는 문제점이 있다.In addition, there is a problem in that the horizontal potential barrier is reduced at the portion where the n well and the pocket and the P + source / drain region meet → the off-state leakage current increases → the power consumption increases → the operation speed of the device is reduced.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은BC-pMOSFET의 p채널 하부에 산소 이온을 주입하여 n웰과 포켓 및 P+ 소오스/드레인영역이 만나는 부분을 차단하여 수평 포텐셜의 변화를 방지하여 오프 상태 누설전류 특성을 향상시킬 수 있는 pMOSFET의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to inject oxygen ions into the lower part of the p-channel of the BC-pMOSFET to block a portion where the n well and the pocket and the P + source / drain region meet each other. The present invention provides a method of manufacturing a pMOSFET that can prevent a change and improve an off-state leakage current characteristic.
도 1a 및 도 1b는 종래 기술에 따른 pMOSFET의 제조공정도.1A and 1B are manufacturing process diagrams of a pMOSFET according to the prior art.
도 2는 종래 pMOSFET의 오프상태 누설전류 경로를 표시한 단면도.2 is a cross-sectional view showing an off-state leakage current path of a conventional pMOSFET.
도 3은 종래 pMOSFET의 수직 깊이에 따른 수평 방향 포텐셜의 위치별 변화 그래프.3 is a graph of changes in position of a horizontal potential according to a vertical depth of a conventional pMOSFET.
도 4a 내지 도 4e는 본 발명에 따른 pMOSFET의 제조 공정도.4A-4E are process diagrams of fabricating a pMOSFET in accordance with the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
10 : 반도체 기판 12 : 얕은 트랜치 소자분리산화막10 semiconductor substrate 12 shallow trench isolation oxide film
14 : 게이트산화막 16 : 게이트전극14 gate oxide film 16 gate electrode
18 : 저농도 불순물영역 20 : 스페이서18: low concentration impurity region 20: spacer
22 : 소오스영역 24 : 드레인영역22: source region 24: drain region
30 : 절연층 32 : 산화막30: insulating layer 32: oxide film
34 : 도전층34: conductive layer
상기와 같은 목적을 달성하기 위해 본 발명에 따른 pMOSFET 제조방법의 특징은,Features of the pMOSFET manufacturing method according to the present invention to achieve the above object,
반도체기판 상에 채널로 예정되어있는 부분을 노출시키는 홈을 구비하는 절연막 패턴을 형성하는 공정과,Forming an insulating film pattern having a groove for exposing a portion intended as a channel on the semiconductor substrate;
상기 노출되어있는 반도체기판 내에서 트랜지스터의 채널 하부부분에 산화막을 형성하는 공정과,Forming an oxide film on a lower portion of a channel of the transistor in the exposed semiconductor substrate;
상기 구조의 전표면에 도전층을 형성하여 홈을 매립하는 공정과,Forming a conductive layer on the entire surface of the structure to fill the groove;
상기 절연층상의 도전층을 제거하여 홈을 메운 게이트전극을 형성하는 공정과,Removing the conductive layer on the insulating layer to form a gate electrode filled with grooves;
상기 절연층 패턴을 제거하는 공정과,Removing the insulating layer pattern;
상기 게이트전극 양측의 반도체기판에 이온주입을 실시하여 저농도불순물영역을 형성하되 상기 산화막과 일부 중첩되도록 형성하는 공정과,Forming a low concentration impurity region by implanting ions into the semiconductor substrates on both sides of the gate electrode, but partially overlapping the oxide film;
상기 게이트전극의 측벽에 스페이서를 형성하는 공정과,Forming a spacer on sidewalls of the gate electrode;
상기 노출되어있는 반도체기판에 고농도 불순물영역을 형성하는 공정을 구비함에 dlTeik.DlTeik. A process for forming a high concentration impurity region in the exposed semiconductor substrate.
또한 본 발명의 다른 특징은 상기 MOSFET의 소자분리를 얕은 채널 소자분리산화막으로 실시하고, 상기 절연층 형성 전에 n웰 형성과 p채널 필드 스톱, 깊은 이온주입을 실시하는 공정을 구비하며, 상기 절연층을 산화막이나 질화막 계열로 형성하고, 상기 산화막 형성을 절연층 패턴에 의해 노출되어있는 반도체기판에서 p채널의 아래 부분을 Rp점으로 하여 산소이온을 주입한 후, 열처리하여 형성하며, 상기 이온주입의 Rp 가 표면으로부터 400Å이고, 상기 산소이온주입을 1.0E12∼5.0E12 농도로 10∼30keV의 에너지로 주입하며, 상기 열처리 공정을 700∼800℃의 온도에서 10∼60분 실시하고, 상기 산화막이 300∼500Å 두께로 형성하며, 상기 도전층 형성전에 p채널 Vt 조절을 위한 이온주입을 실시하고, 상기 도전층을 다결정실리콘층이나 실리사이드 또는 금속층으로 형성하며, 상기 절연층상의 도전층 제거공정을 CMP 방법으로 실시한다.In addition, another aspect of the present invention is to perform the device isolation of the MOSFET as a shallow channel device isolation oxide film, and to form the n-well formation, p-channel field stop, deep ion implantation before forming the insulating layer, the insulating layer Is formed by an oxide film or a nitride film series, and the oxide film is formed by injecting oxygen ions at a lower portion of the p-channel as the Rp point in the semiconductor substrate exposed by the insulating layer pattern, followed by heat treatment. Rp is 400 kPa from the surface, and the oxygen ion implantation is injected at an energy of 10 to 30 keV at a concentration of 1.0E12 to 5.0E12, and the heat treatment step is performed at a temperature of 700 to 800 ° C for 10 to 60 minutes, and the oxide film is 300 It is formed to have a thickness of ˜500 μm, and ion implantation for p-channel Vt control is performed before forming the conductive layer, and the conductive layer is formed of a polysilicon layer, a silicide or a metal layer. And removing the conductive layer on the insulating layer by the CMP method.
이하, 첨부된 도면을 참조하여 본 발명에 따른 pMOSFET의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a pMOSFET according to the present invention will be described in detail with reference to the accompanying drawings.
도 4a 내지 도 4e는 본 발명에 따른 pMOSFET의 제조 공정도이다.4A through 4E are manufacturing process diagrams of a pMOSFET according to the present invention.
먼저, n 또는 p형 반도체기판(10)에서 소자분리 영역으로 예정되어있는 부분 상에 얕은 트랜치 소자분리 산화막(12)을 형성하고, n웰 형성과 p채널 필드 스톱, 깊은 이온주입을 실시한 후, 상기 반도체기판(10)에서 p채널로 예정되어있는 부분을 노출시키는 다마신을 위한 절연층(30)을 산화막이나 질화막 계열로 형성한다. (도 4a 참조).First, a shallow trench isolation oxide film 12 is formed on a portion of the n or p-type semiconductor substrate 10 that is intended as an isolation region, and n well formation, p-channel field stop, and deep ion implantation are performed. An insulating layer 30 for damascene exposing a portion of the semiconductor substrate 10 to be defined as a p-channel is formed as an oxide film or a nitride film series. (See FIG. 4A).
그다음 상기 절연층(30)에 의해 노출되어있는 반도체기판(10)에서 p채널의 바로 아래 부분을 이온주입 피크점(Rp: 표면으로부터 약 400Å)으로 하여 산소이온을 1.0E12∼5.0E12 농도로 10∼30keV의 에너지로 주입한 후, 소정조건, 예를들어 700∼800℃의 온도에서 10∼60분바람직하게는 30분 정도 열처리하여 디팩트를 제거하고, p채널의 하부에 300∼500Å 정도 두께의 산화막(32)을 형성한다. (도 4b 참조).Then, in the semiconductor substrate 10 exposed by the insulating layer 30, the lower portion of the p-channel is made into the ion implantation peak point (Rp: about 400 kPa from the surface), and oxygen ions are added at a concentration of 1.0E12 to 5.0E12. After implanting with energy of -30 keV, heat treatment is preferably performed for 10 to 60 minutes at a predetermined condition, for example, temperature of 700 to 800 DEG C for about 30 minutes to remove the defect, and the thickness of about 300 to 500 kV at the bottom of the p-channel. Oxide film 32 is formed. (See FIG. 4B).
그후 상기 반도체기판(10)에 p채널 Vt 조절을 위한 이온주입후에 노출되어있는 반도체기판(10)에 게이트산화막(14)을 형성하고, 상기 구조의 전표면에 게이트전극이 되는 도전층(34)을 도포한다. 상기 도전층(34)은 다결정실리콘층이나 실리사이드 또는 금속층등으로 형성할 수 있다. (도 4c 참조).Thereafter, a gate oxide film 14 is formed on the semiconductor substrate 10 exposed after ion implantation for p-channel Vt control on the semiconductor substrate 10, and the conductive layer 34 serving as a gate electrode on the entire surface of the structure. Apply. The conductive layer 34 may be formed of a polysilicon layer, a silicide or a metal layer. (See FIG. 4C).
그다음 상기 절연층(30)상의 도전층(34)을 화학기계적연마(chemical-mechani cal polishing; 이하 CMP라 칭함) 방법으로 연마하여 절연층(30)을 노출시키면, 상기 절연층(30)의 홈 부분에 다마신된 게이트전극(16)이 형성되고, 그후 상기 절연층(30)을 제거한 후, 상기 게이트전극(16) 양측의 반도체기판(10)에 저농도 p형 불순물을 이온주입하여 저농도 불순물영역(18)을 형성한다. (도 4d 참조).Then, the conductive layer 34 on the insulating layer 30 is polished by chemical-mechani cal polishing (hereinafter referred to as CMP) method to expose the insulating layer 30, and thus the grooves of the insulating layer 30 are exposed. A damascene gate electrode 16 is formed in the portion, and then the insulating layer 30 is removed, and a low concentration impurity region is formed by ion implanting low concentration p-type impurities into the semiconductor substrate 10 on both sides of the gate electrode 16. (18) is formed. (See FIG. 4D).
그후, 상기 게이트전극(16)의 측벽에 산화막으로된 스페이서(20)를 형성하고, 다시 고농도 p형 불순물을 이온주입하여 P+의 소오스영역(22)과 드레인영역(24)을 형성한다. 이때 상기 산화막(32)이 p 채널영역과 n웰 및 소오스/드레인영역이 만나는 경계지역에 형성되어 오프상태 누설전류의 통로를 막는다. (도 4e 참조).Thereafter, a spacer 20 made of an oxide film is formed on the sidewall of the gate electrode 16, and a high concentration of p-type impurities is ion implanted to form a source region 22 and a drain region 24 of P +. At this time, the oxide layer 32 is formed at the boundary area where the p-channel region and the n-well and source / drain regions meet to block the passage of the off-state leakage current. (See FIG. 4E).
상기한 바와 같이 본 발명에 따른 pMOSFET의 제조방법은 다마신 공정을 이용하여 pMOSFET의 채널 하부에 산화막을 형성하여 p 채널영역과 n웰영역을 분리시키고, p 채널영역과 n웰 및 소오스/드레인영역이 만나는 경계지역을 분리시켜 수평 포텐셜 베리어의 감소를 방지하여, 소자의 오프 상태 누설전류를 감시킴과 동시에 소자의 동작특성을 형상 시킬 수 있는 이점이 있다.As described above, the method of manufacturing a pMOSFET according to the present invention uses an damascene process to form an oxide film under a channel of the pMOSFET to separate the p-channel region and the n-well region, and to convert the p-channel region and the n-well and source / drain regions. The boundary area is separated to prevent the reduction of the horizontal potential barrier, thereby monitoring the off-state leakage current of the device and at the same time forming the device operating characteristics.
Claims (12)
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