KR20020000607A - Semiconductor memory device incorporating a column redundancy scheme - Google Patents

Abstract

PURPOSE: A semiconductor memory device having a column redundancy scheme is provided to effectively perform a repairing process using a small number of redundancy bitlines, by repairing a defective main bitline to an arbitrary redundancy bitline. CONSTITUTION: Main segments have a plurality of main bitlines. A redundancy segment has bitlines for replacing defective main bitlines when a defect occurs in the main bitlines. An active redundancy column predecoder has a column redundancy fuse box using a plurality of fuses. The defective main bitline is repaired to an arbitrary redundancy bitline by the active redundancy column predecoder.

Description

A semiconductor memory device having an open redundancy scheme {SEMICONDUCTOR MEMORY DEVICE INCORPORATING A COLUMN REDUNDANCY SCHEME}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a column redundancy scheme.

In general, column redundancy of a semiconductor memory device is performed according to the following principle. If there is a defective main cell or main memory cell in the memory device, the commodity value of the memory chip is lost. This results in a great loss of product productivity. Therefore, even if such a defective main memory cell exists, the semiconductor memory device is repaired by replacing such a defective cell with a previously prepared redundant cell, which causes the memory product to operate normally.

In general, a main bit line connected to a main memory cell is also called a main column, and a redundancy bit line connected to a spare cell is also called a column redundancy. The specification uses the terms main bit line (1, see FIG. 1) and redundancy bit line (2, see FIG. 1).

For reference, factors in the manufacturing process that may cause defects include the presence of impurity particles, generation of a bridge effect in which adjacent metal lines are electrically connected, deterioration of insulation characteristics due to defects in insulating films, and the like. There is this.

Two basic components in an open redundancy scheme: first, a redundancy bit line 2 connected with a spare cell; Secondly, there is an address storage block which stores the main address or main address of the defective main memory cell. If a defective main cell is found during the test process to determine whether the memory is operating normally, which is performed after the production of the chip, the main address of the cell is stored to store the main address of the defective memory cell. It is written to the address storage block and shipped to the finished product. Then, when the main address is input from the outside when the chip is actually used, the chip internally compares with the main address or the main address in the address storage block already input. If there is a match, the spare cell prepared in advance instead of the defective memory cell is used (or accessed). If it does not match, the main cell is used as it is (or accessed).

1 is a block diagram illustrating a schematic configuration of a semiconductor memory device using a thermal redundancy scheme according to the prior art. When the address signal A <3: 0> of the main bit line 1 is input to the chip from the outside, it is input to the column address pre decoder 3 to decode the signals YA targeted to the main bit line. The redundancy decoded signals RYA <3: 0> for <15: 0> and the redundancy bit line 2 are simultaneously generated. The signals YA <15: 0> and RYA <3: 0> serve to control voltages on corresponding bit lines via corresponding lines.

Here, one of sixteen main bit lines 1 is selected by the main address signals A <3: 0> and one of four redundancy bit lines 2 by a signal A <1: 0> at the same time. Is selected, and as a result, main data and redundancy data are simultaneously input to a multiplexer 6 located at the output portion. When the main memory cell is a normal memory cell without defects, the multiplexer 6 selects main data, and the thus selected main data is output from the multiplexer 6. In contrast, when the main memory cell is a defective memory cell, the multiplexer 6 selects the redundancy data, and the thus selected redundancy data is output from the multiplexer 6.

As described above, the selection signal nRs for selecting one of the main data and the redundancy data is input to the input main address signal A <3: 0 in the passive redundancy address pre decoder 5. Generated by &lt; / RTI &gt; and provided to the corresponding multiplexer (2). The redundancy column address predecoder 5 has a built-in column redundancy fuse box, which stores the main address of the defective cell found during the test.

For example, if a defective cell is found at column address A <3: 0> = 1000, the raw box may cut a fuse corresponding to the position of '1100' among the fuses provided in the thermal redundancy fuse box by laser or the like. Organize your logic. As a result, when the address signal A <3: 0> of '1000' is input from the outside of the chip during the application of the product, it is logically recognized as the main address of the defective main cell, and the selection signal nRs is appropriately converted and outputted. When the redundancy data is selected by the multiplexer 6 and other addresses A <3: 0> are inputted, the selection signal nRs is switched (toggled) so that the main data is selected by the multiplexer 6.

FIG. 2 is a schematic diagram of the maintenance by the specific relationship between the main bit line 1 and the redundancy bit line 2 by the repair according to the thermal redundancy of the prior art, to illustrate one disadvantage of the prior art. There is a main segment 9 (main segment 1) repeated with BL <15: 0> represented by 16 main bit lines as one main segment 8 (main segment 0). On the other hand, there is one or more repair segment 10 (repair segment 0) for RBL <3: 0> represented by four redundancy bit lines (2). At this time, in the related art, a bit line of a main cell which can be replaced by a complementary segment has a specific relationship. For example, in FIG. 2, RBL <0> of the complement segment 10 may replace BL <0, 4, 8, 12>, and RBL <1> of the complement segment 10 is BL <1, 5, 9 , 13>. For example, normal maintenance is done as follows. If BL <0> and BL <1> of the main segment 8 are the main bit lines to be repaired, it is possible to repair using RBL <0> and RBL <1> of the complementary segment.

However, the open redundancy scheme according to the prior art has a problem that there is an example that is not repairable. That is, as shown in FIG. 2, when a defect occurs in the same column, for example, BL <0>, simultaneously in the main segment 8 and the main segment 9, the RBL <of the repair segment capable of repairing the BL <0> is repaired. Since there is only one 0>, maintenance is impossible and the product cannot be used.

In other words, the column redundancy fuse box in the redundancy column address predecoder 5 of FIG. 1 has a relationship in which a specific main bit line is repaired by a specific redundancy bit line in the logic circuit configuration at the design stage. That is, there is a feature that cannot be repaired by any redundancy bit line. As a result, when there are a large number of defective main cells among the redundancy bit lines, if a replaceable redundancy bit line overlaps due to the condition of the specific relationship, repair is impossible and the chip cannot be used. In addition, under the above specific relationship, in order to be able to perform various repairs, a large number of redundancy bit lines must be set inefficiently at the design stage, resulting in an increase in cost due to an increase in the required area of the chip.

Accordingly, it is an object of the present invention to provide a thermal redundancy scheme of a semiconductor memory device that can improve redundancy efficiency by repairing a defective main bit line with an arbitrary redundancy bit line.

It is another object of the present invention to provide an open redundancy scheme of a semiconductor memory device capable of repairing defective bit lines by one fuse box when adjacent main bit lines are electrically connected without using a separate fuse box.

1 is a block diagram showing a schematic configuration of a semiconductor memory device using a thermal redundancy scheme according to the prior art;

2 is a view for explaining a problem according to the prior art;

3 is a block diagram showing a schematic configuration of a semiconductor memory device using a thermal redundancy scheme according to the present invention;

FIG. 4 is a view for explaining an operation of replacing two main rows in which defective ones are replaced with spare columns based on a repair method using thermal redundancy according to the present invention; FIG.

5 is a circuit diagram showing a column redundancy fuse box in an active redundancy column address predecoder according to a first embodiment of the present invention; And

6 is a circuit diagram illustrating a column redundancy fuse box in an active redundancy column address predecoder according to a second embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

1: main bit line 2: redundancy bit line

3: column address predecoder

4: redundancy column address predecoder

5: Passive Redundancy Column Predecoder 6: Multiplexer

7: Active Redundancy Column Free Decoder

(Configuration)

According to an aspect of the present invention for achieving the above object, a semiconductor memory device includes a main segment having a plurality of main bit lines; A redundancy segment having redundancy bit lines for replacing defective main bit lines when the main bit lines fail; And an active redundancy column predecoder having a column redundancy fuse box using a plurality of fuses, wherein the defective main bit line is repaired by the active redundancy column free decoder to any redundancy bit line.

In this embodiment, by appropriately disconnecting the fuses of the thermal redundancy fuse box embedded in the active redundancy column free decoder, the NMOS transistors connected to each fuse are switched off or on at the input of the desired address signal, respectively. An output signal of the level is generated.

In this embodiment, the semiconductor memory device additionally includes a trigger active redundancy column free decoder having a fuse column for a four-column repair consisting of a plurality of fuses, and suitably disconnecting the fuses for the four-column repair. For example, four consecutive redundancy bit line address signals are output when any one of the desired two to four adjacent address signals is input.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail based on the reference drawings.

3 is a diagram illustrating a schematic configuration of a semiconductor memory device to which a thermal redundancy scheme according to the present invention is applied. In FIG. 3, components that perform the same function as FIG. 1 are denoted by the same reference numerals.

Compared with the conventional redundancy column free decoder, the semiconductor memory device according to the present invention adopts the active redundancy column free decoder method and is conventional in designing a thermal redundancy fuse box embedded in the free decoder. This rule excludes the specific relationship that appears in, i.e., the limited relationship that can only repair a particular redundancy bit line for a particular main bit line. In the improved scheme, arbitrary redundancy of the main bit line can be repaired. As shown in FIG. 3, the selection signal nRs of the two signals nRs and PRYi generated in the active redundancy column free decoder 7 is sent to a 2: 1 multiplexer 6 to provide main data and redundancy data. The other signal PRYi is input to the redundancy column address predecoder 4 as a signal for operating the selected redundancy bit line. Since the signal for operating the redundancy bit line 2 is present, the redundancy bit line 2 when the main address signal A <3: 0> is input to a normal main cell in the column redundancy method according to the present invention. Since this operation does not work, the loading effect caused by the redundancy bit line 2 can be reduced in the course of signal transmission. In contrast, in the prior art, since signals are always transmitted simultaneously to the main bit line 1 and the redundancy bit line, there is a loading effect by the two bit lines. In particular, in consideration of the fact that the normal main cell occupies most of the chip, this effect of the open redundancy technology according to the present invention is considered to be a greater advantage.

As described above, the thermal redundancy technique according to the present invention excludes a specific relationship between the main bit line 1 and the redundancy bit line 2 as described in the prior art. If this is explained in more detail as follows. FIG. 4 is a diagram schematically illustrating a method of replacing the main bit line 1 with the redundancy bit line 2 by a complement according to the thermal redundancy technique of the present invention. As can be seen from Fig. 4, any redundancy bit line 2 can be repaired in correspondence with any main bit line 1. In the case of the thermal redundancy technique of the present invention shown in Fig. 4, for example, to compensate for each bit line to repair BL <0> of the main segment 8 and BL <1> of the main segment 9, for example. It can be replaced by corresponding to RBL <0> and RBL <1> in the segment 10. In addition, BL <0> arranged in each of the main segments 8 and 9 has the advantage that it can be repaired in the same way even if a defect occurs at the same time.

In the above-described redundancy technique of the present invention, the method of mapping the redundancy bit line 2 to any main bit line 1 is performed by a column redundancy fuse box present in the active redundancy column free decoder 7 of FIG. . FIG. 4 shows a preferred embodiment of a thermal redundancy fuse box in the active redundancy column free decoder 7 shown in FIG. 3.

For example, the operation principle will be described on the assumption that there is a defect in a cell corresponding to the main address signal A <3: 0> = '1000' during a product test. In order to store the address, the fuses 15, 18, 20, and 22 of the fuse box shown in FIG. 4 are terminated by using a laser or the like. The principle is to blow the fuse so that the NMOS transistors are all turned off when the corresponding address comes in so that Node B stays in the 'high' state of the supply voltage (Vcc). In this state, the finished chip is manufactured and actually applied.

It is assumed that the address signal is input from the outside of the chip in actual application. One input signal CREDENi of the NOR gate 14 is an open redundancy enable signal, and a 'low' signal is input to enable a repair process, and the node B is connected to the power supply voltage Vcc by the line charger 13. Suppose that it is charged with) and is in the 'high' state. At this time, the output signal PRYi of the NOR gate 14 outputs 'low'. In this operating state, if the input address corresponding to the main address signal A <3: 0> = '1000' is input, all the NMOS transistors are turned off because the fuses 15, 18, 20, and 22 are blown. Stays in the state. As a result, node B remains 'high', which causes the output signal PRYi of NOR gate 14 to continue to be 'low'. The output signal PRYi in the 'low' state is delivered to the decoder for a certain time. The decoder then outputs the address of the currently defective main bit line instead.

In addition, the selection signal nRs of FIG. 3 is controlled so that the redundancy data is selected instead of the main data in the 2: 1 multiplexer 6. Unlike this example, if a signal other than A <3: 0> = '1000' is input as the address input signal, fuses 16, 17, 19 other than the blown fuses 15, 18, 20, and 22 are input. At least one of the NMOS transistors connected to the second transistor 21 is turned on to become the voltage of the node B. As a result, unlike the previous case, the signal PRYi has a 'high' state. The signal PRYi becomes a signal for determining that the corresponding main cell is a normal cell. That is, it is transmitted to the decoder to control the selection signal nRs of FIG. 3 to select and output main data from the 2: 1 multiplexer 6.

A decoder circuit employing a column redundancy scheme according to another embodiment of the present invention is shown in FIG. Another embodiment of the invention has a four-column repair method. The four-column repair method aims to effectively solve a bridge phenomenon in which a normal cell is electrically connected between adjacent main bit lines among the causes of a defect. If a bridge occurs, a fault may occur in two to four main bit lines.

In this case, when relying on the repair method shown in Fig. 5 instead of the 4-column repair method, the thermal redundancy fuse box used requires two to four corresponding to the defective bit lines, thereby reducing the required area of the chip. Increases. In order to solve this problem, the four-column repair method enables repair of two adjacent to four main bit lines which are defective by a bridge phenomenon with one open redundancy fuse box. The principle is described with reference to FIG. 6 as follows.

The principle of the trigger circuit 25 shown in FIG. 6 is as follows. For example, if the four main bit lines that failed during the test of the producer are A <3: 1> = '1000', '1001', '1010' and '1011', Disconnect the fuse as shown. That is, when the corresponding address is received, the fuse is blown so that all of the NMOS transistors are turned off so that the node B stays at the 'high' state of the power supply voltage Vcc. Therefore, the fuse 15 corresponding to A <3> = '1' is blown out of the fuses 15-22 and the fuse 18 corresponding to A <2> = '0' is blown. Finally, blow fuses 19, 20, 21, 22 to correspond to all cases of A <1: 0>, that is, '00', '01', '10', and '11'. If only one of the above four signals is input, the role of causing the remaining three addresses to be output by the decoder is performed by the trigger circuit 25. The producer uses a method of disconnecting the fuse of the four-column repair fuse box present in the trigger circuit 25 as described in FIG. 4, and the signal PRYi read for a predetermined time as described in FIG. 5 is defective. When the bit line address is 'low' indicating the input state, the trigger circuit 25 outputs a specific signal (high or low) to the decoder 23 so that four redundancy column addresses are output by the decoder 23. do. On the other hand, when the signal PRYi is 'high', the trigger circuit 25 outputs the opposite signal (low or high) so that four redundancy column addresses are not output in the decoder. In this case, the input address signal A <3: 0> indicates a normal main bit line, or only the main bit line of the corresponding address is defective.

As described above, since the open redundancy repair method according to the present invention can repair a defective main bit line to an arbitrary redundancy bit line, the repairing opportunity is greatly improved compared to the repair method of the prior art, thereby reducing the number of redundancies. Efficient maintenance is possible with bit lines. In addition, many fuse boxes can be repaired without the use of separate fuse boxes for each main bit line in case of repairing two to four consecutive defective main bit lines by a bridge or the like that may occur during the process. It is possible to suppress an increase in the required area of the chip due to these.

Claims (3)

Main segments having a plurality of main bit lines; A redundancy segment having redundancy bit lines for replacing defective main bit lines when the main bit lines fail; An active redundancy column free decoder having a thermal redundancy fuse box using a plurality of fuses; And wherein the defective main bit line is repaired by the active redundancy column free decoder to any redundancy bit line. The method of claim 1, By properly disconnecting the fuses of the thermal redundancy fuse box embedded in the active redundancy column free decoder, the NMOS transistors connected to each fuse are switched off or on at the input of a desired address signal to generate an output signal having a desired level. Semiconductor memory device. The method of claim 1, The semiconductor memory device additionally includes a trigger active redundancy column free decoder having a fuse box for a four-column repair composed of a plurality of fuses, and suitably disconnects the fuse for the four-column repair. And at least four consecutive redundancy bit line address signals are output when any one of four to four adjacent address signals is input.