KR100224771B1 - 2 row bridge repair compensation circuit - Google Patents

Abstract

The present invention relates to a two-row repair compensation circuit for repairing two word lines simultaneously connected to a defective cell in a semiconductor memory device, wherein both a sub-decoder address and a main decoder address are used as an address for activating a redundancy word line. This improves the repair performance of the memory device by repairing defective word lines generated at each cycle, and improves productivity by enabling the use of all the wasted chips due to non-repairable word lines. There is this.

Description

2-row bridge repair compensation circuit

1 is a circuit diagram showing a fuse box portion of a typical two-row bridge repair compensation circuit.

Figures 2a and 2b show a typical two-row bridge repair compensation circuit.

2c is a layout diagram of a word line of a general 16M DRAM.

3a and 3b are detailed diagrams of a two-row bridge repair compensation circuit for the present invention.

4 is a detailed diagram of a two-row bridge repair compensation circuit according to another embodiment of the present invention.

5 is a detailed diagram of a two-row bridge repair compensation circuit according to still another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10, 40: sub decoder address input unit

20, 50, 60, 70: main decoder address input section

30: input signal path selection control unit

31: fuse

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-row repair compensation circuit for simultaneously repairing two word lines to which defective cells are connected in a semiconductor memory device. In particular, a defective cell may be repaired due to a metal bridge. It is related to a two-row bridge repair compensation circuit that improves yield.

In general, a low repair circuit is a self-compensation that compensates for a defect by replacing a spare word line with a spare word line to which a defective cell is connected when a defect occurs in any cell in the cell array. When the selected row address is applied into the device, a normal path for selecting a defective cell is broken, and a repair operation is performed instead.

For the convenience of description, the repair circuit will be described with reference to the cell array structure of the 16 mega DRAM currently used.

The 16 mega DRAM consists of four large cell array blocks consisting of 16 cell array small blocks, typically 256k bits per small block for operational stability, resulting in a total of 64 cell array small blocks. There is one spare word line for each small block.

The four cell array blocks are divided into two addresses of the column addresses, and the sixteen cell array small blocks are distinguished by four addresses of the row addresses.

FIG. 1 is a circuit diagram illustrating a fuse box of a repair circuit of a 16M DRAM. A row address is input according to the enable of a ras signal (/ RAS), and a word line is normally received by receiving the address of the memory cell. And a fuse that is connected to each other and cuts a signal designating a normal word line or a column line by disconnecting the fuse corresponding to the address according to the address input of the generated cell when a defect occurs in any one cell (1). ) And a plurality of N MOS transistors 2 connected to one end of the fuses 1 and receiving a cell address through a gate, and the state of the Lars signal / RAS through the inverter INVI. Inverts the outputs of the NAND gate NAND1 and the NAND gate NAND1 receiving the P MOS transistor P1 being turned on and the address signals a and b for selecting a predetermined region among all memory cells. The NAND gate NAND2 and the NAND gate NAND2 which receive a signal output from the inverter INV2 and the inverter INV2 and the potential state of the node 1 connected to one end of the fuse 1, Inverter INV3 and the NAND gate NAND2 outputting a repair active control signal (NRD), which inverts the output to disable the normal word line and thereby drive the redundancy word line. It includes a P MOS transistor (P2) for receiving the feed-back output of the output to the gate terminal to supply a power supply voltage to node 1.

In the fuse box circuit configured as described above, when a defect occurs in a word line and a cell which are normally operated, the fuse 1 connected to the address is disconnected to disable the normal word line.

At the same time, the NRD signal transitions to a high state to operate the repair unit.

2A and 2B are detailed circuit diagrams of a conventional two-row repair compensation circuit, each of two redundancy address signals for detecting word lines that are not adjacent to each other, operating in accordance with the state of the NRD signal output from the fuse box. If any one of them is detected as an input, the word lines to which defective cells are connected are repaired, respectively.

The operation of the circuit will be described with reference to the word line arrangement of the DRAM shown in FIG. 2C.

In order to repair the word line to which the defective cell is connected, the word line is repeated in four cycles of RA0, RA1, RA2, RA3, RA0, RA1, RA2, RA3, RA0 ... etc. by the redundancy address signal RA. When redundancy address signals RA0, RA1, RA2, and RA3 are regarded as the lowest addresses by address decoding, RA0 = RA00, RA1 = RA01, RA2 = RA10, and RA3 = RA11.

The operation process of such a repair circuit is as follows.

First, referring to FIG. 2A, when the repair active control signal / NRD transitions to 'high' in order to select a redundancy word line, the low repair compensation circuit detects one of the two redundancy address signals RA01_0 and RA01_2 input. The operation starts by the redundancy address signal.

First, when the redundancy address signal RA01_0 is detected, the NMOS transistor N1 is turned on so that the potential of the node 2 is already turned on by the transistor N1 and the / NRD signal. It is emitted through the ground potential (Vss) through.

Therefore, the potential of the node 2 becomes low and the potential of the node 4 becomes high to drive the redundancy word line RWL1 by turning on the NMOS transistor N4, where the potential of the redundancy word line is the word line. According to the boosting signal c, a voltage pulled up to 'V _PP ' is applied. When the redundancy address signal RA01_2 is detected, the N MOS transistor N2 is turned on so that the potential of the node 2 is turned on by the transistor N2 and the N-most transistor N3 already turned on by the / NRD signal. Through the ground potential (V _SS ).

Therefore, the potential of node 2 becomes low and the potential of node 4 becomes high to turn on the NMOS transistor N4 to drive the redundancy word line RWL1, where the potential of the redundancy word line is the word line. According to the boosting signal c, a voltage pulled up to 'V _PP ' is applied.

In this case, it can be seen that the row repair compensation circuit (FIG. 2a) drives the redundancy word line RWL1 when any one of the two redundancy dress signals RA01_0 and RA01_2 to be input is detected.

The low repair compensation circuit of FIG. 2B receives redundancy address signals RA01_1 and RA01_3, and replaces another word line that is detected by the detected redundancy address signal with the redundancy word line RWL2. Since the operation and configuration thereof are the same as those of the low repair compensation circuit shown in FIG. 2A, the description thereof will be omitted.

However, in the conventional two-row repair compensation circuit shown in FIG. In this case, the redundancy word lines RWL1 and RWL2 are both enabled by the low repair compensation circuits of FIGS. 2A and 2B to repair the two defective word lines, but the portions having one period of four are adjacent to each other. In the drawings, '○' marked portions (33, 00, 33, 00 ...) there was a problem that can not be repaired.

Accordingly, an object of the present invention is to make it possible to repair all defective word lines by using a sub decoder address and a main decoder address in order to solve the above-described problems.

In order to achieve the above object, in the present invention, an address signal input to one redundancy word line is extended to a sub decoder address input terminal and a main decoder address input terminal, and an input signal path selection control unit is designed to control the input signal. Under the control of the path selection controller, the address of the word line to be repaired is input.

The two-row bridge repair compensating circuit configuration of the present invention, which operates as described above, when a fault occurs in any one of a plurality of cells, disconnects the fuse corresponding to the address according to the address input of the defective cell. In a two-row repair compensation circuit including a fuse box for blocking a signal specifying a word line and a repair unit for outputting a redundancy word line active signal, operation is controlled according to a redundancy active control signal output from the fuse box, n A fuse box symmetrically connected to a sub decoder address input unit for receiving an address signal of a sub decoder and a sub decoder address input unit for repair of two adjacent sub word lines in a single block formed of two sub word lines; Depending on the redundancy active control signal output from A main decoder address input unit which is operation controlled and receives an address signal of a main decoder for repair of two adjacent word lines belonging to two different blocks forming a group of n sub word lines, and the sub decoder address input unit And an input signal path selection control unit for selectively controlling an operation of the main decoder address input unit to switch a path for activating a redundancy word line. The above and other objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A and 3B are circuit diagrams illustrating a two-row bridge repair compensation circuit implemented by the present invention. FIG. 3A is a circuit diagram for activating a redundancy word line RWLI. FIG. 3B is a diagram showing an active redundancy word line RWL2. These circuit diagrams show the subdecoder address input units 10 and 40 for inputting an address when a defect occurs in a word line corresponding to a subdecoder address, and an address when a defect occurs in a word line corresponding to a main decoder address. A main decoder address input section (20, 50) for input and an input signal path selection control section (30) for selectively controlling operations of the sub address input section (10) and the main address input section (20); Since the description is the same as in the prior art, the description is omitted.

The input signal path selection controller 30 pumps a capacitor 31 for selectively activating each of the address input units 10 and 20 and a pumping capacitor for charging / discharging a power voltage applied through the fuse 31. Capacitor: PC3l, inverters INV31 and INV32 for inverting the potential applied through the fuse 31, and NMOS transistors N3l operated by receiving signals output from the inverter INV31 as gates. ).

In addition, since the sub decoder address input unit 10 and the main decoder address input unit 20 are configured in the same manner, the same elements are assigned the same reference numerals.

In the repair circuit of the present invention configured as described above, an operation of performing a repair in the case where a general word line defect occurs (for example, RA01_0 and RA01_1, RA01_1 and RA01_2, RA01I_2 and RA01_3, RA01_3 and RA01_0) will be described. In this case, the circuit is operated without cutting the fuse 31 of the input signal path selection controller 30. When the fuse 31 is not cut, the state of each P MOS transistor P9 applying a power voltage to each of the address input units 10 and 20 is a sub-decoder receiving the voltage output from the inverter INV31. The P MOS transistor P9 in the address input unit 10 is turned on because the output of the inverter INV31 is 'low', and conversely, the P MOS transistor P9 in the main decoder address input unit 20 is the inverter INV32. Is turned off because its output is 'high'.

The N MOS transistor N11 connected to the ground terminal in each address input unit 10 or 20 and the N MOS transistor N11 in the sub decoder address input unit 10 are turned on by the output of each of the inverters INV31 and INV32. -On, the N MOS transistor N11 in the main decoder address input section 20 is turned off.

Accordingly, the activity of the redundancy word line RWL1 is determined according to the output of the sub decoder address input unit 10.

On the other hand, if the fuse 31 of the input signal path selection control unit 30 is blown, the output of the inverter INV31 becomes 'high' state, and the output of the inverter INV32 becomes 'low' state. The P MOS transistor P9 and the N MOS transistor N11 in the address input unit 20 are turned on.

Therefore, the activity of the redundancy word line RWL1 is determined according to the output of the main decoder address input unit 20.

In addition, whether the input signal path selection control unit 30 cuts the fuse 31 may be determined in advance since the address cell when a defect occurs on the wafer may be checked in advance.

Since the operation of the circuit of FIG. 3B is the same as that of the circuit of FIG. 3A, description thereof is omitted.

As described above, when the repair circuit implemented by the present invention uses the main decoder dress, as described above, two word lines (33, 00) adjacent to each period in the word line repeated four times in one cycle are mentioned. , 33, 00 ‥‥) makes repairing possible impossible.

FIG. 4 is a repair circuit diagram showing another embodiment of the present invention. In FIG. 3A and FIG. 3B, 'RA23' is used as the main decoder address. In FIG. 4, it is applied to the main decoder address input unit 60. When using 'RA45' address as an address, it is a circuit to repair adjacent parts when it is grouped in one cycle of main, which is one step above the word line, which is four by one.

Since the operation process is the same as those of FIGS. 3a and 3b, description thereof is omitted.

FIG. 5 is a repair circuit diagram showing still another embodiment according to the present invention. In FIG. 5, a main stage 64 is used in one cycle than in the case where the 16 groups are grouped in one cycle using the address 'RA67' as the address applied to the main decoder address input unit 70. It is a circuit to repair adjacent parts when they are bundled in one cycle.

Since the operation of FIG. 5 is also the same as those of FIGS. 3A and 3B, description thereof will be omitted.

For reference, the repair circuits presented in the present invention and the embodiments of the present invention may be designed all within one chip according to the designer's needs, or may selectively design only the repair circuit for the most defective part. Of course.

As described in detail above, the repair circuit of the present invention is capable of repairing a defective word line generated at each period by using both a sub decoder address and a main decoder address as an address for activating a redundancy word line. In addition to improving performance, the productivity benefits are achieved by making all the chips previously wasted due to non-repairable wordlines available.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, and those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims Should be seen.

Claims (5)

A fuse box for blocking a signal designating a normal word line by disconnecting a fuse corresponding to the address when a defect occurs in any one of a plurality of cells, and a redundancy word line active signal In a two-row repair compensation circuit including a repair unit for outputting a signal, the repair of two sub-word lines adjacent to each other in a pair of n sub-word lines in accordance with a redundancy active control signal output from the fuse box. And a sub decoder address input unit receiving an address signal of a sub decoder and a symmetrical connection with the sub decoder address input unit and operated according to a redundancy active control signal output from the fuse box, thereby providing a set of n sub word lines. Belong to two different blocks Switching a path for activating a redundancy word line by selectively controlling operations of the main decoder address input unit receiving the address signal of the main decoder and the sub decoder address input unit and the main decoder address input unit for repair of two adjacent word lines. And a two-roof bridge repair compensation circuit, comprising: an input signal path selection control unit. The address input to the main decoder address input unit is a main address having a low address 23 (RA23) as an input, and the defective word line is repaired between periods constituting a group of four addresses. 2-Roo bridgely pair compensation circuit. The address input to the main decoder address input unit uses a main address of a low address 45 (RA45) as an input to repair defective word lines between cycles of 16 addresses. 2-row bridge repair compensation circuit The address input to the main decoder address input unit is a main address having a low address 67 (RA67) as an input, and the defective word line is repaired between periods constituting a group of 64 addresses. 2-Roo bridgely pair compensation circuit. The electronic device of claim 1, wherein the input signal path selection control unit comprises: a fuse for selectively activating each of the address input units, a pumping capacitor for charging and discharging a power supply voltage applied through the fuse, and a potential applied through the fuse And a N MOS transistor operated by receiving a signal output from the first inverter as a gate and inverting the first and second inverters.