KR20010108840A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- KR20010108840A KR20010108840A KR1020000029780A KR20000029780A KR20010108840A KR 20010108840 A KR20010108840 A KR 20010108840A KR 1020000029780 A KR1020000029780 A KR 1020000029780A KR 20000029780 A KR20000029780 A KR 20000029780A KR 20010108840 A KR20010108840 A KR 20010108840A
- Authority
- KR
- South Korea
- Prior art keywords
- bit line
- depositing
- film
- thickness
- polysilicon
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 238000000151 deposition Methods 0.000 claims abstract description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 238000005498 polishing Methods 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000001039 wet etching Methods 0.000 claims abstract description 5
- 238000000059 patterning Methods 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 11
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 11
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 239000002002 slurry Substances 0.000 claims description 11
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052721 tungsten Inorganic materials 0.000 claims description 11
- 239000010937 tungsten Substances 0.000 claims description 11
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims description 9
- 229910020776 SixNy Inorganic materials 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- -1 spacer nitride Chemical class 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 238000013313 FeNO test Methods 0.000 claims description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- 229910008479 TiSi2 Inorganic materials 0.000 claims description 3
- 229910008482 TiSiN Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910008814 WSi2 Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 3
- 229910017604 nitric acid Inorganic materials 0.000 claims description 3
- 239000007800 oxidant agent Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 비트라인 콘택 에치후 폴리실리콘을 증착하는 단계와, 상기 결과물 위에 비트라인 마스크를 이용하여 폴리실리콘을 패터닝하고 질화막를 증착하고 전면 에치하여 질화막 스패이서를 형성하는 단계와, 상기 결과물 위에 비트라인 절연막을 증착하고 화학적 기계적 연마하는 단계와, 상기 결과물 위에 폴리실리콘을 습식 식각하여 제거하는 단계와, 상기 결과물 위에 확산방지 금속막과 배선용 금속막을 증착하고 리세스하는 단계와, 상기 결과물 위에 마스크 질화막를 증착하고 이를 화학적 기계적 연마하여 금속 비트라인을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention relates to a method for manufacturing a semiconductor device, comprising: depositing polysilicon after bitline contact etching, patterning polysilicon using a bitline mask, depositing a nitride film, and etching the entire surface using a bitline mask to form a nitride spacer And depositing and chemically polishing the bit line insulating layer on the resultant, wet etching and removing polysilicon on the resultant, and depositing and recessing the diffusion preventing metal layer and the wiring metal layer on the resultant product. And forming a metal bit line by depositing a mask nitride film on the resultant and chemically mechanical polishing it.
Description
본 발명은 반도체 소자의 금속 비트라인 형성 방법에 관한 것으로, 특히 텅스텐의 산화를 억제함으로써 캐패시터 콘택 형성시 브리지 또는 누설 전류가 증가하는 것을 방지시킨 금속 비트라인 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal bit line in a semiconductor device, and more particularly, to a method for forming a metal bit line in which a bridge or leakage current is prevented from increasing when a capacitor contact is formed by suppressing oxidation of tungsten.
도 1a 및 도 1b는 종래의 일반적인 금속 비트라인 형성에 따른 문제점을 설명하기 위한 단면도이다.1A and 1B are cross-sectional views illustrating a problem caused by forming a conventional metal bit line.
비트라인 콘택 에치후 폴리실리콘(1) 또는 확산방지금속막(2)과 텅스텐을 증착하고 비트라인 마스크를 이용하여 패터닝 한 다음, 질화막(4)를 증착하는 도중 도 1a의 3과 같이 텅스텐이 산화되어 네가티브 슬로프를 형성시킨다. 이후 질화막 스패이서(5)를 형성하면 산화된 텅스텐 형상에 따라 전면 에치되는 경향을 보인다.After the bitline contact etch, the polysilicon 1 or the diffusion barrier metal film 2 and tungsten are deposited, patterned using a bitline mask, and the tungsten oxide is oxidized as shown in FIG. 1A during the deposition of the nitride film 4. To form a negative slope. Subsequently, when the nitride film spacer 5 is formed, the entire surface is etched according to the oxidized tungsten shape.
그 후, 도 1b와 같이 비트라인 절연막(6)을 증착하고 열처리한 다음, 화학적 기계적 연마하고 난반사 방지막을 증착하고 캐패시터 콘택 에치를 진행하면, 비트라인의 텅스텐이 드러나게 되어 비트라인과 캐패시터간에 브리지가 형성(8)됨으로써 소자 결함(fail)이 발생하거나 질화막 스패이서(3)의 두께가 얇아(도 1b의 9부분) 누설 전류가 크게 증가하는 문제점이 있었다.Subsequently, as shown in FIG. 1B, when the bit line insulating layer 6 is deposited and heat treated, chemical mechanical polishing, an antireflection film is deposited, and the capacitor contact etch proceeds, the tungsten of the bit line is exposed to expose the bridge between the bit line and the capacitor. Formation 8 causes device defects to occur or the thickness of the nitride film spacer 3 is thin (nine parts of FIG. 1B), which causes a large increase in leakage current.
따라서, 본 발명은 상기 문제점을 해결하기 위하여 이루어진 것으로, 본 발명의 목적은 비트라인과 캐패시터간의 브리지나 누설 전류가 증가되는 것을 방지시킨 반도체 소자의 제조 방법을 제공하는데 있다.Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device which prevents an increase in a bridge or leakage current between a bit line and a capacitor.
도 1a 및 도 1b는 종래의 금속 비트라인 형성 방법에 따른 문제점을 설명하기 위한 공정 단면도1A and 1B are cross-sectional views illustrating a problem in accordance with a conventional method for forming a metal bit line.
도 2a 내지 도 2d는 본 발명에 의한 금속 비트라인을 형성하기 위한 제조 공정 단면도2A to 2D are cross-sectional views of a manufacturing process for forming a metal bit line according to the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1, 10 : 폴리실리콘막 2, 14 : 확산 방지 금속막1, 10 polysilicon film 2, 14 diffusion preventing metal film
3 : 산화된 텅스텐 형상부 4, 16 : 마스크 질화막3: oxidized tungsten shape 4, 16: mask nitride film
5, 11 : 질화막 스패이서 6 : 비트라인 절연막5, 11 nitride film spacer 6 bit line insulating film
7 : 폴리실리콘 또는 금속막 플러그 15 : 텅스텐 배선막7: polysilicon or metal film plug 15: tungsten wiring film
8 : 캐패시터 플러그 형성후 플러그막이 텅스텐과 브리지된 형상부8: Shape where the plug film is bridged with tungsten after the formation of the capacitor plug
9 : 질화막 스패이서 두께가 얇아 누설 전류가 크게 증가되는 형상부9: Shape portion in which the nitride film spacer is thin and leakage current is greatly increased
13 : 폴리실리콘 제거후 형상부13: Shape after removing polysilicon
상기 목적을 달성하기 위하여, 본 발명에 의한 반도체 소자의 제조 방법은,In order to achieve the above object, the semiconductor device manufacturing method according to the present invention,
비트라인 콘택 에치후 폴리실리콘을 증착하는 단계와,Depositing polysilicon after bitline contact etch;
상기 결과물 위에 비트라인 마스크를 이용하여 폴리실리콘을 패터닝하고 질화막를 증착하고 전면 에치하여 질화막 스패이서를 형성하는 단계와,Patterning polysilicon using the bit line mask, depositing a nitride film and etching the entire surface on the resultant to form a nitride spacer;
상기 결과물 위에 비트라인 절연막을 증착하고 화학적 기계적 연마하는 단계와,Depositing and chemically polishing a bit line insulating film on the resultant;
상기 결과물 위에 폴리실리콘을 습식 식각하여 제거하는 단계와,Wet etching and removing polysilicon on the resultant;
상기 결과물 위에 확산방지 금속막과 배선용 금속막을 증착하고 리세스하는 단계와,Depositing and recessing the diffusion preventing metal film and the wiring metal film on the resultant;
상기 결과물 위에 마스크 질화막를 증착하고 이를 화학적 기계적 연마하여 금속 비트라인을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.And forming a metal bit line by depositing a mask nitride film on the resultant and chemically mechanical polishing it.
여기서, 상기 폴리실리콘은 400∼1200℃에서 2000∼8000Å 두께로 증착한 다음, 비트라인 마스크를 이용하여 패터닝한 다음, 스패이서 질화막를 저압 또는 플라즈마 증가 방법으로 SixNy, Si-rich SiN, SiON, Si-rich SiON을 400∼1200℃에서 100∼1000Å 두께로 증착하고 전면 에치하여 질화막 스패이서를 형성한 것을 특징으로 한다.Herein, the polysilicon is deposited at a thickness of 2000 to 8000 에서 at 400 to 1200 ° C., and then patterned using a bit line mask, and then a spacer nitride layer is formed by SixNy, Si-rich SiN, SiON, Si- using a low pressure or plasma increasing method. A rich SiON was deposited at 400 to 1200 DEG C with a thickness of 100 to 1000 GPa and etched to the entire surface to form a nitride film spacer.
그리과, 상기 비트라인 절연막은 BPSG, PSG, FSG, PE-TEOS, PE-SiH4, HDP PSG, HDP PSG, APL 옥사이드를 3000∼10000Å 두께로 증착한 후 선택적으로 300∼1000℃로 열처리한 다음, 50∼500nm 크기의 실리카, 세리아 또는 알루미나 계열 산화막 슬러리를 pH 8∼11로 유지하면서 폴리실리콘이 드러날때까지 화학적 기계적 평탄화하는 것을 특징으로 한다.Then, the bit line insulating film is BPSG, PSG, FSG, PE-TEOS, PE-SiH4, HDP PSG, HDP PSG, APL oxide is deposited to 3000 ~ 10000∼ thickness and selectively heat treated to 300 ~ 1000 ℃, 50 The silica, ceria or alumina-based oxide slurry having a size of ˜500 nm is maintained at a pH of 8 to 11, and chemically and mechanically planarized until polysilicon is exposed.
상기 폴리실리콘은 질산, 불산 및 초산을 혼합하여 습식 식각하여 모두 제거하는 것을 특징으로 한다.The polysilicon is characterized by removing all by wet etching by mixing nitric acid, hydrofluoric acid and acetic acid.
상기 확산 방지 금속막은 스퍼터 또는 화학 기상 증착법으로 Ti, TiN, TiAiN, TiSiN, TaN, WN, TiSi2, WSi2를 단일막으로 또는 조합하여 300∼600℃에서 50∼1000Å 두께로 증착한 다음, 배선용 금속막을 스퍼터 또는 화학 기상 증착법으로 텅스텐(W), 알루미늄(Al), 구리(Cu) 등을 300∼600℃에서 500∼5000Å 두께로 증착하는 것을 특징으로 한다.The diffusion barrier metal film is formed by sputtering or chemical vapor deposition to deposit a thickness of 50 to 1000 Pa at 300 to 600 ° C. in a single film or a combination of Ti, TiN, TiAiN, TiSiN, TaN, WN, TiSi2, and WSi2, and then form a wiring metal film. Tungsten (W), aluminum (Al), copper (Cu) and the like are deposited to a thickness of 500 to 5000 kPa at 300 to 600 ° C by sputtering or chemical vapor deposition.
상기 증착된 금속 비트라인을 비트라인 깊이 500∼2000Å 두께의 목표로 리세스 에치백하는 것을 특징으로 한다.The deposited metal bit line is recess etched back to a target having a thickness of 500 to 2000 micrometers of bit line depth.
상기 금속 비트라인은 50∼500㎚ 크기의 실리카, 세리아, 알루미나 계열 슬러리를 H2O2, FeNO3와 같은 산화제로 pH 2∼6으로 유지하면서 비트라인 절연막 상부 금속막을 모두 제거한 다음, 500∼2000Å 두께의 목표로 리세스하여 형성하는 것을 특징으로 한다.The metal bit line removes all of the upper metal film of the bit line insulating film while maintaining a silica, ceria, and alumina-based slurry having a size of 50 to 500 nm at pH 2 to 6 with an oxidizing agent such as H 2 O 2 and FeNO 3. It is formed by recessing in order to aim at thickness.
상기 마스크 질화막는 저압 또는 플라즈마 증가 방법으로 SixNy, Si-rich SiN, SiON, Si-rich(5∼20% Si 함량) SiON 을 300∼650℃에서 1000∼4000Å 두께로 증착한 다음, 비트라인 절연막 상부 질화막를 50∼500㎚ 크기의 일반적인 실리카, 세리아 또는 알루미나 계열 산화막 슬러리를 pH8∼11로 유지하면서 절연막 상부 질화막가 모두 제거될 때까지 화학적 기계적 연마하는 것을 특징으로 한다.The mask nitride film is formed by depositing SixNy, Si-rich SiN, SiON, Si-rich (5 to 20% Si) SiON at 300 to 650 ° C. at a thickness of 1000 to 4000 mm by a low pressure or plasma increasing method. Mainly maintaining the pH of the silica, ceria or alumina-based oxide slurry of the size of 50 to 500 nm at pH 8-11, and chemical mechanical polishing until all the nitride film on the insulating film is removed.
상기 마스크 질화막는 저압 또는 플라즈마 증가 방법으로 SixNy, Si-richSiN, SiON, Si-rich(5∼20% Si 함량) SiON 을 300∼650℃에서 1000∼4000Å 두께로 증착하고 증착 두께의 30∼80% 정도 에치백한 다음 50∼500㎚ 크기의 실리카, 세리아 또는 알루미나 계열 산화막 슬러리를 pH 8∼11로 유지하면서 절연막 상부 질화막가 모두 제거될 때까지 화학적 기계적 연마하는 것을 특징으로 한다.The mask nitride film is formed by depositing SixNy, Si-richSiN, SiON, Si-rich (5 to 20% Si) SiON at 1000 to 4000 mm thick at 300 to 650 ° C. by a low pressure or plasma increasing method, and about 30 to 80% of the deposition thickness. After etching, the silica, ceria, or alumina-based oxide slurry having a size of 50 to 500 nm is maintained at a pH of 8 to 11, and is chemically mechanically polished until all of the nitride film on the insulating film is removed.
이하, 본 발명에 따라 금속 비트라인 형성 공정에서 텅스텐 산화를 근본적으로 방지할 수 있는 방법을 첨부 도면을 참조하여 설명하고자 한다.Hereinafter, a method for fundamentally preventing tungsten oxidation in the metal bit line forming process according to the present invention will be described with reference to the accompanying drawings.
또, 실시예를 설명하기 위한 모든 도면에서 동일한 기능을 갖는 것은 동일한 부호를 사용하고 그 반복적인 설명은 생략한다.In addition, in all the drawings for demonstrating an embodiment, the thing with the same function uses the same code | symbol, and the repeated description is abbreviate | omitted.
도 2a 내지 도 2d는 본 발명에 의한 금속 비트라인을 형성하기 위한 제조 공정 단면도이다.2A to 2D are cross-sectional views of a manufacturing process for forming a metal bit line according to the present invention.
비트라인 콘택 에치후 도핑실리콘, 단결정실리콘 또는 폴리실리콘(10)을 400∼1200℃에서 2000∼8000Å 두께로 증착한다. 그 후, 비트라인 마스크를 이용하여 패터닝한 다음, 스패이서 질화막를 저압(Low Pressure) 방법으로 SixNy, Si-rich SiN, SiON, Si-rich SiON을 100∼1000Å 두께로 증착하여 질화막 스패이서(11)를 형성한다.After the bitline contact etch, doped silicon, single crystal silicon or polysilicon 10 is deposited at 400-1200 ° C. to a thickness of 2000-8000 mm 3. Subsequently, after the patterning is performed using a bit line mask, the spacer nitride is deposited using a low pressure method to deposit a thickness of SixNy, Si-rich SiN, SiON, and Si-rich SiON in a thickness of 100 to 1000 GPa. To form.
비트라인 절연막(12)으로 BPSG, PSG, FSG, PE-TEOS, PE-SiH4, HDP USG, HDP PSG, APL 옥사이드를 3000∼10000Å 두께로 증착하고, 선택적으로 300∼1000℃로 열처리한 다음, 50∼500㎚ 크기의 일반적인 실리카, 세리아, 알루미나 계열 산화막 슬러리를 pH 2∼6으로 유지하면서 폴리실리콘이 드러날 때까지 화학적 기계적 평탄화하고, 폴리실리콘(11)을 질산, 불산 및 초산을 혼합하여 습식식각하여 제거한다(도 2a 및 도 2b).BPSG, PSG, FSG, PE-TEOS, PE-SiH4, HDP USG, HDP PSG, and APL oxide were deposited to a thickness of 3000 to 10000 kPa with a bit line insulating film 12, and optionally heat-treated to 300 to 1000 ° C., and then 50 While maintaining a pH of 2 to 6, a general silica, ceria, and alumina-based oxide slurry having a size of -500 nm is chemically mechanically planarized until polysilicon is exposed, and the polysilicon 11 is wet-etched by mixing nitric acid, hydrofluoric acid, and acetic acid. Remove (FIGS. 2A and 2B).
그 후, 확산 방지 금속막(14)을 스퍼터 또는 화학 기상 증착법으로 Ti, TiN, TiAiN, TiSiN, TaN, WN, TiSi2, WSi2를 단일막으로 또는 조합하여 300∼600℃에서 50∼1000Å 두께로 증착한다.Subsequently, the diffusion barrier metal film 14 is deposited to a thickness of 50 to 1000 Pa at 300 to 600 DEG C or a combination of Ti, TiN, TiAiN, TiSiN, TaN, WN, TiSi2, WSi2 as a single film or a combination by sputtering or chemical vapor deposition. do.
그리고, 상기 확산 방지 금속막(14)위에 배선용 금속막(15)을 스퍼터 또는 화학 기상 증착법으로 텅스텐(W), 알루미늄(Al), 구리(Cu) 등을 300∼600℃에서 500∼5000Å 두께로 증착한다. 그 후, 도 2c와 도 2d와 같이 500∼2000Å 두께의 목표로 리세스 에치백하여 금속 배선을 형성하거나 또는 50∼500㎚ 크기의 실리카, 세리아, 알루미나 계열 슬러리를 H2O2, FeNO3와 같은 산화제로 pH 2∼6으로 유지하면서 비트라인 절연막 상부 금속막을 모두 제거한다. 그 후, 500∼2000Å 두께의 목표로 리세스함으로써 금속 배선 비트라인을 형성한다.The tungsten (W), aluminum (Al), copper (Cu), and the like are deposited on the diffusion preventing metal film 14 by sputtering or chemical vapor deposition at a thickness of 500 to 5000 kPa at 300 to 600 ° C. Deposit. Thereafter, as shown in FIGS. 2C and 2D, the recesses are etched back to a target thickness of 500 to 2000 microns to form metal wirings, or silica, ceria, and alumina based slurries having a size of 50 to 500 nm may be mixed with H 2 O 2 and FeNO 3 . All metal films on the bit line insulating film are removed while maintaining the pH at 2 to 6 with the same oxidizing agent. Thereafter, the metal wiring bit lines are formed by recessing them to a target of 500 to 2000 탆 thickness.
그리고, 상기 배선용 금속막(15)위에 마스크 질화막(16)를 스텝 커버리지 특성이 좋은 저압 또는 플라즈마 증가 방법으로 SixNy, Si-rich SiN, SiON, Si-rich(5∼20% Si 함량) SiON 을 300∼650℃에서 1000∼4000Å 두께로 증착한 다음, 50∼500㎚ 크기의 일반적인 실리카, 세리아 또는 알루미나 계열 산화막 슬러리를 pH8∼11로 유지하면서 절연막 상부 마스크 질화막(16)를 직접 연마하거나, 절연막 상부 마스크 질화막(16)를 30∼80% 정도 에치백한 다음, 화학적 기계적 연마하면 금속 비트라인과 캐패시터간의 브리지 형성 또는 누설 전류 증가를 근본적으로 방지할 수 있어 안정된 캐패시터 플러그 형상(17)을 형성할 수 있다.Then, on the wiring metal film 15, SixNy, Si-rich SiN, SiON, Si-rich (5 to 20% Si content) SiON is added to the mask nitride film 16 by low pressure or plasma increasing method having good step coverage characteristics. After depositing at a thickness of 1000 to 4000 Pa at ˜650 ° C., the upper surface of the insulating film upper mask nitride film 16 is directly polished or the upper surface of the insulating film mask is maintained while maintaining a general silica, ceria, or alumina oxide slurry having a size of 50 to 500 nm at a pH of 8 to 11. By etching back the nitride film 16 by about 30 to 80% and then chemically mechanical polishing, it is possible to fundamentally prevent bridge formation between the metal bit line and the capacitor or increase leakage current, thereby forming a stable capacitor plug shape 17. .
이상에서 설명한 바와 같이, 본 발명에 의한 반도체 소자의 금속 비트라인 형성 방법에 의하면, 비트라인 콘택 에치후 폴리실리콘 비트라인을 형성하고 비트라인 절연막 평탄화후 드러난 폴리실리콘을 제거하고 비어있는 비트라인 배선에 확산방지 금속막과 배선용 금속막을 증착하고 리세스한 다음, 마스크 질화막를 증착하고 연마하여 비트라인을 형성함으로써, 비트라인과 캐패시터간 브리지나 누설 전류 증가를 방지시킬 수 있는 효과가 있다.As described above, according to the method of forming a metal bit line of a semiconductor device according to the present invention, a polysilicon bit line is formed after bit line contact etching, and polysilicon exposed after planarization of the bit line insulating layer is removed, and the empty bit line wiring is removed. By depositing and recessing the diffusion preventing metal film and the wiring metal film and then depositing and polishing the mask nitride film to form a bit line, there is an effect of preventing an increase in a bridge or leakage current between the bit line and the capacitor.
아울러 본 발명의 바람직한 실시예들은 예시의 목적을 위해 개시된 것이며, 당업자라면 본 발명의 사상과 범위 안에서 다양한 수정, 변경, 부가등이 가능할 것이며, 이러한 수정 변경등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000029780A KR100680937B1 (en) | 2000-05-31 | 2000-05-31 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000029780A KR100680937B1 (en) | 2000-05-31 | 2000-05-31 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010108840A true KR20010108840A (en) | 2001-12-08 |
| KR100680937B1 KR100680937B1 (en) | 2007-02-08 |
Family
ID=41612257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000029780A KR100680937B1 (en) | 2000-05-31 | 2000-05-31 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100680937B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100451986B1 (en) * | 2001-12-31 | 2004-10-08 | 주식회사 하이닉스반도체 | Method for forming strage node contact plug of semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100224788B1 (en) * | 1996-12-31 | 1999-10-15 | 김영환 | Process for fabricating semicondcutor device |
| KR20000020470A (en) * | 1998-09-21 | 2000-04-15 | 김영환 | Method for forming bit lines of semiconductor device |
-
2000
- 2000-05-31 KR KR1020000029780A patent/KR100680937B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100451986B1 (en) * | 2001-12-31 | 2004-10-08 | 주식회사 하이닉스반도체 | Method for forming strage node contact plug of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100680937B1 (en) | 2007-02-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6815331B2 (en) | Method for forming metal wiring layer of semiconductor device | |
| US7332427B2 (en) | Method of forming an interconnection line in a semiconductor device | |
| KR20040008942A (en) | A method for forming a semiconductor device | |
| KR100680937B1 (en) | Method for manufacturing semiconductor device | |
| JPH10116904A (en) | Manufacture of semiconductor device | |
| KR100481831B1 (en) | Capacitor Manufacturing Method for Semiconductor Devices | |
| US20030228764A1 (en) | Innovative method to build a high precision analog capacitor with low voltage coefficient and hysteresis | |
| US20030003712A1 (en) | Methods for fabricating a semiconductor device | |
| KR100582370B1 (en) | Method for fabricating gate electrode using damascene process | |
| KR100609980B1 (en) | Method for preventing overetch of PMD layer | |
| KR100639196B1 (en) | Method for manufacturing semiconductor device | |
| KR100359166B1 (en) | Method for forming a contact plug in semiconductor device | |
| KR100680938B1 (en) | Method of making metal word line and bit line in semiconductor device | |
| KR100492897B1 (en) | Method for fabricating polysilicon plug using polysilicon slurry | |
| JP2001110769A (en) | Manufacturing method of semiconductor device, and semiconductor device | |
| KR100370160B1 (en) | method for forming W plug of semiconductor device | |
| KR20010005107A (en) | Method for forming plug of semiconductor device | |
| KR100545699B1 (en) | Method for forming plug for capacitor contact of semiconductor device | |
| KR20010063497A (en) | Method for forming contact plug of semiconductor device | |
| KR100680460B1 (en) | Method of forming a metal wiring in a semiconductor device | |
| KR100849773B1 (en) | Method for manufacturing semiconductor device | |
| KR100935189B1 (en) | Method for planarization intermediate layer of semicoductor device | |
| KR20010061490A (en) | Method for forming capacitor bottom electrode of semiconductor device capable of preventing loss of bottom electrode caused with degradation of adhesion strength | |
| KR20010058987A (en) | Method for forming metal pattern of semiconductor device | |
| KR20020002538A (en) | Method for forming contact plug in semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110126 Year of fee payment: 5 |
|
| LAPS | Lapse due to unpaid annual fee |