KR20010097961A - Method of Fabricating Thin Film Transistor - Google Patents
Method of Fabricating Thin Film Transistor Download PDFInfo
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- KR20010097961A KR20010097961A KR1020000022491A KR20000022491A KR20010097961A KR 20010097961 A KR20010097961 A KR 20010097961A KR 1020000022491 A KR1020000022491 A KR 1020000022491A KR 20000022491 A KR20000022491 A KR 20000022491A KR 20010097961 A KR20010097961 A KR 20010097961A
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- gate electrode
- ohmic contact
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- metal layer
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- 239000010409 thin film Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 46
- 238000002161 passivation Methods 0.000 claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000004380 ashing Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 8
- 239000000203 mixture Substances 0.000 claims abstract description 4
- 238000001312 dry etching Methods 0.000 claims description 27
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052750 molybdenum Inorganic materials 0.000 claims description 5
- 239000011733 molybdenum Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- BCCOBQSFUDVTJQ-UHFFFAOYSA-N octafluorocyclobutane Chemical compound FC1(F)C(F)(F)C(F)(F)C1(F)F BCCOBQSFUDVTJQ-UHFFFAOYSA-N 0.000 description 4
- 235000019407 octafluorocyclobutane Nutrition 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910001182 Mo alloy Inorganic materials 0.000 description 3
- -1 acryl Chemical group 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 241001239379 Calophysus macropterus Species 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910016024 MoTa Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 150000002894 organic compounds Chemical class 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Thin Film Transistor (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 박막트랜지스터의 제조방법에 관한 것으로서 투명기판 상의 소정 부분에 게이트전극 및 게이트라인을 형성하는 공정과, 상기 투명기판 상에 상기 게이트전극 및 게이트라인을 덮도록 게이트절연막, 활성층 및 오믹접촉층을 순차적으로 형성하는 공정과, 상기 오믹접촉층 상에 오믹금속층을 형성하고 상기 오믹금속층을 패터닝하여 상기 게이트라인과 수직되는 데이터라인과 상기 게이트전극과 대응하는 부분에 소오스 및 드레인전극을 형성하면서 상기 오믹접촉층도 상기 활성층이 노출되도록 패터닝하는 공정과, 상기 활성층 상에 상기 소오스 및 드레인전극과 오믹금속층을 덮도록 패시베이션층을 형성하고 상기 패시베이션층 상의 상기 데이터라인을 포함하는 상기 소오스 및 드레인전극과 대응하는 부분에 포토레지스트 패턴을 형성하는 공정과, 상기 포토레지스트 패턴을 마스크로 사용하여 상기 패시베이션층, 오믹금속층, 오믹접촉층 및 활성층의 노출된 부분을 순차적으로 식각하고 SF6+ O2의 혼합 가스로 애싱(ashing) 처리하는 공정과, 상기 포토레지스트 패턴을 제거하는 공정을 구비한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, the method comprising: forming a gate electrode and a gate line in a predetermined portion on a transparent substrate; and a gate insulating layer, an active layer, and an ohmic contact layer to cover the gate electrode and the gate line on the transparent substrate. Forming an ohmic metal layer on the ohmic contact layer and patterning the ohmic metal layer to form a data line perpendicular to the gate line and a source and drain electrode at a portion corresponding to the gate electrode. Patterning an ohmic contact layer so that the active layer is exposed; forming a passivation layer on the active layer to cover the source and drain electrodes and the ohmic metal layer; Form a photoresist pattern on the corresponding part The process and the steps of using the photoresist pattern as a mask, etching the exposed portions of the passivation layer, the ohmic metal layer, an ohmic contact layer and the active layer in order to handle the ashing (ashing) a gas mixture of SF 6 + O 2 And removing the photoresist pattern.
따라서, Cl 성분이 잔류하지 않으므로 H2O의 H2성분과의 반응으로 인한 HCl 용액이 생성되지 않아 제 1 금속층이 노출되는 것을 방지하므로 게이트전극의 노출된 부분이 손상으로 판정되어 되는 것을 방지하여 수율을 향상시킬 수 있다.Therefore, since Cl component does not remain, HCl solution is not generated due to the reaction of H 2 O with H 2 component, thereby preventing the first metal layer from being exposed, thereby preventing the exposed portion of the gate electrode from being judged as damaged. Yield can be improved.
Description
본 발명은 박막트랜지스터의 제조방법에 관한 것으로서, 특히, 4개의 마스크를 사용하여 공정을 감소시킬 수 있는 박막트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a thin film transistor, and more particularly, to a method of manufacturing a thin film transistor that can reduce the process using four masks.
액정표시장치는 게이트전극, 게이트절연막, 활성층, 오믹접촉층, 소오스 및 드레인전극으로 구성된 박막트랜지스터(Thin Film Transistor)로 이루어진 스위칭 소자와 화소(pixel) 전극이 형성된 하판과 칼라필터가 형성된 상판 사이에 주입된 액정으로 이루어진다.The liquid crystal display device includes a switching element composed of a thin film transistor including a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source and a drain electrode, a lower plate on which a pixel electrode is formed, and an upper plate on which a color filter is formed. It consists of the injected liquid crystal.
상기에서 통상적인 방법에 의해 하판을 제조할 때 게이트전극, 활성층 및 오믹접촉층, 소오스 및 드레인전극, 패시베이션층 내의 접촉홀과 화소전극을 패터닝하기 위해 5개의 마스크가 필요하다. 그러므로, 마스크 수를 감소시켜 4개의 마스크만으로 공정을 진행하여 하판을 형성하기 위한 연구가 활발히 진행되고 있다.When manufacturing the lower plate by the conventional method described above, five masks are required to pattern the contact holes and pixel electrodes in the gate electrode, the active layer and the ohmic contact layer, the source and drain electrodes, and the passivation layer. Therefore, research is being actively conducted to form a lower plate by reducing the number of masks and proceeding with only four masks.
도 1a 내지 도1e는 종래 기술에 따른 박막트랜지스터의 제조 공정도이다.1A to 1E are manufacturing process diagrams of a thin film transistor according to the prior art.
도 1a를 참조하면, 투명기판(11) 상에 스퍼터링(sputtering) 등의 방법으로 금속박막을 형성하고 습식 방법을 포함하는 포토리쏘그래피 방법으로 투명기판(11)의 소정 부분에 잔류하도록 패터닝하여 게이트전극(13) 및 게이트라인(15)을 형성한다. 이 때, 금속박막을 2층으로 형성하는 데, 하부층에 알루미늄(Al)과 네오딤(Nd)의 합금을 2000Å 정도의 두께로 증착하고, 그리고, 상부층에 몰리브덴(Mo)을 500Å 정도의 두께로 증착하여 형성한다.Referring to FIG. 1A, a metal thin film is formed on a transparent substrate 11 by sputtering or the like, and is patterned to remain in a predetermined portion of the transparent substrate 11 by a photolithography method including a wet method. The electrode 13 and the gate line 15 are formed. At this time, the metal thin film is formed into two layers, an alloy of aluminum (Al) and neodym (Nd) is deposited to a thickness of about 2000 kPa on the lower layer, and molybdenum (Mo) to about 500 kPa on the upper layer. By vapor deposition.
도 1b를 참조하면, 투명기판(11) 상에 게이트전극(13) 및 게이트라인(15)을 덮도록 게이트절연막(17), 활성층(19) 및 오믹접촉층(21)을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 순차적으로 형성한다. 상기에서 게이트절연막(17)은 산화실리콘 또는 질화실리콘 등의 절연물질을 증착하여 형성하고, 활성층(19)은 불순물이 도핑되지 않은 비정질실리콘 또는 다결정실리콘으로 형성된다. 또한, 오믹접촉층(21)은 N형 또는 P형의 불순물이 고농도로 도핑된 비정질실리콘 또는 다결정실리콘으로 형성된다.Referring to FIG. 1B, the gate insulating layer 17, the active layer 19, and the ohmic contact layer 21 are chemically vapor deposited on the transparent substrate 11 to cover the gate electrode 13 and the gate line 15. Vapor Deposition: Formed sequentially by the following CVD method). The gate insulating layer 17 is formed by depositing an insulating material such as silicon oxide or silicon nitride, and the active layer 19 is formed of amorphous silicon or polycrystalline silicon that is not doped with impurities. In addition, the ohmic contact layer 21 is formed of amorphous silicon or polycrystalline silicon doped with N-type or P-type impurities at a high concentration.
도 1c를 참조하면, 오믹접촉층(21) 상에 크롬(Cr), 몰리브덴(Mo), 티타늄(Ti) 또는 탄탈륨(Ta) 등의 금속이나, MoW, MoTa 또는 MoNb 등의 몰리브덴 합금(Mo alloy)을 CVD 방법 또는 스퍼터링(sputtering) 방법으로 증착하여 오믹금속층(25)을 형성한다. 상기에서 오믹금속층(25)은 오믹접촉층(21)과 오믹 접촉을 이룬다.Referring to FIG. 1C, a metal such as chromium (Cr), molybdenum (Mo), titanium (Ti) or tantalum (Ta), or a molybdenum alloy such as MoW, MoTa, or MoNb may be formed on the ohmic contact layer 21. ) Is deposited by a CVD method or a sputtering method to form an ohmic metal layer 25. The ohmic metal layer 25 is in ohmic contact with the ohmic contact layer 21.
그리고, 오믹금속층(25)과 오믹접촉층(21)을 활성층(19)이 노출되도록 포토리쏘그래피 방법으로 순차적으로 패터닝한다. 이 때, 오믹금속층(25)은 패터닝되어 게이트라인(15)과 수직되는 데이터라인(도시되지 않음)이 형성되며 게이트전극(13)과 대응하는 부분에 소오스 및 드레인전극(23)(24)이 형성된다. 또한, 오믹금속층(25)은 게이트라인(15)과 대응하는 부분 상에도 패터닝되어 제거되지 않고 잔류하게 된다.The ohmic metal layer 25 and the ohmic contact layer 21 are sequentially patterned by a photolithography method so that the active layer 19 is exposed. At this time, the ohmic metal layer 25 is patterned to form a data line (not shown) perpendicular to the gate line 15, and source and drain electrodes 23 and 24 are formed at portions corresponding to the gate electrode 13. Is formed. In addition, the ohmic metal layer 25 is patterned on the portion corresponding to the gate line 15 to remain without being removed.
도 1d를 참조하면, 활성층(19) 상에 소오스 및 드레인전극(23)(24)과 오믹금속층(25)을 덮도록 질화실리콘 또는 산화실리콘 등의 무기절연물질을 증착하여 패시베이션층(27)을 형성한다. 상기에서 패시베이션층(27)을 아크릴(acryl)계 유기화합물, BCB(benzocyclobutene) 또는 PFCB(perfluorocyclobutane) 등의 유전 상수가 작은 유기 절연물로 형성할 수도 있다.Referring to FIG. 1D, an inorganic insulating material such as silicon nitride or silicon oxide is deposited on the active layer 19 to cover the source and drain electrodes 23 and 24 and the ohmic metal layer 25 to form the passivation layer 27. Form. The passivation layer 27 may be formed of an organic insulator having a low dielectric constant such as an acryl-based organic compound, benzocyclobutene (BCB), or perfluorocyclobutane (PFCB).
패시베이션층(27) 상에 포토레지스트를 도포한 후 데이터라인(도시되지 않음)을 포함하는 소오스 및 드레인전극(23)(24)과 대응하는 부분에만 잔류하도록 패터닝하여 포토레지스트 패턴(29)을 형성한다. 이 때, 포토레지스트 패턴(29)이 게이트라인(15)과 대응하는 부분에 잔류되지 않도록 한다.After the photoresist is applied on the passivation layer 27, the photoresist pattern 29 is formed by patterning the photoresist to remain only at portions corresponding to the source and drain electrodes 23 and 24 including data lines (not shown). do. At this time, the photoresist pattern 29 may not remain in the portion corresponding to the gate line 15.
도 1e를 참조하면, 포토레지스트 패턴(29)을 마스크로 사용하여 패시베이션층(27), 오믹금속층(25), 오믹접촉층(21) 및 활성층(19)의 노출된 부분을 순차적으로 식각한다. 상기에서 패시베이션층(27), 오믹금속층(25), 오믹접촉층(21) 및 활성층(19)을 3 단계의 건식 식각에 의해 순차적으로 패터닝한다. 그리고, 포토레지스트 패턴(29)을 스트립(strip)하여 제거한다.Referring to FIG. 1E, the exposed portions of the passivation layer 27, the ohmic metal layer 25, the ohmic contact layer 21, and the active layer 19 are sequentially etched using the photoresist pattern 29 as a mask. The passivation layer 27, the ohmic metal layer 25, the ohmic contact layer 21, and the active layer 19 are sequentially patterned by three steps of dry etching. The photoresist pattern 29 is stripped and removed.
상기에서 1 단계 건식 식각은 SF6+ He의 혼합 가스로 패시베이션층(27)을, 2 단계 건식 식각은 SF6+ He + O2의 혼합 가스로 오믹금속층(25)을, 3 단계 건식 식각은 SF6+ He + HCl의 혼합 가스로 오믹접촉층(21) 및 활성층(19)을 순착적으로 식각하여 게이트라인(15)과 대응하는 부분의 게이트절연막(17)을 노출시킨다. 이 때, 게이트전극(13)과 대응하는 부분은 1 단계 건식 식각시 SF6+ He의 혼합 가스에 의해 패시베이션층(27) 뿐만 아니라 오믹접촉층(21) 및 활성층(19)도 식각되며, 2 단계 건식 식각시 SF6+ He + O2의 혼합 가스에 의해 게이트절연막(17)이 식각되어 게이트전극(13)이 노출된다. 그러므로, 게이트전극(13)의 노출된 부분은 3 단계 건식 식각시 SF6+ He + HCl의 혼합 가스와 접촉된다. 상기에서 3 단계 건식 식각시 사용되는 SF6+ He + HCl의 혼합 가스에서 HCl도 가스 상태이므로 게이트전극(13)의 노출된 부분이 식각에 의한 손상을 받지 않게 된다.The first step dry etching is the passivation layer 27 with a mixed gas of SF 6 + He, the second step dry etching is an ohmic metal layer 25 with a mixed gas of SF 6 + He + O 2 , the third step dry etching is The ohmic contact layer 21 and the active layer 19 are sequentially etched using a mixed gas of SF 6 + He + HCl to expose the gate insulating layer 17 corresponding to the gate line 15. At this time, the portion corresponding to the gate electrode 13 is etched not only the passivation layer 27 but also the ohmic contact layer 21 and the active layer 19 by the mixed gas of SF 6 + He during the one-step dry etching. During the step dry etching, the gate insulating layer 17 is etched by the mixed gas of SF 6 + He + O 2 to expose the gate electrode 13. Therefore, the exposed portion of the gate electrode 13 is in contact with the mixed gas of SF 6 + He + HCl during the three-step dry etching. In the mixed gas of SF 6 + He + HCl used in the three-step dry etching, HCl is also in a gas state, so that the exposed portion of the gate electrode 13 is not damaged by etching.
상술한 종래 기술에 따른 박막트랜지스터의 제조 방법은 2 단계 건식 식각에 의해 노출된 게이트전극에 3 단계 건식 식각시 SF6+ He + HCl 중 Cl 성분이 잔류하게 되는 데, 이 Cl 성분은 포토레지스트 패턴을 제거할 때 사용되는 H2O의 H2성분과 반응하여 HCl 용액을 생성한다. 상기에서 생성된 HCl 용액은 게이트전극의 노출된 부분을 식각하여 제 1 금속층이 손상시켜 패턴 검사시 불량으로 검출하여 수율을 저하시키는 문제점이 있었다.According to the above-described method of manufacturing a thin film transistor, a Cl component of SF 6 + He + HCl remains in the gate electrode exposed by the two-step dry etching during the three-step dry etching, which is a photoresist pattern. reaction with H 2 component of the H 2 O is used to remove the HCl to produce a solution. The HCl solution generated above has a problem in that the exposed portion of the gate electrode is etched to damage the first metal layer, thereby detecting the defect as a defect during pattern inspection, thereby lowering the yield.
따라서, 본 발명의 목적은 게이트전극의 제 2 금속층이 식각되는 것을 방지하여 제 1 금속층의 손상으로 인한 수율 저하를 방지할 수 있는 박막트랜지스터의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor which can prevent the second metal layer of the gate electrode from being etched, thereby preventing a decrease in yield due to damage of the first metal layer.
도 1a 내지 도 1e는 종래 기술에 따른 박막트랜지스터의 제조 공정도1a to 1e is a manufacturing process diagram of a thin film transistor according to the prior art
도 2a 내지 도 2f는 본 발명에 따른 박막트랜지스터의 제조 공정도2a to 2f is a manufacturing process diagram of a thin film transistor according to the present invention
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
31 : 투명기판 33 : 게이트전극31: transparent substrate 33: gate electrode
35 : 게이트라인 37 : 게이트절연막35 gate line 37 gate insulating film
39 : 활성층 41 : 오믹접촉층39: active layer 41: ohmic contact layer
43, 44 : 소오스 및 드레인전극43, 44 source and drain electrodes
45 : 금속층45: metal layer
47 : 패시베이션층 49 : 포토레지스트 패턴47: passivation layer 49: photoresist pattern
상기 목적을 달성하기 위한 본 발명에 따른 박막트랜지스터의 제조방법은 투명기판 상의 소정 부분에 게이트전극 및 게이트라인을 형성하는 공정과, 상기 투명기판 상에 상기 게이트전극 및 게이트라인을 덮도록 게이트절연막, 활성층 및 오믹접촉층을 순차적으로 형성하는 공정과, 상기 오믹접촉층 상에 오믹금속층을 형성하고 상기 오믹금속층을 패터닝하여 상기 게이트라인과 수직되는 데이터라인과 상기게이트전극과 대응하는 부분에 소오스 및 드레인전극을 형성하면서 상기 오믹접촉층도 상기 활성층이 노출되도록 패터닝하는 공정과, 상기 활성층 상에 상기 소오스 및 드레인전극과 오믹금속층을 덮도록 패시베이션층을 형성하고 상기 패시베이션층 상의 상기 데이터라인을 포함하는 상기 소오스 및 드레인전극과 대응하는 부분에 포토레지스트 패턴을 형성하는 공정과, 상기 포토레지스트 패턴을 마스크로 사용하여 상기 패시베이션층, 오믹금속층, 오믹접촉층 및 활성층의 노출된 부분을 순차적으로 식각하고 SF6+ O2의 혼합 가스로 애싱(ashing) 처리하는 공정과, 상기 포토레지스트 패턴을 제거하는 공정을 구비한다.A method of manufacturing a thin film transistor according to the present invention for achieving the above object comprises the steps of forming a gate electrode and a gate line on a predetermined portion on the transparent substrate, a gate insulating film to cover the gate electrode and the gate line on the transparent substrate, Sequentially forming an active layer and an ohmic contact layer, and forming an ohmic metal layer on the ohmic contact layer and patterning the ohmic metal layer to source and drain the data line perpendicular to the gate line and a portion corresponding to the gate electrode. Patterning the ohmic contact layer to expose the active layer while forming an electrode, and forming a passivation layer on the active layer to cover the source and drain electrodes and the ohmic metal layer, and including the data line on the passivation layer. Photoresist at the portion corresponding to the source and drain electrodes Bit by using a step of forming a pattern, the photoresist pattern as a mask, etching the exposed portions of the passivation layer, the ohmic metal layer, an ohmic contact layer and the active layer in order to ashing in a gas mixture of SF 6 + O 2 (ashing ) And a step of removing the photoresist pattern.
상기 목적 외에 본 발명의 다른 목적 및 특징들은 첨부한 도면들을 첨부한 도면들을 참조한 실시예에 대한 설명을 통하여 명백하게 드러나게 될 것이다.Other objects and features of the present invention in addition to the above objects will become apparent from the following description of the embodiments with reference to the accompanying drawings.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도2f는 본 발명에 따른 박막트랜지스터의 제조 공정도이다.2A to 2F are manufacturing process diagrams of the thin film transistor according to the present invention.
도 2a를 참조하면, 투명기판(41) 상에 스퍼터링(sputtering) 등의 방법으로 금속박막을 형성하고 습식 방법을 포함하는 포토리쏘그래피 방법으로 투명기판(31)의 소정 부분에 잔류하도록 패터닝하여 게이트전극(33) 및 게이트라인(35)을 형성한다. 이 때, 금속박막을 2층으로 형성하는 데, 하부층에 알루미늄(Al)과 네오딤(Nd)의 합금을 1500∼2500Å 정도의 두께로 증착하고, 그리고, 상부층에 몰리브덴(Mo)을 500∼700Å 정도의 두께로 증착하여 형성한다.Referring to FIG. 2A, a metal thin film is formed on the transparent substrate 41 by sputtering or the like, and patterned so as to remain on a predetermined portion of the transparent substrate 31 by a photolithography method including a wet method. The electrode 33 and the gate line 35 are formed. At this time, the metal thin film is formed into two layers. An alloy of aluminum (Al) and neodym (Nd) is deposited to a thickness of 1500 to 2500 kPa in the lower layer, and the molybdenum (Mo) is 500 to 700 kPa in the upper layer. It is formed by depositing to a thickness of about.
도 2b를 참조하면, 투명기판(31) 상에 게이트전극(33) 및 게이트라인(35)을 덮도록 게이트절연막(37), 활성층(39) 및 오믹접촉층(41)을 CVD 방법으로 순차적으로 형성한다. 상기에서 게이트절연막(37)은 산화실리콘 또는 질화실리콘 등의 절연물질을 증착하여 형성하고, 활성층(39)은 불순물이 도핑되지 않은 비정질실리콘 또는 다결정실리콘으로 형성된다. 또한, 오믹접촉층(41)은 N형 또는 P형의 불순물이 고농도로 도핑된 비정질실리콘 또는 다결정실리콘으로 형성된다.Referring to FIG. 2B, the gate insulating layer 37, the active layer 39, and the ohmic contact layer 41 are sequentially covered by the CVD method so as to cover the gate electrode 33 and the gate line 35 on the transparent substrate 31. Form. The gate insulating layer 37 is formed by depositing an insulating material such as silicon oxide or silicon nitride, and the active layer 39 is formed of amorphous silicon or polycrystalline silicon that is not doped with impurities. In addition, the ohmic contact layer 41 is formed of amorphous silicon or polycrystalline silicon doped with N-type or P-type impurities at a high concentration.
도 2c를 참조하면, 오믹접촉층(41) 상에 크롬(Cr), 몰리브덴(Mo), 티타늄 또는 탄탈륨 등의 금속이나, MoW, MoTa 또는 MoNb 등의 몰리브덴 합금(Mo alloy)을 CVD 방법 또는 스퍼터링(sputtering) 방법으로 증착하여 오믹금속층(45)을 형성한다. 상기에서 오믹금속층(45)은 오믹접촉층(41)과 오믹 접촉을 이룬다.Referring to FIG. 2C, a metal such as chromium (Cr), molybdenum (Mo), titanium, or tantalum, or a molybdenum alloy (Mo alloy) such as MoW, MoTa, or MoNb is CVD or sputtered on the ohmic contact layer 41. The ohmic metal layer 45 is formed by depositing by a sputtering method. The ohmic metal layer 45 is in ohmic contact with the ohmic contact layer 41.
그리고, 오믹금속층(45)과 오믹접촉층(41)을 활성층(39)이 노출되도록 포토리쏘그래피 방법으로 순차적으로 패터닝한다. 이 때, 오믹금속층(45)은 패터닝되어 게이트라인(35)과 수직되는 데이터라인(도시되지 않음)이 형성되며 게이트전극(33)과 대응하는 부분에 소오스 및 드레인전극(43)(44)이 형성된다. 또한, 오믹금속층(45)은 게이트라인(35)과 대응하는 부분 상에도 패터닝되어 제거되지 않고 잔류하게 된다.The ohmic metal layer 45 and the ohmic contact layer 41 are sequentially patterned by a photolithography method so that the active layer 39 is exposed. At this time, the ohmic metal layer 45 is patterned to form a data line (not shown) perpendicular to the gate line 35, and source and drain electrodes 43 and 44 are formed at portions corresponding to the gate electrode 33. Is formed. In addition, the ohmic metal layer 45 is patterned on the portion corresponding to the gate line 35 to remain without being removed.
도 2d를 참조하면, 활성층(39) 상에 소오스 및 드레인전극(43)(44)과 오믹금속층(45)을 덮도록 질화실리콘 또는 산화실리콘 등의 무기절연물질을 증착하여 패시베이션층(47)을 형성한다. 상기에서 패시베이션층(47)을 아크릴(acryl)계 유기화합물, BCB(benzocyclobutene) 또는 PFCB(perfluorocyclobutane) 등의 유전 상수가 작은 유기 절연물로 형성할 수도 있다.Referring to FIG. 2D, the passivation layer 47 is formed by depositing an inorganic insulating material such as silicon nitride or silicon oxide on the active layer 39 to cover the source and drain electrodes 43 and 44 and the ohmic metal layer 45. Form. The passivation layer 47 may be formed of an organic insulator having a low dielectric constant such as an acryl-based organic compound, benzocyclobutene (BCB), or perfluorocyclobutane (PFCB).
패시베이션층(47) 상에 포토레지스트를 도포한 후 데이터라인(도시되지 않음)을 포함하는 소오스 및 드레인전극(43)(44)과 대응하는 부분에만 잔류하도록 패터닝하여 포토레지스트 패턴(49)을 형성한다. 이 때, 포토레지스트 패턴(49)이 게이트라인(45)과 대응하는 부분에 잔류되지 않도록 한다.After the photoresist is applied on the passivation layer 47, the photoresist pattern 49 is formed by patterning the photoresist to remain only at portions corresponding to the source and drain electrodes 43 and 44 including data lines (not shown). do. In this case, the photoresist pattern 49 may not remain in the portion corresponding to the gate line 45.
도 2e를 참조하면, 포토레지스트 패턴(49)을 마스크로 사용하여 패시베이션층(47), 오믹금속층(45), 오믹접촉층(41) 및 활성층(39)의 노출된 부분을 순착적으로 식각한다. 상기에서 패시베이션층(47), 오믹금속층(45), 오믹접촉층(41) 및 활성층(39)을 3 단계의 건식 식각에 의해 순차적으로 패터닝한다.Referring to FIG. 2E, the exposed portions of the passivation layer 47, the ohmic metal layer 45, the ohmic contact layer 41, and the active layer 39 are sequentially etched using the photoresist pattern 49 as a mask. . The passivation layer 47, the ohmic metal layer 45, the ohmic contact layer 41, and the active layer 39 are sequentially patterned by three steps of dry etching.
상기에서 1 단계 건식 식각은 SF6+ He의 혼합 가스로 패시베이션층(47)을, 2 단계 건식 식각은 SF6+ He + O2의 혼합 가스로 오믹금속층(45)을, 3 단계 건식 식각은 SF6+ He + HCl의 혼합 가스로 오믹접촉층(41) 및 활성층(39)을 순착적으로 식각한다. 이 때, 게이트전극(33)과 대응하는 부분은 1 단계 건식 식각시 SF6+ He의 혼합 가스에 의해 패시베이션층(47) 뿐만 아니라 오믹접촉층(41) 및 활성층(39)도 식각되며, 2 단계 건식 식각시 SF6+ He + O2의 혼합 가스에 의해 게이트절연막(39)이 식각되어 게이트전극(33)이 노출된다. 그러므로, 게이트전극(33)의 노출된 부분은 3 단계 건식 식각시 SF6+ He + HCl의 혼합 가스와 접촉된다. 상기에서 3 단계 건식 식각시 사용되는 SF6+ He + HCl의 혼합 가스에서 HCl도 가스 상태이므로 게이트전극(33)의 노출된 부분이 식각에 의한 손상을 받지 않게 된다.The first step dry etching is a passivation layer 47 with a mixed gas of SF 6 + He, the second step dry etching is an ohmic metal layer 45 with a mixed gas of SF 6 + He + O 2 , the third step dry etching is The ohmic contact layer 41 and the active layer 39 are sequentially etched with a mixed gas of SF 6 + He + HCl. At this time, the portion corresponding to the gate electrode 33 is etched not only the passivation layer 47 but also the ohmic contact layer 41 and the active layer 39 by the mixed gas of SF 6 + He during the one-step dry etching. During the step dry etching, the gate insulating layer 39 is etched by the mixed gas of SF 6 + He + O 2 to expose the gate electrode 33. Therefore, the exposed portion of the gate electrode 33 is in contact with the mixed gas of SF 6 + He + HCl during the three-step dry etching. In the mixed gas of SF 6 + He + HCl used in the three-step dry etching, HCl is also in a gas state, so that the exposed portion of the gate electrode 33 is not damaged by etching.
그리고, 게이트전극(33)의 노출된 부분에 잔류하는 Cl 성분을 제거한다. 상기에서 Cl 성분은 SF6+ O2의 혼합 가스로 애싱(ashing) 처리하면 하기의 식,The Cl component remaining in the exposed portion of the gate electrode 33 is removed. The Cl component in the above ashing (ash) treatment with a mixed gas of SF 6 + O 2
SF6+ Cl2→SF4Cl2↑+ F2,SF 6 + Cl 2 → SF 4 Cl 2 ↑ + F 2 ,
4O2+ Cl2→2ClO4↑4O 2 + Cl 2 → 2ClO 4 ↑
과 같이 반응한다. 그러므로, Cl 성분은 SF6및 O2성분과 반응하여 증발하므로 게이트전극(33)의 노출된 부분에 잔류하지 않게 된다.React as Therefore, the Cl component reacts with the SF 6 and O 2 components and evaporates so that the Cl component does not remain in the exposed portion of the gate electrode 33.
도 2f를 참조하면, 포토레지스트 패턴(49)을 스트립(strip)하여 제거한다. 이 때, 게이트전극(33)의 노출된 부분에 Cl 성분이 잔류하지 않으므로 H2O의 H2성분과의 반응으로 인한 HCl 용액이 생성되지 않는다. 그러므로, 게이트전극(33)의 노출된 부분이 손상되는 것이 방지된다.Referring to FIG. 2F, the photoresist pattern 49 is stripped and removed. At this time, since the Cl component does not remain in the exposed portion of the gate electrode 33, HCl solution due to the reaction of H 2 O with the H 2 component is not produced. Therefore, the exposed portion of the gate electrode 33 is prevented from being damaged.
상술한 바와 같이 본 발명에 따른 박막트랜지스터의 제조 방법은 패시베이션층을 SF6+ He의 혼합 가스로 인한 1 단계 건식 식각으로, 오믹금속층을 SF6+ He + O2의 혼합 가스로 인한 2 단계 건식 식각으로, 그리고, 오믹접촉층 및 활성층을 SF6+ He + HCl의 혼합 가스로 인한 3 단계 건식 식각으로 순차적으로 식각한다. 이 때, 게이트전극과 대응하는 부분은 1 단계 건식 식각시 패시베이션층 뿐만 아니라 오믹접촉층 및 활성층도 식각되며, 2 단계 건식 식각시 게이트절연막이 식각되어 게이트전극이 노출되므로 이 게이트전극의 노출된 부분은 3 단계 건식 식각시 SF6+ He + HCl의 혼합 가스와 접촉되어 잔류하는 Cl 성분을 SF6+ O2의 혼합 가스로 애싱(ashing) 처리하여 제거한다.Method of manufacturing a TFT according to aspects of the present invention as described above, a passivation layer of the first step dry-etching due to the mixed gas of SF 6 + He, the ohmic metal layer of SF 6 + He + O 2-step dry due to the second gas mixture of By etching, the ohmic contact layer and the active layer are sequentially etched in a three step dry etching due to the mixed gas of SF 6 + He + HCl. At this time, the portion corresponding to the gate electrode is etched not only the passivation layer but also the ohmic contact layer and the active layer during the one-step dry etching, and the exposed portion of the gate electrode since the gate insulating film is etched during the two-step dry etching. Is removed by ashing the Cl component remaining in contact with the mixed gas of SF 6 + He + HCl during the three-step dry etching with a mixed gas of SF 6 + O 2 .
따라서, 본 발명은 Cl 성분이 잔류하지 않으므로 H2O의 H2성분과의 반응으로 인한 HCl 용액이 생성되지 않아 제 1 금속층이 노출되는 것을 방지하므로 게이트전극의 노출된 부분이 손상으로 판정되어 되는 것을 방지하여 수율을 향상시킬 수 있는 잇점이 있다.Therefore, in the present invention, since the Cl component does not remain, HCl solution is not generated due to the reaction of H 2 O with the H 2 component, thereby preventing the first metal layer from being exposed. Thus, the exposed portion of the gate electrode is determined to be damaged. There is an advantage that can be prevented to improve the yield.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서, 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여져야 할 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.
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