KR20060021531A - Method for fabricating array substrate of tft-lcd - Google Patents

Abstract

The present invention discloses a method for manufacturing an array substrate of a thin film transistor liquid crystal display device. The disclosed method includes providing a glass substrate having a gate line including a gate electrode and having a gate insulating film formed on a front surface thereof to cover the gate electrode and the gate line, and an amorphous silicon film for a channel layer on the gate insulating film. And sequentially forming a doped amorphous silicon film for an ohmic contact layer and a source / drain metal film including Al, and covering a data line formation region including a source / drain electrode formation region on the source / drain metal film. Forming a data line by wet etching the source / drain metal film and forming a data line by over-etching the source / drain metal film. Making the side portion undercut to the bottom of the halftone mask; Removing the reverse halftone mask portion, and dry-etching the source / drain metal film portion and the doped amorphous silicon film portion below the channel region using Cl2 gas to dry the source / drain electrode and the ohmic contact layer. And forming a channel layer and forming a thin film transistor, removing the halftone mask, forming a passivation layer on the substrate resultant, and forming a pixel electrode contacting the source electrode on the passivation layer. It characterized by comprising the step of forming.

Description

Method for fabricating array substrate of thin film transistor liquid crystal display device

1A to 1E are cross-sectional views illustrating a conventional method for manufacturing an array substrate.

Figure 2a to 2e is a cross-sectional view for each process for explaining the array substrate manufacturing method according to the present invention.

* Description of the symbols for the main parts of the drawings *

21: glass substrate 22: gate electrode

23 gate insulating film 24 amorphous silicon film

24a: channel layer 25 doped amorphous silicon film

25a: ohmic contact layer 26: metal film for source / drain

26a / 26b: source / drain electrodes 27: halftone mask

30: thin film transistor

The present invention relates to a method for manufacturing a thin film transistor liquid crystal display device, and more particularly, to an array substrate manufacturing method using a four-mask process.

Liquid crystal displays have been developed in place of the CRT (Cathode Ray Tube) based on the advantages of low weight, low voltage driving and low power consumption. In particular, since T-Film Transistors (TFT-LCDs) have realized high quality, large size, and colorization comparable to CRTs, they have recently diversified not only in the notebook PC and monitor market but also in everybody. It is used.

Such a TFT-LCD typically has a structure in which an array substrate with TFT and pixel electrodes and a color filter substrate with color filters and counter electrodes are bonded under the liquid crystal layer.

On the other hand, in such a TFT-LCD, it is very important to reduce the number of manufacturing steps thereof, in particular, the number of manufacturing steps of the array substrate. This is because as the number of manufacturing processes is reduced, the manufacturing cost of the TFT-LCD can be reduced, because a larger amount of TFT-LCD can be supplied at a lower price.

Here, the reduction of the number of manufacturing processes is usually realized by the reduction of the number of mask processes, and recently, TFT-LCDs are manufactured by 5-mask and 4-mask processes. The mask process may be understood as a process of forming a photoresist pattern which is an etch mask through photoresist coating, exposure and development processes.

Hereinafter, a method of manufacturing an array substrate using a conventional 4-mask process will be described with reference to FIGS. 1A to 1E.

Referring to FIG. 1A, after depositing a gate metal film on the glass substrate 1, the metal film is patterned according to a first mask process to form a gate line including the gate electrode 2 (not shown). Thereafter, a gate insulating film 3 is formed on the entire surface of the glass substrate 1 so as to cover the gate electrode 2 and the gate line, and then an amorphous silicon (hereinafter referred to as a-Si) film 4 for the channel layer thereon. And the doped amorphous silicon (hereinafter, n + a-Si) film 5 for the ohmic contact layer and the metal film 6 for the source / drain are deposited in this order. As the source / drain metal film 6, an Al film, an Al alloy film, or a laminated film based on Al such as Mo / Al / Mo or Ti / Al / Ti is formed.

Referring to FIG. 1B, the thickness of the portion disposed on the channel region while covering the data line forming region including the source / drain electrode forming region on the source / drain metal film 6 according to the second mask process is different. A half tone mask (7) that is relatively thinner than the portion is formed.

Referring to FIG. 1C, the source / drain metal film 6 is etched using the halftone mask 7 to form a data line (not shown).

Referring to FIG. 1D, the halftone mask portion on the channel region is removed through a known ashing process, thereby exposing the source / drain metal film portion on the channel region.

Referring to FIG. 1E, the exposed source / drain metal film portion is removed by dry etching using Cl 2 gas, thereby forming source / drain electrodes 6a and 6b. Subsequently, the n + a-Si film portion on the channel region is etched to form the ohmic contact layer 5 and the channel layer 4a, thereby forming the TFT 10.

Here, the active line is formed by etching together the portion of the n + a-Si film and the portion of the a-Si film below that are not covered by the halftone mask 7 and the source / drain metal film.

Although not shown, a via hole for exposing a source / drain electrode, for example, a source electrode, may be formed by applying a protective film on the substrate resultant up to the above step with the remaining halftone mask removed. Form.

Thereafter, an ITO metal film is deposited on the passivation film including the via hole, and then the ITO metal film is patterned according to a fourth mask process to form a pixel electrode in contact with the source electrode. As a result, the fabrication of the array substrate is completed. do.

However, according to the conventional method of manufacturing an array substrate using a four-mask process, by applying an etching rate such that the primary wet etching of the source / drain metal film is etched along the forming surface of the halftone mask. As a result, the side portion of the etched source / drain metal film may be exposed to the Cl 2 gas during the second dry etching using the Cl 2 gas. In this case, as the Cl2 gas remaining on the exposed side of the source / drain metal film is exposed to the atmosphere, the Cl2 gas reacts with moisture in the air to change into HCl. Serious problems such as short circuits occur.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and a method of manufacturing an array substrate of a TFT-LCD which can prevent the occurrence of corrosion when etching the source / drain metal film of the Al base film with Cl2 gas. The purpose is to provide.                         

In addition, another object of the present invention is to provide a method of manufacturing an array substrate of a TFT-LCD which can secure a process yield by preventing short circuit of data lines due to corrosion.

In order to achieve the above object, the present invention provides a glass substrate comprising a gate line including a gate electrode, a gate insulating film formed on the front surface to cover the gate electrode and the gate line; Sequentially forming a source / drain metal film including an a-Si film for a channel layer, an n + a-Si film for an ohmic contact layer, and Al on the gate insulating film; Forming a halftone mask on the source / drain metal film, covering a data line formation region including a source / drain electrode formation region and having a thickness thinner than that on the channel predetermined region; First wet etching the source / drain metal film to form a data line, and performing excessive etching so that a side portion of the etched source / drain metal film is undercut under the halftone mask; Etching away the halftone mask portion on the channel region; The source / drain metal film portion on the channel region and the n + a-Si film portion below it are dry-etched secondly using Cl2 gas to form a source / drain electrode, an ohmic contact layer and a channel layer, and a thin film transistor Configuring a; Removing the halftone mask; Forming a protective film on the substrate resultant; And forming a pixel electrode on the pixel area on the passivation layer.

The source / drain metal film is any one of an Al film, an Al alloy film, or an Al-based laminated film (Mo / Al / Mo or Ti / Al / Ti).

The primary wet etching of the source / drain metal film is performed with a transient etching of 200% or more.

The secondary dry etching of the source / drain metal film is performed by adding at least one gas selected from the group consisting of BCl 3 gas, CCl 4 gas, SiCl 4 gas, and BBr 3 gas to Cl 2 gas.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be briefly described. In the case of applying a material susceptible to corrosion, such as an Al base film, to the source / drain metal film, the first wet etching process for forming a data line, By applying overetch, the lateral portions of the etched source / drain metal film cause a significant amount of undercut under the halftone mask.

In this case, during the subsequent dry etching using the Cl2 gas, the side portion of the undercut source / drain metal film is suppressed from direct contact with the Cl2 gas, and thus, Al by HCl generated during atmospheric exposure is suppressed. Corrosion of the base film is prevented or minimized.

Accordingly, the present invention can prevent corrosion by the etched source / drain metal film, that is, the HCl of the data line, thereby securing a process yield.

In detail, a method of manufacturing an array substrate of a TFT-LCD according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2E.

Referring to FIG. 2A, a gate line including a gate electrode 22 is formed by depositing a gate metal film on a transparent insulating substrate, for example, a glass substrate 21, and then patterning the gate metal film according to a first mask process. Not shown). Thereafter, a gate insulating film 23 is formed on the entire surface of the substrate to cover the gate electrode 22 and the gate line, and then the a-Si film 24 for the channel layer and the ohmic contact layer are formed on the gate insulating film 23. An n + a-Si film 25 is sequentially formed, and then an Al film, an Al alloy film, or an Al-based laminated film (Mo / Al / Mo or Ti /) is formed on the n + a-Si film 25 for the ohmic contact layer. A source / drain metal film 26 made of any one of Al / Ti) is formed.

Referring to FIG. 2B, the thickness of the channel region is relatively greater than that of other portions while covering the data line forming region including the source / drain electrode forming region on the source / drain metal layer 26 according to the second mask process. A thin halftone mask 27 is formed.

Referring to FIG. 2C, the source / drain metal layer 26 is first wet-etched using the halftone mask 27 as an etch mask, and thus, a data line perpendicular to the gate line is illustrated. Form. In this case, the first wet etching of the source / drain metal layer 26 may be performed by over-etching 200% or more of the source / drain metal layer 26 etched under the halftone mask 27. Make the sides undercut a significant amount. This is to be described later, but to suppress or minimize the corrosion problem by preventing the side of the source / drain metal film 26 etched during the subsequent secondary dry etching to be directly exposed to Cl2 gas.

Referring to FIG. 2D, the halftone mask portion on the channel region is removed by a known etching process, thereby exposing the source / drain metal film portion on the channel region.

Referring to FIG. 2E, secondary dry etching using a mixed gas of BCl3 gas, CCl4 gas, SiCl4 gas, or BBr3 gas, preferably a mixed gas of BCl3 / Cl2, is added to Cl2 gas for the substrate product. In this process, the source / drain electrodes 26a and 26b are etched by etching the source / drain metal film portions on the exposed channel region, followed by etching the n + a-Si film portions thereunder. In addition to forming the ohmic contact layer 25a, a-Si channel layer 24a is formed. As a result, the TFT 30 is constituted.

At this time, during the second dry etching, the active line is formed by etching together the portion of the n + a-Si film and the portion of the a-Si film below that are not covered by the halftone mask 27 and the source / drain metal film. Do it.

Here, in the second dry etching process using the BCl3 / Cl2 mixed gas, the side wetted portion of the first wet-etched source / drain metal film is substantially undercut to the lower portion of the halftone mask 27, and thus with the Cl2 gas. There is no direct contact, whereby corrosion in the side portions of the etched source / drain metal film by HCl formed in reaction with moisture in the atmosphere does not occur or is minimized.

As a result, the present invention induces sufficient undercut through the transient etching during the first wet etching of the source / drain metal film, thereby preventing corrosion of the side portion of the etched source / drain metal film during the subsequent second dry etching. It can be suppressed or minimized, so that the process yield can be secured.

Subsequently, although not shown, the halftone mask used as the etching mask is removed. After that, a protective film is formed on the entire surface of the substrate to protect the TFT 30, and then the protective film is etched according to a third mask process to expose a source / drain electrode, for example, a source hole 26a. Next, a pixel electrode 22 in contact with the exposed source electrode 26a according to the fourth mask process is formed on the pixel area on the passivation layer, thereby completing the fabrication of the array substrate of the TFT-LCD according to the present invention. do.

As described above, in the present invention, in applying the Al base film as the metal film for the source / drain, a sufficient undercut is caused by performing excessive etching during the first wet etching of the metal film for the source / drain to form a data line. The occurrence of lateral corrosion due to exposure to Cl2 gas during subsequent secondary dry etching to form the source / drain electrodes can be suppressed or minimized, thereby ensuring process yield.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

Claims (4)

Providing a glass substrate having a gate line including a gate electrode and having a gate insulating film formed on a front surface thereof to cover the gate electrode and the gate line; Sequentially forming an amorphous silicon film for a channel layer, a doped amorphous silicon film for an ohmic contact layer, and a source / drain metal film including Al on the gate insulating film; Forming a halftone mask on the source / drain metal film, covering a data line formation region including a source / drain electrode formation region and having a thickness thinner than that on the channel predetermined region; First wet etching the source / drain metal film to form a data line, and performing excessive etching so that a side portion of the etched source / drain metal film is undercut under the halftone mask; Etching away the halftone mask portion on the channel region; The source / drain metal film portion on the channel region and the doped amorphous silicon film portion below are dry-etched secondly using Cl2 gas to form a source / drain electrode, an ohmic contact layer and a channel layer, and a thin film transistor Configuring a; Removing the halftone mask; Forming a protective film on the substrate resultant; And And forming a pixel electrode in contact with the source electrode on the passivation layer. The method of claim 1, wherein the source / drain metal film is any one selected from the group consisting of an Al film, an Al alloy film, and an Al-based laminated film (Mo / Al / Mo or Ti / Al / Ti). An array substrate manufacturing method of a thin film transistor liquid crystal display device. The method of claim 1, wherein the first wet etching of the source / drain metal film is performed by a transient etching of 200% or more. The method of claim 1, wherein the second dry etching of the source / drain metal film is performed by adding at least one gas selected from the group consisting of BCl3 gas, CCl4 gas, SiCl4 gas, and BBr3 gas to Cl2 gas. An array substrate manufacturing method of a thin film transistor liquid crystal display device.

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