KR20010094043A - Method For Forming The Self Align Contact - Google Patents
Method For Forming The Self Align Contact Download PDFInfo
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- KR20010094043A KR20010094043A KR1020000017411A KR20000017411A KR20010094043A KR 20010094043 A KR20010094043 A KR 20010094043A KR 1020000017411 A KR1020000017411 A KR 1020000017411A KR 20000017411 A KR20000017411 A KR 20000017411A KR 20010094043 A KR20010094043 A KR 20010094043A
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims abstract description 5
- 229920000314 poly p-methyl styrene Polymers 0.000 claims abstract 9
- 206010063401 primary progressive multiple sclerosis Diseases 0.000 claims abstract 9
- 230000004888 barrier function Effects 0.000 claims description 16
- 239000000126 substance Substances 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract description 6
- UIUXUFNYAYAMOE-UHFFFAOYSA-N methylsilane Chemical compound [SiH3]C UIUXUFNYAYAMOE-UHFFFAOYSA-N 0.000 abstract description 6
- 238000011109 contamination Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 239000000463 material Substances 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- -1 Methyl Silane Oxide Chemical compound 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
Description
본 발명은 반도체 소자의 형성 방법에 관한 것으로서, 특히, 고집적화된 반도체 소자에서 미세 콘택홀의 콘택전극 제조 공정시 식각 선택비를 증가시키고, 종횡비를 감소하며, 오염물질을 감소하여 결함을 최대한도로 줄일 수 있는 자기정렬 콘택전극 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device. In particular, in a highly integrated semiconductor device, an etching selectivity may be increased, an aspect ratio may be reduced, and a contamination may be reduced to a maximum defect in a contact electrode manufacturing process of a micro contact hole. A self-aligning contact electrode forming method.
일반적으로, 반도체기판 상에 여러가지 상부층을 적층한 후 식각공정으로 콘택홀을 형성하는 방법중 하나인 자기정렬 콘택(SAC : Self Align Contact) 형성방법은, 소정 하부구조를 갖는 반도체기판 상에 식각장벽막(예컨대, SiN)과 층간절연막(IPO ; Inter Poly Oxide)를 순차적으로 형성하고, 그 위에 포토레지스트의 도포하고 노광 및 현상공정을 통하여 콘택홀이 형성될 부위의 포토레지스트만을 선택적으로 제거하여 포토레지스트패턴을 형성한 후, 건식 혹은 습식식각으로 상기 패턴에 의해 드러나는 층간절연막을 식각해서 콘택홀을 형성하는 방법이다.In general, a method of forming a self alignment contact (SAC), which is a method of forming contact holes through an etching process after stacking various upper layers on a semiconductor substrate, has an etching barrier on a semiconductor substrate having a predetermined substructure. A film (e.g., SiN) and an interlayer insulating film (IPO) are sequentially formed, the photoresist is applied thereon, and only the photoresist of the site where the contact hole is to be formed is selectively removed through the exposure and development processes. After forming the resist pattern, a contact hole is formed by etching the interlayer insulating film exposed by the pattern by dry or wet etching.
예를 들면, 워드라인 및 비트라인이 형성된 기판에 실시되는 자기정렬콘택전극을 형성하는 방법은 다음과 같다.For example, a method of forming a self-aligned contact electrode formed on a substrate on which word lines and bit lines are formed is as follows.
소정의 하부구조를 갖는 반도체기판 상에 워드라인(Word Line) 및 비트라인 (Bit Line)상에 식각장벽막(Barrier Layer) 및 층간절연막을 증착하는 공정을 진행한다. 그리고, 층간절연막을 화학적연마공정으로 평탄화한 후, 층간절연막 상부에자기정렬형 포토레지스트 패턴을 형성한다. 상기 포토레지스트 패턴에 맞추어 층간절연막 및 식각장벽막을 식각해서 자기정렬 콘택홀을 형성한다. 그 다음, 상기 콘텍홀내에 도전체로서 폴리실리콘층을 매립하고, 화학기계적연마공정(CMP) 또는 전면 식각공정으로 평탄화시켜 콘택홀 내에 자기정렬 콘택전극을 형성한다.A process of depositing an etch barrier film and an interlayer insulating film on a word line and a bit line on a semiconductor substrate having a predetermined substructure is performed. After the interlayer insulating film is flattened by a chemical polishing process, a self-aligned photoresist pattern is formed on the interlayer insulating film. The interlayer insulating film and the etching barrier film are etched according to the photoresist pattern to form a self-aligning contact hole. Then, a polysilicon layer is embedded in the contact hole as a conductor, and planarized by a chemical mechanical polishing process (CMP) or an entire surface etching process to form a self-aligned contact electrode in the contact hole.
한편, 도 1a 내지 도1c는 자기정렬콘택전극 제조 공정시 발생되는 여러 가지 문제점을 나타낸 도면이다.On the other hand, Figures 1a to 1c is a view showing a variety of problems generated during the self-aligned contact electrode manufacturing process.
먼저, 도 1a를 참조하면, 층간 절연막 하부에 식각장벽막이 없거나 취약한 경우 하부구조, 특히 배선에 침식(Attack)이 가하여 불량한 상태를 보이고 있으며, 도 1b는 층간 절연막을 평탄화하면서 발생하는 스크래치 결함(Scratch Defect)을 보인 도면이고, 도 1c는 층간절연막을 평탄화한 후에 슬러리 잔류물질(Slurry Residue)이 잔류된 상태를 보인 도면이다.First, referring to FIG. 1A, when an etch barrier film is not provided or is vulnerable under the interlayer insulating film, erosion is applied to the underlying structure, especially the wiring, and a bad state is shown. FIG. 1C is a view showing a state in which a slurry residue remains after planarizing the interlayer insulating film.
이와 같이, 종래 자기정렬 콘택전극 제조 공정시 층간절연막의 평탄화 공정, 콘택홀 식각 공정 및 콘택전극 분리를 위한 평탄화 공정으로 인해 발생되는 소자의 오염 및 결함에 의해 반도체 소자의 제조 수율이 저하되는 문제점이 있었다.As described above, the manufacturing yield of the semiconductor device may be degraded due to the contamination and defects of the device caused by the planarization of the interlayer insulating layer, the contact hole etching process, and the planarization process for contact electrode separation in the conventional self-aligned contact electrode manufacturing process. there was.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 반도체 소자의 자기정렬 콘택전극 제조 공정시 기판의 하부 구조물에 식각장벽막을 증착하고 그 상부면에 통상의 층간 절연막 대신에 노광 공정에 의해 산화물질로 변성되는 PPMS(Plasma Polymerized Methyl Silane)를 이용하여 포토레지스트 패턴을 형성한 후에 식각장벽막을 식각해서 자기정렬 콘택홀을 형성함으로써 이후 콘택홀 식각을 위한 층간절연막의 평탄화 공정을 생략할 수 있어 여러번의 평탄화 공정으로 인한 오염 및 결함을 줄일 수 있으며 동시에 콘택홀 식각 종횡비(aspect ratio)를 줄일 수 있는 것이 목적이다.SUMMARY OF THE INVENTION The present invention has been made in view of this point, and in the process of fabricating a self-aligned contact electrode of a semiconductor device, an etch barrier film is deposited on a lower structure of a substrate, and the upper surface is modified into an oxide material by an exposure process instead of a conventional interlayer insulating film. After forming a photoresist pattern using PPMS (Plasma Polymerized Methyl Silane), the etching barrier film is etched to form a self-aligned contact hole, thereby eliminating the planarization of the interlayer dielectric layer for contact hole etching. The aim is to reduce contamination and defects caused by the process and at the same time reduce the contact hole etching aspect ratio.
도 1a는 종래의 자기정렬 콘택홀을 형성할 때, 하층 배선에 발생되는 손실을 보인 도면이며,FIG. 1A is a view showing a loss generated in a lower layer wiring when a conventional self-aligned contact hole is formed.
도 1b는 종래의 자기정렬 콘택홀을 형성할 때, 층간 절연막을 평탄화하면서 발생하는 스크래치 결함(Scratch Defect)을 보인 도면이며,FIG. 1B is a view showing scratch defects generated by planarizing an interlayer insulating layer when forming a conventional self-aligned contact hole. FIG.
도 1c는 종래의 자기정렬 콘택홀을 형성할 때, 층간절연막을 평탄화한 후에 슬러리 잔류물질(Slurry Residue)이 잔류된 상태를 보인 도면이며,FIG. 1C is a view illustrating a slurry residual material remaining after planarizing an interlayer insulating film when forming a conventional self-aligned contact hole.
도 2a 내지 도 2f는 본 발명에 따른 자기정렬 콘택홀을 형성하는 공정을 순차적으로 보인 도면이다.2A through 2F are views sequentially illustrating a process of forming a self-aligned contact hole according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
10 : 반도체기판 15 : 게이트절연막10 semiconductor substrate 15 gate insulating film
20 : 게이트전극 25 : 스페이서막20 gate electrode 25 spacer film
30 : 식각장벽막 40 : PPMS막30 etch barrier 40 PPMS film
45 : 자기정렬 패턴 55 : 자기정렬 콘택홀 영역45: self-aligned pattern 55: self-aligned contact hole region
55' : 자기정렬 콘택홀 60 : 콘택전극55 ': self-aligned contact hole 60: contact electrode
이러한 목적은 반도체소자의 자기정렬 콘택전극 형성방법에 있어서, 반도체기판 상에 게이트절연막, 게이트전극, 게이트전극 측벽에 스페이서막 및 소오스/드레인 접합층을 순차적으로 형성하는 단계와, 결과물 전면에 식각장벽막을 형성하는 단계와, 식각장벽막이 형성된 결과물 상에 화학기상증착법으로 PPMS(Plasma Polymerized Methyl Silane)막을 형성하는 단계와, PPMS막에 노광, 현상 및 식각 공정을 실시하여 PPMSO(Plasma Polymerized Methyl Silane Oxide)막으로 이루어지며 콘택홀을 정의하는 자기정렬 패턴을 형성하는 단계와, 자기정렬 패턴 하부의 식각장벽막을 식각하여 소오스/드레인 접합층이 개방되는 자기정렬콘택홀을 형성하는 단계와, 자기정렬콘택홀 내에 도전체를 매립하고 화학기계적연마법으로 연마해서 콘택전극을 형성하는 단계를 포함하여 이루어진다.The object of the present invention is to provide a method of forming a self-aligned contact electrode of a semiconductor device, the method comprising sequentially forming a spacer film and a source / drain junction layer on a sidewall of a gate insulating film, a gate electrode and a gate electrode, and an etch barrier on the entire surface of the resultant substrate. Forming a film, forming a PPMS (Plasma Polymerized Methyl Silane) film on the resultant on which the etch barrier film is formed, and exposing, developing, and etching the PPMS film to a PPMSO (Plasma Polymerized Methyl Silane Oxide). Forming a self-aligned pattern formed of a film and defining a contact hole, etching the etch barrier under the self-aligned pattern to form a self-aligned contact hole in which a source / drain junction layer is opened, and a self-aligned contact hole Embedding the conductor in the substrate and polishing by chemical mechanical polishing to form a contact electrode. The.
본 발명의 제조 방법에 있어서, 상기 PPMS막의 현상 공정시 Cl2플라즈마로 현상하거나 Cl2/ HBr 플라즈마로 현상하는 것이 바람직하다.In the production method of the present invention, it is preferable to develop with Cl 2 plasma or develop with Cl 2 / HBr plasma during the development process of the PPMS film.
그리고 본 발명의 제조 방법에 있어서, 상기 PPMS의 식각 공정이전에 O2플라즈마를 처리할 수 있다.In the manufacturing method of the present invention, the O 2 plasma may be treated before the etching process of the PPMS.
또한 본 발명의 제조 방법에 있어서, 상기 자기정렬콘택홀을 형성한 후에, 자기정렬 패턴의 조직을 치밀하게 하기 위해 추가의 열 공정을 실시할 수 있다.In addition, in the manufacturing method of the present invention, after the self-aligned contact hole is formed, an additional thermal process may be performed to densify the structure of the self-aligned pattern.
또한, 본 발명의 제조 방법에 있어서, 상기 자기정렬 패턴을 이후 층간 절연막으로 이용할 수 있도록 두껍게 증착하는 것이 바람직하다.Further, in the manufacturing method of the present invention, it is preferable to deposit the self-aligned pattern thickly so that it can be used as an interlayer insulating film.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 반도체소자의 자기정렬 콘택전극 형성방법의 일실시예에 대해 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of a method for forming a self-aligned contact electrode of a preferred semiconductor device of the present invention.
도 2a 내지 도 2f는 본 발명에 따른 자기정렬 콘택홀을 형성하는 공정을 순차적으로 보인 도면이다.2A through 2F are views sequentially illustrating a process of forming a self-aligned contact hole according to the present invention.
도 2a에 도시된 바와 같이, 반도체기판(10) 상에 반도체소자로서 게이트절연막(15), 게이트전극(20), 게이트전극(20) 측벽에 스페이서막(25) 및 소오스/드레인 접합층(미도시함)을 순차적으로 형성하여 트랜지스터를 완성한다.As shown in FIG. 2A, a gate insulating film 15, a gate electrode 20, a spacer film 25 on sidewalls of the gate electrode 20, and a source / drain junction layer are formed on the semiconductor substrate 10 as a semiconductor device. To form a transistor in order to complete the transistor.
그리고, 상기 결과물에 이후 형성될 층간절연막,(본 실시예에서는 PPMSO)에 대해 식각 선택비가 다른 식각장벽막(30)으로서 실리콘질화막을 형성한다.Then, a silicon nitride film is formed as an etch barrier film 30 having an etch selectivity different from that of the interlayer insulating film (PPMSO in this embodiment) to be formed later on the resultant.
그 다음, 도 2b에 도시된 바와 같이, 식각장벽막(30)이 형성된 결과물 상부에 화학기상증착법(Chemical Vapor Deposition)으로 PPMS(Plasma Polymerized Methyl Silane)막(40)을 증착한다. 여기서, PPMS막(40)은 메틸 실레인 전구체(methyl silane presursor)를 CVD 반응기에서 증착한 것으로서 그 화학식은 다음과 같다.Next, as shown in FIG. 2B, a Plasma Polymerized Methyl Silane (PPMS) film 40 is deposited by chemical vapor deposition (Chemical Vapor Deposition) on the resultant product on which the etch barrier film 30 is formed. Here, the PPMS film 40 is a methyl silane precursor (methyl silane presursor) is deposited in a CVD reactor, the chemical formula is as follows.
계속해서 도 2c에 도시된 바와 같이, 상기 PPMS막(40)에 콘택홀 마스크를 이용한 노광 공정을 실시한다. 이때, 노광 공정은 248nm 또는 198nm의 DUV를 이용하는데, 자외선 방사에 노출되는 PPMS막은 대기상태의 산화물과 광-산화되어 PPMSO(Plasma Polymerized Methyl Silane Oxide)로 변형된다.Subsequently, as illustrated in FIG. 2C, an exposure process using a contact hole mask is performed on the PPMS film 40. At this time, the exposure process uses a DUV of 248 nm or 198 nm, the PPMS film exposed to ultraviolet radiation is photo-oxidized with the oxide in the atmosphere is transformed into PPMSO (Plasma Polymerized Methyl Silane Oxide).
여기서, PPMSO의 화학식은 다음과 같다.Here, the chemical formula of PPMSO is as follows.
그리고, 노광 공정을 거친후에 노광되지 않는 콘택홀부위를 정의하는 PPMS막(40)을 제거하기 위하여 현상 공정을 실시한다. 이때, 현상 공정은 Cl2플라즈마로 현상하거나 Cl2/ HBr 플라즈마로 현상하는 것이 바람직하다. 이러한 현상 공정에 의해, 이후 콘택홀이 형성되지 않는 부위에는 저유전율의 PPMSO막이 형성된다.After the exposure process, a development process is performed to remove the PPMS film 40 that defines the non-exposed contact hole portion. At this time, the developing process is preferably developed by Cl 2 plasma or developed by Cl 2 / HBr plasma. By this development process, a low dielectric constant PPMSO film is formed in the site where a contact hole is not formed later.
이 저유전율의 PPMSO막의 화학식은 다음과 같다.The chemical formula of this low dielectric constant PPMSO film is as follows.
그 다음, 도 2d에 도시된 바와 같이, 본 발명의 제조 공정은 상기 현상된 PPMS을 제거하기 위하여 식각 공정을 진행하는데, 희석제 등의 화학약품을 사용한다.Then, as shown in Figure 2d, the manufacturing process of the present invention proceeds the etching process to remove the developed PPMS, using a chemical such as a diluent.
계속해서, O2플라즈마 등의 어닐링 공정을 실시하여 저유전율의 PPMSO를 절연 특성이 양호한 산화 물질로 변화시킴으로서 자기정렬 콘택홀 영역(55)을 정의하는 요(凹)구조의 자기정렬 패턴(45)을 형성한다. 여기서, 산화 물질로 변화된 PPSMO의 자기정렬 패턴(45)은 반도체소자와 이후 형성될 배선 사이를 층간 분리하는 층간 절연막으로 사용될 수 있다.Subsequently, a self-aligned pattern 45 having a concave structure defining the self-aligned contact hole region 55 by performing an annealing process such as an O 2 plasma to change the low dielectric constant PPMSO into an oxidizing material having good insulating properties. To form. Here, the self-aligned pattern 45 of the PPSMO changed into an oxidizing material may be used as an interlayer insulating film separating an interlayer between a semiconductor device and a wiring to be formed later.
상술한 어닐링 공정에 의해 산화 특성이 향상된 자기정렬 패턴(45)의 PPMSO막의 화학식은 다음과 같다.The chemical formula of the PPMSO film of the self-aligned pattern 45 having improved oxidation characteristics by the annealing process described above is as follows.
그 다음 도 2e에 도시된 바와 같이, 자기정렬 패턴(45) 하부의식각장벽막(30)을 식각하여 소오스/드레인 접합층이 개방되는 자기정렬콘택홀(55')을 형성한다. 그리고, 상기 자기정렬콘택홀(55')을 형성한 후에, 자기정렬 패턴(45)의 조직을 치밀하게 하기 위해 추가의 열 공정을 실시할 수 있다.Next, as shown in FIG. 2E, the etching barrier layer 30 under the self-aligning pattern 45 is etched to form a self-aligning contact hole 55 ′ in which the source / drain junction layer is opened. Further, after the self-aligned contact hole 55 'is formed, an additional thermal process may be performed to densify the structure of the self-aligned pattern 45.
그 다음, 도 2f에 도시된 바와 같이, 자기정렬콘택홀(55')이 형성된 결과물에 도전체로서 도프트 폴리실리콘을 매립하고 화학기계적연마법으로 연마하여 본 발명에 따른 자기정렬 콘택전극(60)을 형성한다.Next, as shown in FIG. 2F, the doped polysilicon is embedded as a conductor in the resultant self-aligned contact hole 55 ′ and polished by chemical mechanical polishing, and the self-aligned contact electrode 60 according to the present invention. ).
상기한 바와 같이, 본 발명은 자기정렬 콘택 전극 제조 공정시 종래 층간 절연막 증착, 평탄화 및 콘택홀 식각 공정대신에 화학적기상증착법의 포토레지스트 공정(즉, PPMS⇒PPMSO로 변화, 어닐처리)을 이용함으로써 제조 공정을 단순화할 수 있다.As described above, the present invention uses a chemical vapor deposition photoresist process (ie, change from PPMS to PPMSO, annealing) instead of the conventional interlayer insulating film deposition, planarization, and contact hole etching processes in the self-aligned contact electrode manufacturing process. The manufacturing process can be simplified.
그리고, 본 발명은 층간 절연막의 평탄화 공정 및 층간 절연막내 콘택홀 식각 공정으로 인한 오염 및 결함을 제거할 수 있다.In addition, the present invention can eliminate contamination and defects due to the planarization process of the interlayer insulating film and the contact hole etching process in the interlayer insulating film.
또한, 본 발명은 화학적기상증착법의 포토레지스트 공정에 따르는 콘택홀 종횡비(aspect ratio)의 감소할 수 있어 고집적 반도체소자의 미세한 콘택 제조 공정에 용이하다.In addition, the present invention can reduce the contact hole aspect ratio according to the photoresist process of chemical vapor deposition, which facilitates the fine contact manufacturing process of the highly integrated semiconductor device.
Claims (6)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000017411A KR20010094043A (en) | 2000-04-03 | 2000-04-03 | Method For Forming The Self Align Contact |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1020000017411A KR20010094043A (en) | 2000-04-03 | 2000-04-03 | Method For Forming The Self Align Contact |
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