KR20010086035A - 메모리 장치의 물리적 페이지 상태를 탐색하기 위해페이지 태그 레지스터를 이용하는 방법 - Google Patents

메모리 장치의 물리적 페이지 상태를 탐색하기 위해페이지 태그 레지스터를 이용하는 방법 Download PDF

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Publication number
KR20010086035A
KR20010086035A KR1020017006145A KR20017006145A KR20010086035A KR 20010086035 A KR20010086035 A KR 20010086035A KR 1020017006145 A KR1020017006145 A KR 1020017006145A KR 20017006145 A KR20017006145 A KR 20017006145A KR 20010086035 A KR20010086035 A KR 20010086035A
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KR
South Korea
Prior art keywords
page
memory
bank
address
requested
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020017006145A
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English (en)
Korean (ko)
Inventor
헨리 스트라코프스키
피오트르 스자벨스키
Original Assignee
마이클 골위저, 호레스트 쉐퍼
인피네온 테크놀로지스 아게
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Application filed by 마이클 골위저, 호레스트 쉐퍼, 인피네온 테크놀로지스 아게 filed Critical 마이클 골위저, 호레스트 쉐퍼
Publication of KR20010086035A publication Critical patent/KR20010086035A/ko
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Dram (AREA)
KR1020017006145A 1998-11-16 1999-11-15 메모리 장치의 물리적 페이지 상태를 탐색하기 위해페이지 태그 레지스터를 이용하는 방법 Ceased KR20010086035A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US10893098P 1998-11-16 1998-11-16
US60/108,930 1998-11-16
US09/439,303 US6374323B1 (en) 1998-11-16 1999-11-12 Computer memory conflict avoidance using page registers
US09/439,303 1999-11-12
PCT/US1999/027021 WO2000029957A1 (en) 1998-11-16 1999-11-15 Using page tag registers to track a state of physical pages in a memory device

Publications (1)

Publication Number Publication Date
KR20010086035A true KR20010086035A (ko) 2001-09-07

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020017006145A Ceased KR20010086035A (ko) 1998-11-16 1999-11-15 메모리 장치의 물리적 페이지 상태를 탐색하기 위해페이지 태그 레지스터를 이용하는 방법

Country Status (7)

Country Link
US (1) US6374323B1 (enExample)
JP (1) JP2002530743A (enExample)
KR (1) KR20010086035A (enExample)
CN (1) CN1282925C (enExample)
DE (2) DE19983745T1 (enExample)
GB (1) GB2359909B (enExample)
WO (1) WO2000029957A1 (enExample)

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US7778103B2 (en) 2007-04-05 2010-08-17 Samsung Electronics Co., Ltd. Semiconductor memory device for independently selecting mode of memory bank and method of controlling thereof
KR101121902B1 (ko) * 2010-06-22 2012-03-20 성균관대학교산학협력단 변경된 메모리 주소를 추적하는 트랜잭션 메모리 시스템 및 방법

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US7047391B2 (en) * 1998-09-14 2006-05-16 The Massachusetts Institute Of Technology System and method for re-ordering memory references for access to memory
US6453370B1 (en) * 1998-11-16 2002-09-17 Infineion Technologies Ag Using of bank tag registers to avoid a background operation collision in memory systems
US6490674B1 (en) 2000-01-28 2002-12-03 Hewlett-Packard Company System and method for coalescing data utilized to detect data hazards
US6535966B1 (en) * 2000-05-17 2003-03-18 Sun Microsystems, Inc. System and method for using a page tracking buffer to reduce main memory latency in a computer system
KR100644596B1 (ko) 2000-07-27 2006-11-10 삼성전자주식회사 버스 시스템 및 그 버스 중재방법
US6684311B2 (en) * 2001-06-22 2004-01-27 Intel Corporation Method and mechanism for common scheduling in a RDRAM system
US7007133B2 (en) * 2002-05-29 2006-02-28 Micron Technology, Inc. Synchronous memory open page register
JP2004078683A (ja) * 2002-08-20 2004-03-11 Toshiba Corp コンピュータシステムおよび共有メモリ制御方法
US7308510B2 (en) * 2003-05-07 2007-12-11 Intel Corporation Method and apparatus for avoiding live-lock in a multinode system
US7404047B2 (en) * 2003-05-27 2008-07-22 Intel Corporation Method and apparatus to improve multi-CPU system performance for accesses to memory
US7231499B2 (en) * 2003-12-17 2007-06-12 Broadcom Corporation Prioritization of real time / non-real time memory requests from bus compliant devices
JP4419074B2 (ja) * 2004-11-15 2010-02-24 エルピーダメモリ株式会社 半導体記憶装置
CN100385417C (zh) * 2005-06-15 2008-04-30 乐金电子（惠州）有限公司 请求页面调度方法及将有关页面信息输入到页面内的方法
US20070174549A1 (en) * 2006-01-24 2007-07-26 Yevgen Gyl Method for utilizing a memory interface to control partitioning of a memory module
CN101639817B (zh) * 2009-03-13 2012-01-25 青岛海信信芯科技有限公司 一种存储器的控制方法、存储器控制器和存储器控制系统
US20100318746A1 (en) * 2009-06-12 2010-12-16 Seakr Engineering, Incorporated Memory change track logging
US8856488B2 (en) 2010-02-11 2014-10-07 Memory Technologies Llc Method for utilizing a memory interface to control partitioning of a memory module
KR101292309B1 (ko) * 2011-12-27 2013-07-31 숭실대학교산학협력단 반도체칩 및 메모리 제어방법, 그리고 그 방법을 컴퓨터에서 실행시키기 위한 프로그램을 기록한 기록매체
KR20160061704A (ko) 2014-11-24 2016-06-01 삼성전자주식회사 페이지 상태 알림 기능이 있는 메모리 장치
US9601193B1 (en) 2015-09-14 2017-03-21 Intel Corporation Cross point memory control
US10068663B1 (en) 2017-05-30 2018-09-04 Seagate Technology Llc Data storage device with rewriteable in-place memory
US10090067B1 (en) 2017-05-30 2018-10-02 Seagate Technology Llc Data storage device with rewritable in-place memory
US10147501B1 (en) 2017-05-30 2018-12-04 Seagate Technology Llc Data storage device with rewriteable in-place memory
US11449431B2 (en) 2017-05-30 2022-09-20 Seagate Technology Llc Data storage device with rewritable in-place memory
JP7621132B2 (ja) * 2021-02-22 2025-01-24 キヤノン株式会社 メモリ制御回路およびその制御方法
CN116225977B (zh) * 2023-05-09 2023-08-11 中信建投证券股份有限公司 一种存储地址确定方法及电路系统

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US6104417A (en) * 1996-09-13 2000-08-15 Silicon Graphics, Inc. Unified memory computer architecture with dynamic graphics memory allocation
US5893917A (en) * 1996-09-30 1999-04-13 Intel Corporation Memory controller and method of closing a page of system memory
US5784582A (en) * 1996-10-28 1998-07-21 3Com Corporation Data processing system having memory controller for supplying current request and next request for access to the shared memory pipeline
US5940848A (en) * 1997-01-14 1999-08-17 Intel Corporation Computer system and method for efficiently controlling the opening and closing of pages for an aborted row on page miss cycle
US6112265A (en) * 1997-04-07 2000-08-29 Intel Corportion System for issuing a command to a memory having a reorder module for priority commands and an arbiter tracking address of recently issued command
US5969997A (en) * 1997-10-02 1999-10-19 International Business Machines Corporation Narrow data width DRAM with low latency page-hit operations
US6052134A (en) * 1997-12-22 2000-04-18 Compaq Computer Corp. Memory controller and method for dynamic page management
US6199145B1 (en) * 1998-02-27 2001-03-06 Intel Corporation Configurable page closing method and apparatus for multi-port host bridges
US6219765B1 (en) * 1998-08-03 2001-04-17 Micron Technology, Inc. Memory paging control apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7778103B2 (en) 2007-04-05 2010-08-17 Samsung Electronics Co., Ltd. Semiconductor memory device for independently selecting mode of memory bank and method of controlling thereof
KR101286643B1 (ko) * 2007-04-05 2013-07-22 삼성전자주식회사 독립적으로 뱅크의 모드를 선택하는 반도체 메모리 장치,메모리 컨트롤러 및 그 제어 방법
KR101121902B1 (ko) * 2010-06-22 2012-03-20 성균관대학교산학협력단 변경된 메모리 주소를 추적하는 트랜잭션 메모리 시스템 및 방법

Also Published As

Publication number Publication date
DE19983745B9 (de) 2012-11-08
WO2000029957A1 (en) 2000-05-25
GB0111924D0 (en) 2001-07-04
GB2359909A (en) 2001-09-05
GB2359909B (en) 2003-10-29
US6374323B1 (en) 2002-04-16
DE19983745B3 (de) 2012-10-25
JP2002530743A (ja) 2002-09-17
DE19983745T1 (de) 2002-03-28
CN1282925C (zh) 2006-11-01
CN1333891A (zh) 2002-01-30

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