KR20010082914A - method for manufacturing EEPROM devices - Google Patents

Abstract

PURPOSE: A method for fabricating an EEPROM(Electrically Erasable Programmable Read-Only Memory) device is to improve the operation speed of a memory cell by eliminating the step of a floating gate electrode. CONSTITUTION: An isolation layer(11) is formed on both sides of a semiconductor substrate(10) to define an active region of the semiconductor substrate. A gate oxide layer(15) is formed on the active region. An N+ tunnel ion implantation region(21) is formed by implanting N-type impurity ions into the active region. A tunnel oxide layer(20) is grown on a predetermined part of the N+ tunnel ion implantation region. A polysilicon layer for a floating gate electrode(31) is deposited on the entire surface of the semiconductor substrate including the tunnel oxide layer. A lower oxide layer(41) and an immediate nitride layer(43) are deposited on the polysilicon layer in this order. An insulating layer(40) consists of the lower oxide layer and the immediate nitride layer. An oxide layer for the first spacer(60) is deposited on the entire structure.

Description

Method for manufacturing EEPROM devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable programmable read-only memory (EEPROM) device, and more particularly, to a method for manufacturing an EEPROM device that achieves improved productivity while reducing integration gate step height.

Generally, EEPROMs are nonvolatile memory devices that are erased and programmed using electrical signals. Within the EEPROM are a number of memory cells, each of which can be individually erased and programmed. In general, each EEPROM cell has two transistors. For example, a floating gate tunnel oxide (FLOTOX) type EEPROM cell includes one sense transistor and one selection transistor. Select transistors in the EEPROM device are used to select individual EEPROM cells to be erased or programmed. Sense transistors in EEPROM devices are transistors that actually perform erase and program operations in individual cells. A phenomenon known as electron turnneling to program and erase a cell is used to store positive or negative charges, respectively, in the floating gate electrode of the sense transistor. Programming is accomplished by applying a positive voltage to the drain of the sense transistor while the control gate remains ground. Thus, electrons are tunneled from the floating gate of the sense transistor to the drain via the tunneling insulating film to make the floating gate positively charged. EEPROM cells are erased by storing negative charge in the floating gate. Negative charge storage on the floating gate is typically achieved by applying a positive voltage to the control gate of the transistor while grounding the drain and the source. This bias causes the electrons to tunnel from the drain through the tunneling insulating film to the floating gate, creating a negative charge in the floating gate.

Recently, in order to increase the memory capacity of the FLOTOX type EEPROM, the cell size of the EEPROM has been reduced as the density of the EEPROM increases. As a result, limitations in the manufacturing process, which are difficult to further reduce the small-sized turnnel region overlapping the active region, have started to appear. In order to overcome this limitation, EEPROM cells have been developed in the direction of shrinking the active region instead of shrinking the turnnel region. In a cell of a conventional EEPROM device, it is configured as shown in FIG. That is, an isolation layer 14 is formed in an inactive region to electrically isolate an active region of the semiconductor substrate 10 such as a silicon substrate, a tunnelel oxide film 20 is formed on a portion of the N + source region, and the tunnelel oxide film A floating gate 31 of polycrystalline silicon is formed on the 20, and an insulating film 40 is formed on the floating gate 31. An oxide film spacer 47 is formed on sidewalls of the floating gate 31 and the insulating layer 40, and the polysilicon layer 51 for the sense gate 50 on the floating gate 30 and on the floating gate 31 is formed thereon. Tungsten silicide layer 53 is formed. The insulating film 40 has an O / N / O (oxide / nitride / oxide) stacked structure and is formed of a lower oxide film 41, an interlayer insulating film 43, and an upper oxide film 45.

However, in the conventional EEPROM device configured as described above, since the floating gate 30 and the insulating film 40 thereon are formed in the same pattern by a photolithography process using the same photoresist pattern as a mask, the floating gate 30 ) Step becomes severe. This increases the possibility that a stringer of the polysilicon layer 51 is generated when forming the pattern of the polysilicon layer 51 for the sense gate 50 in a subsequent process. In addition, when the cell size is reduced for higher integration of the EEPROM device, the gap between the floating gates 30 becomes smaller, so that the shim 55 of the tungsten silicide layer 53 is located at the points between the floating gates 30. This bunch. As a result, the conventional EEPROM device has a problem that the word line has a high resistance and further, the operation speed of the memory cell is slow.

Accordingly, it is an object of the present invention to provide a method for manufacturing an EEPROM device to reduce the step of the floating gate electrode to improve the operating speed of the memory cell.

In addition, another object of the present invention is to provide a method for manufacturing an EEPROM device to improve the productivity by simplifying the manufacturing process.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional structural view of a main part for explaining a defect phenomenon in which a shim is generated in a tungsten silicide layer of a conventional electrically erasable programmable read-only memory (EEPROM) device.

2 is a layout diagram showing the main parts of a memory cell of the EEPROM device according to the present invention;

3 to 11 are process diagrams illustrating a method for manufacturing an EEPROM device cut along lines A-A and B-B of FIG. 2, respectively.

The manufacturing method of the EEPROM device according to the present invention for achieving the above object is

Forming an isolation layer in an inactive region of the semiconductor substrate to isolate the active region of the semiconductor substrate;

Forming a tunnel oxide on a portion of the active region;

Forming a lower gate oxide layer and an intermediate layer nitride layer for the floating gate and the O / N / O stacked structure on the tunneling oxide layer in the same pattern;

Exposing a surface of the active region while forming a first spacer of an insulating material on sidewalls of the floating gate, the lower oxide layer, and the intermediate layer nitride layer;

Forming an upper oxide layer for the O / N / O layered structure on the first spacer, the intermediate layer nitride layer, and the exposed active region; And

Forming a sense gate on the floating gate and interposing a select gate and a gate of the high voltage transistor on the exposed active region through the O / N / O layered film; It features.

Preferably, the step of forming the upper oxide film

Stacking the upper oxide film; And

Annealing the upper oxide film to form an upper oxide film on the active region as a gate oxide film of a high voltage transistor.

Further, the upper oxide film may be laminated to a thickness of 50 to 80 kPa, and then annealed to form a thickness of 300 to 400 kPa.

Accordingly, the present invention reduces the step height of the floating gate to prevent the formation of holes in the upper tungsten silicide layer of the sense gate and to prevent the formation of stringers in the lower polycrystalline silicon layer of the sense gate, thereby improving the operation speed of the memory cell. . In addition, while forming an upper oxide film having an O / N / O stacked structure, it is used as a gate oxide film of a high voltage transistor to improve process productivity.

Hereinafter, a method of manufacturing an EEPROM device according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part of the same structure and the same action as the conventional part.

2 is a layout diagram illustrating a main portion of a memory cell for an EEPROM device according to the present invention.

As shown in FIG. 2, the memory cell 100 of the EEPROM device includes an active region 12 and an inactive region of the isolation layer 11. The drain region 16 and the source region 18 of the memory cell are formed in the active region 12. A source / drain region 17 is formed in the active region 12 between the select gate 33 of the select transistor and the floating gate 31 of the sense transistor. The source / drain region 17 serves as a source for the high voltage select transistor and serves as a drain for the sense transistor. The memory cell 100 also includes a turnnel ion implantation region 21. The turnnel ion implantation region 21 overlaps the turnnel region 13 of the active region 12.

On the other hand, although only two floating gates are shown in the figure for convenience of description, it is obvious that more fluorating gates are disposed in practice.

Hereinafter, a method of manufacturing an EEPROM device according to the present invention will be described in detail with reference to FIGS. 3 to 11. Parts identical to those in FIG. 2 will be given the same reference numerals.

Referring to FIG. 3, first, a semiconductor substrate 10 of a P-type silicon material or another semiconductor material, for example, the memory cell 100 shown in FIG. Isolation layer 11 in the inactive region of memory cell 100 by a conventional method, such as a local oxidation of silicon (LOCOS) or shallow trench isolation (STI) process, to define the active region 12 of 100. To form. Thereafter, the gate oxide film 15 of the memory cell is formed on the active region 12 to a thickness of about 300 Å.

Referring to FIG. 4, after the formation of the gate oxide film 15 is completed, the photoresist layer 17 exposing a portion of the active region 12 for the turnnel ion implantation region 21 of FIG. 2 and masking the remaining portion. Is formed on the semiconductor substrate 10. Subsequently, N-type impurities such as phosphorus (P) are ion-implanted into the active region 12 by penetrating the oxide film 15 using the pattern of the photosensitive film 17 as a masking film, and then the N + turnnel ion implantation region 21. To form.

Referring to FIG. 5, after formation of the turnnel ion implantation region 21 is completed, the pattern of the remaining photoresist layer 17 is removed, and then a portion of the gate oxide layer 15 for the turnnel region 13 of FIG. 2 is exposed. And a pattern of the photosensitive film 19 for masking the remaining portion is formed on the semiconductor substrate 10. Subsequently, using the pattern of the photosensitive film 19 as a mask, the exposed portion of the gate oxide film 15 is etched until the ion implantation region 21 below it is exposed.

Referring to FIG. 6, after a portion of the ion implantation region 21 is exposed, the pattern of the photoresist layer 19 is removed, and then the tunneling oxide film 20 is formed to a thickness of about 70 μs on the exposed portion of the ion implantation region 21. To grow.

Referring to FIG. 7, after the growth of the turnnel oxide film 20 is completed, the polysilicon layer for the floating gate electrode 31 of FIG. 8 is formed on the entire surface of the semiconductor substrate 10 including the turnnel oxide film 20. 30) is laminated to a thickness of about 1000 mm ₃ and doped with a high concentration necessary for the floating gate using a dopant, for example, POCl ₃ . Subsequently, as shown in FIG. 10, the lower oxide film 41 and the intermediate layer nitride film 43 for the O / N / O stacked structure 40 are sequentially stacked on the polysilicon layer 30. Here, it is preferable that the lower layer oxide film 41 is laminated at a thickness of 40 to 60 kPa, and the intermediate layer nitride film 43 is laminated at a thickness of 90 to 120 kPa.

Referring to FIG. 8, after the stacking of the nitride film 43 is completed, as shown in FIG. 2 using a photolithography process, the polysilicon layer 30 and the oxide film of the portion for the floating gate 31 are formed. 41) and the nitride film 43 are formed in the same pattern, and the polysilicon layer 30, the oxide film 41, and the nitride film 43 of unnecessary portions are removed. Then, an oxide film 61 for the first spacer 60 of FIG. 9 is laminated on the entire surface of the semiconductor substrate 10 of the resultant structure to a thickness of 800 to 1200 Å. Of course, the oxide film 61 may be a high temperature oxide film (HTO) or an oxide film PEOX by a plasma enhanced CVD process, and a nitride film may be used in place of the oxide film 61.

Referring to FIG. 9, after lamination of the oxide film 61 is completed, the oxide film 61 is processed by an etch back process until the nitride film 43 and the gate oxide film 15 under the exposed portion are exposed to the floating gate ( 31, first spacers 60 are formed on sidewalls of the oxide film 41 and the nitride film 43. The first spacer 60 alleviates the step difference between adjacent floating gate electrodes 31.

Then, the gate oxide film 15 is wet etched until the surface of the active region 12 below is exposed, and then the semiconductor substrate 10 as well as the nitride layer 43, the first spacer 60, and the exposed active region. ), An oxide film for the upper oxide film 45 of the insulating film 40 is laminated to a thickness of 50 to 80 Å. Here, a high temperature oxide film, a medium temperature oxide film, or a low temperature oxide film can be used as the oxide film.

Subsequently, the oxide film is further annealed to form an upper oxide film 45 suitable for a gate oxide film of a high voltage transistor (not shown) disposed outside the memory cell, having a thickness of 300 to 400 kPa. This is because the oxide film immediately after the lamination has no problem as the upper oxide film of the O / N / O lamination structure, but is unsuitable as the gate oxide film of the high voltage transistor. In addition, the upper oxide film of the ONO stack structure is suitable as the upper oxide film because only a thickness of 20 to 40 kW is thick while the gate oxide film of the high voltage transistor grows to a thickness of 300 to 400 kW.

Therefore, in the present invention, since the gate oxide film of the high voltage transistor and the upper oxide film of the O / N / O lamination structure are formed into the same upper oxide film 45 by one process, it is possible to improve the productivity of the manufacturing process. In addition, since the first spacer 60 is formed on the sidewall of the floating gate 31 and then the upper oxide film 45 is formed thereon, the step difference of the floating gate 31 can be considerably reduced compared to the conventional art. Tungsten to be formed on the polysilicon layer 51 even if the memory cell size is reduced, almost eliminating the possibility of a stringer in forming the polysilicon layer 51 in a subsequent process for forming the sense gate 24 of FIG. This prevents the formation of the holes 55 in the silicide layer 53. Therefore, an increase in resistance of the word line can be prevented and an operating speed of the memory cell can be improved.

Referring to FIG. 10, after annealing of the upper oxide film 45 is completed, a conductive layer, for example, a lower polycrystalline silicon layer 51 and an upper tungsten silicide layer 53 are stacked on the upper oxide film 45. do. Here, even if the space between the adjacent floating gates is narrowed due to the reduction of the memory cell size, the holes 55 of the tungsten silicide layer 53 are not formed at the points therebetween. And the upper oxide film 45 alleviate the step of the floating gate 31. Meanwhile, various possible silicide layers may be used instead of the tungsten silicide layer 53.

Subsequently, the polysilicon layer 51 and the tungsten silicide layer 53 are formed by using a photolithography process, and as shown in FIG. 2, the floating gate 31 is connected to the sense gate 24 via the insulating film 40. The pattern is formed in a passing pattern, and the select gate 33 is formed in a pattern passing through the active region through the upper insulating layer 45. Although not shown in the drawings, the gate of the high voltage transistor is formed together with the upper insulating layer 45 in the active region located outside the memory cell.

Then, using the sense gate 24, the select gate 33, and the first spacer 60 as a mask, N-type impurities such as phosphorus (P) are ion-implanted in the active region at low concentration to select a transistor and A low concentration region N− for the source / drain regions of the sense transistor and the high voltage transistor is formed in the active region.

As shown in FIG. 11, after the formation of the low concentration region N− is completed, an oxide film for the second spacer 70 is stacked on the entire surface of the semiconductor substrate 10 having the resulting structure and etched back. To be processed. Therefore, the second spacer 70 is formed on the sidewalls of the polysilicon layer 51 and the tungsten silicide layer 53 of the sense gate 24, and also on the first spacer 60 via the upper oxide film 45. The second spacer 70 is formed, and the second spacer 70 is formed on the sidewalls of the polysilicon layer 51 and the tungsten silicide layer 53 of the selection gate 33. Of course, the second spacer 70 is also formed on the sidewall of the gate of the high voltage transistor.

Subsequently, in order to form a double junction structured source / drain region, ion implantation is performed at high concentration using N-type impurities into the active region using the first spacer 60, the second spacer 70, the sense gate and the selection gate as masks. Thus, the high concentration region N + surrounding the low concentration region N− is formed in the active region to complete the EEPROM device of the present invention.

As described above, according to the present invention, the polycrystalline silicon layer for the floating gate of the EEPROM device is laminated on the tunneling oxide film, and the lower oxide film and the intermediate layer nitride film for the O / N / O lamination structure are stacked thereon, It forms in the same pattern of a floating gate, and forms the 1st spacer in these side walls. Then, an oxide film is laminated and annealed on the surface of the intermediate layer nitride film, the first spacer and the active region to form an upper oxide film of an O / N / O stacked structure, and a gate oxide film of a high voltage transistor located outside the memory cell. do. Then, a sense gate is formed on the floating gate with an insulating film having an O / N / O layer structure, an upper oxide film is formed on the active region, and a selection gate and a gate of the high voltage transistor are formed together.

Accordingly, the present invention reduces the step height of the floating gate to prevent the generation of holes in the upper tungsten silicide layer of the sense gate between adjacent floating gates and to prevent the occurrence of stringers of the lower polysilicon layer for the sense gate. It reduces the resistance of the word line of the EEPROM device and further improves the operating speed of the memory cell. Further, while forming an upper oxide film having an O / N / O stacked structure on the intermediate nitride film, the gate oxide film of the high voltage transistor is simultaneously formed to improve productivity.

On the other hand, the present invention is described based on the preferred example shown in the drawings, but not limited to this and various modifications and improvements are possible by those skilled in the art to which the present invention belongs without departing from the spirit of the invention. Of course.

Claims (3)

Forming an isolation layer in an inactive region of the semiconductor substrate to isolate the active region of the semiconductor substrate; Forming a tunnel oxide on a portion of the active region; Forming a lower gate oxide layer and an intermediate layer nitride layer for the floating gate and the O / N / O stacked structure on the tunneling oxide layer in the same pattern; Exposing a surface of the active region while forming a first spacer of an insulating material on sidewalls of the floating gate, the lower oxide layer, and the intermediate layer nitride layer; Forming an upper oxide layer for the O / N / O layered structure on the first spacer, the intermediate layer nitride layer, and the exposed active region; And Forming a sense gate on the floating gate and interposing a select gate and a gate of the high voltage transistor on the exposed active region through the film of the O / N / O stacked structure; Method of manufacturing a pyrom element. The method of claim 1, wherein the forming of the upper oxide film Stacking an upper oxide film for the O / N / O stack structure; And And annealing an upper oxide film on the active region for the high voltage transistor to form a gate oxide film of the high voltage transistor. The method of claim 2, wherein the upper oxide film is laminated to a thickness of 50 to 80 kPa and annealed to form a thickness of 300 to 400 kPa.