KR20010081251A - In plane switching mode liquid crystal display device - Google Patents

Abstract

PURPOSE: An IPS(In Plane Switching) mode LCD is provided to form an array substrate for an LCD by using an IPS mode. CONSTITUTION: A thin film transistor(T) is formed on an intersection point of a gate line(111) and a data line(113). The thin film transistor(T) has a gate electrode(119), a source electrode(121), and a drain electrode(123). A common electrode(115) and a pixel electrode(117) of a finger shape are formed on a pixel region(P). The common electrode(115) is composed of the first common electrode(115a) of a vertical pattern and the second common electrode(115b) of a horizontal pattern. The pixel electrode(117) is composed of the first pixel electrode(117a) and the second pixel electrode(117b).

Description

In-plane switching mode liquid crystal display device

The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device using a transverse electric field system.

In general, a liquid crystal display device is formed by bonding an upper substrate and a lower substrate and injecting a liquid crystal between the upper substrate and the lower substrate.

A polarizer, a retardation film, and the like are attached to outer surfaces of the upper and lower substrates. By selectively configuring such a plurality of components, a liquid crystal display device having high brightness and contrast characteristics by changing a light propagation state or a refractive index is configured.

The liquid crystal cell used in recent years as a liquid crystal display device generally adopts a twisted nematic liquid crystal, and the twisted nematic liquid crystal has a property of varying the light transmittance in gradation display depending on the viewing angle, thereby limiting its large area.

The liquid crystal cell including the twisted nematic liquid crystal is symmetrically distributed in a wide range of light transmittance at the viewing angle in the left and right directions, but because the light transmittance is distributed asymmetrically in the up and down directions, the image is reversed in the up and down directions. There was a problem that a range occurs and the viewing angle is narrowed.

To solve this problem, in-plane switching (hereinafter referred to as "IPS mode") using a parallel electric field is contrast and gray inversion compared to the conventional twisted nematic liquid crystal mode. ), There is an advantage to improve the viewing angle characteristics such as color shift (color shift).

In the IPS mode, the pixel electrode and the common electrode are formed on the same plane on the thin film transistor array substrate, and the liquid crystal is operated by the horizontal electric field of the pixel electrode and the common electrode formed on the same substrate.

Hereinafter, the structure of the IPS mode will be described with reference to the accompanying drawings.

1 is a partial plan view of a conventional array substrate for an IPS mode liquid crystal display device.

As shown in the drawing, the gate wiring 11 and the data wiring 13 cross each other on the substrate, and the common electrode 15 is formed in parallel with the gate wiring 11 in one direction.

The gate wiring 11 and the data wiring 13 cross each other to define a pixel region P. The common electrode 15 and the pixel electrode 17 are formed in a finger shape on the pixel region P, respectively. Patterned into interlocking structures.

The vertical pattern of the common electrode 15 on the pixel region P is formed to protrude vertically from the common electrode 15 formed in parallel with the gate wiring 11.

The common electrode 15 and the pixel electrode 17 are formed on the pixel region P. In this case, the A and B portions and the gate wirings, which are indicated by dotted lines on both sides of the single pixel region P, are formed. 11) the C portion between the common electrode 15 and the common electrode and the pixel electrode do not correspond to each other unlike the center region of the pixel region, so that the liquid crystal molecules (not shown) located in this portion do not operate properly. do.

Such a state may cause a deterioration of the image quality of the liquid crystal display device, so this part should be shielded.

Accordingly, although not shown, a black matrix (not shown) is further formed at positions corresponding to the A, B, and C portions of the upper substrate bonded to the array substrate at predetermined intervals, whereby the preceding A, B, You need a process that covers the C part.

In addition, a thin film transistor T, which is a switching element, is formed at a point where the gate wiring 11 and the data wiring 13 cross each other. The thin film transistor T includes a gate electrode 19 protruding in one direction from the gate line 11 and a source electrode 21 protruding and extending from the data line 13 to the gate electrode 19. And a drain electrode 23 spaced apart from the predetermined distance and in contact with the pixel electrode 17.

A manufacturing process of the array substrate for an IPS mode liquid crystal display device having such a configuration will be described below with reference to FIGS. 2A to 2C.

2A to 2C are cross-sectional views taken along the lines II-II and III-III of FIG. 1.

First, as shown in FIG. 2A, a conductive metal such as aluminum (Al), aluminum alloy (Al alloy), chromium (Cr), molybdenum (Mo), or the like is deposited and patterned on the substrate 9 to form a gate wiring ( 11) of FIG. 1, the gate electrode 19, a horizontal pattern (15b of FIG. 1) parallel to the gate wiring in one direction, and a plurality of vertical protrusions extending vertically from the horizontal pattern (15b of FIG. 1). The common electrode 15 including the pattern (15a of FIG. 1) is formed.

Next, an insulating material such as a silicon oxide film (SiO ₂ ), a silicon nitride film (SiN _X ), or the like is deposited on the substrate 9 on which the gate electrode 19, the common electrode (15 of FIG. 1), and the like are formed. A first insulating layer, which is layer 18, is formed.

Next, as shown in FIG. 2B, amorphous silicon (a-Si) and amorphous silicon (n + a-Si) containing impurities are stacked on the gate insulating layer 18, and then patterned to form an active layer. 25 and the ohmic contact layer 27 are formed.

Next, the conductive metal is deposited and patterned on the entire surface of the substrate 9 on which the ohmic contact layer 27 is formed, and protrudes from the data wiring 13 and the data wiring to the gate electrode 19. The source electrode 21 and the drain electrode 23 spaced apart from each other are formed.

Next, a silicon nitride layer (SiN _x ) is deposited on the source and drain electrodes 21 and 23 to form a second insulating layer 29, and then patterned to form a drain contact on the drain electrode 23. The hole 31 is formed.

Next, as shown in FIG. 2C, a transparent conductive metal such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the substrate 9 on which the second insulating layer 29 is formed. Deposited and patterned to form a finger spaced apart from the plurality of vertical patterns 15a of the common electrode 15 formed on the pixel region (P of FIG. 1) by a predetermined interval, and one side of the drain contact hole 31 is formed. The pixel electrode 17 in contact with the drain electrode 23 is formed through the.

Through the above process, a conventional array substrate for an IPS liquid crystal display device can be constructed.

However, in the conventional arrangement of the array substrate for the IPS mode liquid crystal display device, since parasitic capacitance exists on the gate insulating layer and the second insulating layer interposed between the two electrodes by the plurality of common electrodes and the pixel electrode, The smooth driving requires high driving voltage considering the parasitic capacitance.

In addition, as shown in FIG. 2C, residual DC is formed by an insulating film between the common electrode 15 and the pixel electrode 17, thereby degrading image quality.

The aperture ratio is then lowered by a large number of opaque electrodes forming the transverse electric field. In addition, since the aperture ratio is low, the brightness of the backlight should be 3000cc / m2 or more in order to achieve an appropriate brightness, which affects the electrical characteristics of the thin film transistor, causing problems such as flicker or afterimage.

Accordingly, an object of the present invention is to fabricate an IPS mode liquid crystal display device having a high opening ratio.

1 is a partial plan view of a conventional array substrate for an IPS mode liquid crystal display device;

2A through 2C are cross-sectional views taken along the lines II-II and III-III of FIG. 1;

3 is a partial plan view of an array substrate for an IPS mode liquid crystal display device according to a first embodiment of the present invention;

4A to 4C are cross-sectional views taken along the lines IV-IV and V-V of FIG. 3;

5 is a partial plan view of an array substrate for an IPS mode liquid crystal display according to a second embodiment of the present invention.

<Brief description of symbols for the main parts of the drawings>

111: gate wiring 113: data wiring

115: common electrode 117: pixel electrode

119: gate electrode 121: source electrode

123: drain electrode

A transverse electric field liquid crystal display device for achieving the above object includes a substrate;

A gate wiring formed on the substrate; A data line crossing the gate line; A pixel region in which the gate wiring and the data wiring are defined to cross each other; A switching element positioned at an intersection point of the gate wiring and the data wiring; A pixel electrode on the pixel area, the pixel electrode including a plurality of vertical patterns and a horizontal pattern connecting the plurality of vertical patterns into one; A common electrode disposed on the same layer as the pixel electrode, connecting a plurality of vertical patterns spaced apart from each vertical pattern of the pixel electrode by a predetermined distance, and the vertical pattern into one, and a horizontal pattern positioned on the other side of the horizontal pattern of the pixel electrode; It includes.

Horizontal patterns of the common electrode and the pixel electrode may be positioned on the gate wiring, respectively.

Some vertical patterns of the common electrode may be formed on the data line.

According to an aspect of the present invention, there is provided a method of manufacturing a transverse electric field type liquid crystal display device, including forming a gate electrode and a gate electrode on a substrate; Forming a gate insulating layer on the gate electrode and the gate wiring; Forming a data line, a source electrode and a drain electrode on the gate insulating layer; Depositing a low dielectric material on the entire surface of the substrate on which the data line and the source electrode are formed to form a first insulating layer, and then patterning the first dielectric layer to form a drain contact hole; Depositing and patterning a conductive material on the first insulating layer to form a pixel electrode including a plurality of vertical patterns and a horizontal pattern connecting the plurality of vertical patterns into one, the same layer as the pixel electrode, and the pixel And connecting the plurality of vertical patterns spaced apart from each vertical pattern of the electrode by a predetermined distance and the vertical patterns into one, and forming a common electrode including a horizontal pattern positioned on the other side of the horizontal pattern of the pixel electrode.

The low dielectric material is characterized in that selected from the group of benzocyclobutene and acrylic resin.

Horizontal patterns of the common electrode and the pixel electrode may be formed on the gate wiring, respectively.

Some vertical patterns of the common electrode may be formed on the data line.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First Embodiment

According to the first embodiment of the present invention, a method of forming a common electrode and a pixel electrode on the data line after forming the insulating layer formed on the data line with a transparent organic insulating material having a low dielectric constant in the above-described configuration Suggest.

3 is a schematic plan view of an array substrate for an IPS mode liquid crystal display according to the present invention.

As shown in the drawing, the substrate is formed by crossing the gate wiring 111 and the data wiring 113, and at the point where the gate wiring 111 and the data wiring 113 intersect, the thin film transistor T, which is a switching element, is formed. It is composed.

As described above, the thin film transistor T includes a gate electrode 119, a source electrode 121, and a drain electrode 123.

The common electrode 115 and the pixel electrode 117 are formed in the shape of a finger on the pixel region P defined by the gate wiring 111 and the data wiring 113 intersecting with each other.

The finger-shaped common electrode 115 includes a first common electrode 115a which is the plurality of vertical patterns and a second common electrode 115b which is a horizontal pattern that integrates the plurality of first common electrodes into one. The gate wiring 111 is formed to be spaced apart from the predetermined distance.

The pixel electrode 117 formed to be engaged with the common electrode 115 may also have a second pixel electrode (H) which is a horizontal pattern in which the plurality of vertical patterns include the first pixel electrode 117a and the plurality of first pixel electrodes. 117b).

In this case, the common electrode 115 formed on the single pixel region P may be formed to overlap the data wiring 113 on the data wiring 113.

In this case, the liquid crystal molecules (not shown) positioned at both ends of the pixel region P are affected by the lateral electric field of the common electrode 115 and the pixel electrode 117 unlike the conventional art, thereby performing normal operation.

At least one of the common electrode and the pixel electrode may be formed of a transparent conductive film.

A process of an array substrate for an IPS mode liquid crystal display device having such a configuration will be described below with reference to FIGS. 4A to 4C.

4A to 4C are cross-sectional views taken along the lines IV-IV and V-V of FIG. 3.

First, as shown in FIG. 4A, the above-described conductive metal is deposited and patterned on the substrate 109 to form a gate wiring 111 (see FIG. 3) and a gate electrode 119.

Next, an inorganic insulating material such as a silicon nitride film (SiN _x ), a silicon oxide film (SiO ₂ ), or the like, in some cases, an acrylic resin and benzo on the entire surface of the substrate 109 on which the gate wiring 111 and the like are formed. A gate insulating layer 118 is formed by depositing an organic insulating material such as cyclobutene (BCB).

Next, as shown in FIG. 4B, pure amorphous silicon (a-Si) and amorphous silicon (n + a-Si) containing impurities are stacked on the substrate on which the gate insulating layer 118 is formed, and then patterned. The active layer 125 and the ohmic contact layer 127 are formed.

Next, the conductive metal is deposited and patterned on the substrate 109 on which the ohmic contact layer 127 is formed, thereby forming the data wiring 113, the source electrode 121, and the drain electrode 123.

Next, BCB, which is a low dielectric material 129, is deposited and patterned on the entire surface of the substrate 109 on which the drain electrode 123 and the like are formed, thereby forming a drain contact hole 131 on the drain electrode 123. .

In this case, the low dielectric material may be a material having a dielectric constant of 3 or less, such as acrylic resin, in addition to BCB.

4C illustrates a process of forming a common electrode and a pixel electrode, and includes a transparent conductive metal such as indium tin oxide, indium zinc oxide, aluminum (Al), molybdenum (Mo), chromium (Cr), or an alloy thereof. An opaque conductive metal or the like is selected, deposited, and patterned to form a finger-shaped common electrode 115 and a pixel electrode 117 which are spaced apart from each other at predetermined intervals. 115a) and the vertical pattern 117a of the pixel electrode 117)

The second common electrode 115b of the horizontal pattern which integrates the first common electrode 115a, which is the plurality of vertical patterns, of the finger-shaped common electrode 115 into one is spaced apart from the gate wiring 111 in FIG. To form spaced apart.

In the liquid crystal display according to the present invention formed as described above, by depositing a low dielectric material such as BCB on the data wiring 113, parasitic capacitances formed between the wirings may be minimized, and thus, up to the upper portion of the data wiring 113. The common electrode 115a may be formed.

Second Embodiment

The second embodiment according to the present invention is a modified example of the first embodiment.

5 is a partial plan view of an array substrate for an IPS mode liquid crystal display according to a second embodiment of the present invention.

As shown in the drawing, the second common electrode 115b, which is a horizontal pattern of the common electrode 115 that is simultaneously patterned and parallel to the gate wiring 111, is formed on the gate wiring 111 in the above-described configuration of the first embodiment. A second pixel electrode 117b formed on the upper side and integrating the first pixel electrode 117a as a vertical pattern of the pixel electrode 117 spaced apart from the first common electrode 115a as a vertical pattern into one; ) Is also formed on the gate wiring 111.

Since the wiring structure does not have a malfunction region of the liquid crystal on the pixel region, it is not necessary to form a black matrix to cover the malfunction region, and thus the aperture ratio can be further improved.

Accordingly, the array substrate for the IPS mode liquid crystal display device according to the present invention does not have a malfunction region of liquid crystal molecules in a single pixel region, and thus does not have to form a black matrix formed on the upper substrate in correspondence with a malfunction region of a liquid crystal. First, there is an effect that can obtain a high opening rate.

In addition, since the common electrode and the pixel electrode are formed on the same layer in the configuration according to the first and second embodiments, there is no nonuniformity between the electrodes or an insulating film between the common electrode and the pixel electrode. Residual DC caused is also reduced, thereby improving image quality.

In addition, since there is no parasitic capacitance between the common electrode and the pixel electrode, the third driving voltage does not need to be applied in consideration of the parasitic capacitance, and since the aperture ratio is improved, the brightness of the backlight can be lowered, thereby reducing power consumption. There is.

Claims (3)

A substrate; A gate wiring formed on the substrate; A data line crossing the gate line; A pixel region in which the gate wiring and the data wiring are defined to cross each other; A switching device positioned at the intersection of the gate wiring and the data wiring; A pixel electrode disposed on the pixel area, the horizontal pattern connecting the plurality of vertical patterns and the plurality of vertical patterns into one, wherein the horizontal pattern is formed on the gate wiring; A plurality of vertical patterns disposed on the same layer as the pixel electrode and spaced apart from each vertical pattern of the pixel electrode by a predetermined distance, and a vertical pattern positioned on the other side of the horizontal pattern of the pixel electrode; The vertical pattern is a common electrode formed on the pixel region and the data wiring. Transverse electric field type liquid crystal display device comprising a. Forming a gate wiring and a gate electrode on the substrate; Forming a gate insulating layer on the gate electrode and the gate wiring; Forming an active layer in an island shape on the gate electrode; Forming a data line, a source electrode and a drain electrode on the gate insulating layer on which the active layer is formed; Depositing a low dielectric material on the entire surface of the substrate on which the data line and the source electrode are formed to form a first insulating layer, and then patterning the first dielectric layer to form a drain contact hole; A pixel electrode including a plurality of vertical patterns and a horizontal pattern connecting the plurality of vertical patterns to one on the first insulating layer, and formed on the same layer as the pixel electrode, and each of the vertical patterns of the pixel electrode Connecting a plurality of vertical patterns spaced apart from each other and the vertical pattern to form a common electrode including a horizontal pattern positioned on the other side of the horizontal pattern of the pixel electrode; Method for manufacturing a transverse electric field type liquid crystal display device comprising. The method of claim 2, And said low dielectric material is selected from the group of benzocyclobutene and acrylic resin.