KR20010069008A - The method of forming an contact hole in semiconductor devices - Google Patents
The method of forming an contact hole in semiconductor devices Download PDFInfo
- Publication number
- KR20010069008A KR20010069008A KR1020000001204A KR20000001204A KR20010069008A KR 20010069008 A KR20010069008 A KR 20010069008A KR 1020000001204 A KR1020000001204 A KR 1020000001204A KR 20000001204 A KR20000001204 A KR 20000001204A KR 20010069008 A KR20010069008 A KR 20010069008A
- Authority
- KR
- South Korea
- Prior art keywords
- interlayer insulating
- contact hole
- etching
- layer
- insulating film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000010410 layer Substances 0.000 claims abstract description 75
- 239000011229 interlayer Substances 0.000 claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 abstract description 2
- 238000001039 wet etching Methods 0.000 description 11
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로, 보다 상세하게는 반도체 장치의 콘택 홀 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device.
반도체 장치에서 상하부의 반도체 소자들을 전기적으로 연결하기 위하여 콘택(contact)이 형성된다. 상기 콘택은 반도체 장치 구조물의 형성과 함께 적층되는 다층의 절연막을 통하여 형성된다. 이때 상기 반도체 장치 구조물이란, 트랜지스터, 캐패시터 등의 반도체 소자들이 형성되어 이루어지는 구조물을 가리킨다.In the semiconductor device, contacts are formed to electrically connect upper and lower semiconductor elements. The contact is formed through a multilayer insulating film that is stacked with the formation of a semiconductor device structure. In this case, the semiconductor device structure refers to a structure in which semiconductor elements such as transistors and capacitors are formed.
한편 반도체 장치는 점차 고집적화되어 형성되며, 반도체 장치의 일정 셀(cell) 면적상에는 다수의 반도체 소자들이 고밀도로 형성된다. 이와 같이 반도체 장치의 고집적화에 따라 반도체 소자들의 평면적인 크기는 작아지는 반면, 반도체 소자들의 높이는 증가하게 된다.Meanwhile, semiconductor devices are gradually formed to be highly integrated, and a plurality of semiconductor devices are formed at a high density on a predetermined cell area of the semiconductor device. As the semiconductor device is highly integrated, the planar size of the semiconductor devices may be reduced while the height of the semiconductor devices is increased.
반도체 장치의 고집적화에 따라 반도체 소자들의 높이가 증가하면서, 반도체 소자들을 상하부로 연결하는 콘택의 높이도 증가한다. 이와 같이 콘택의 높이가 증가함에 따라 콘택의 종횡비(aspect ratio), 즉 콘택의 가로 길이에 대한 세로 길이의 비가 증가한다. 따라서 콘택을 위하여 콘택 홀(contact hole)을 형성하고 상기 콘택 홀 내부에 도전물을 채우는 콘택 공정 진행시, 콘택 홀을 채워서 콘택을 이루는데 어려움이 발생한다. 이러한 콘택 공정의 어려움을 해소하기 위하여, 콘택 홀을 형성할 때 콘택 홀의 상부를 습식 식각하여 콘택의 오프닝 부위를 와인 글래스(wine-glass) 형태로 형성함으로써 콘택의 종횡비를 낮추고, 스텝 커버리지(step coverage) 특성을 향상시키는 방법을 일반적으로 사용한다.As the height of semiconductor devices increases, the height of the semiconductor devices increases, and the height of the contact connecting the semiconductor devices to the upper and lower parts also increases. As the height of the contact increases, the aspect ratio of the contact, that is, the ratio of the vertical length to the horizontal length of the contact increases. Therefore, in the process of forming a contact hole for contact and filling a conductive material in the contact hole, it is difficult to form a contact by filling the contact hole. In order to solve the difficulty of the contact process, when forming the contact hole by wet etching the upper portion of the contact hole to form the opening portion of the contact in the form of wine glass (wine-glass) to lower the aspect ratio of the contact, step coverage (step coverage) The method of improving the characteristics is generally used.
그런데 상술한 방법에 의하여 습식 식각되는 다층의 층간 절연막 사이에 식각율의 차이가 있는 경우, 예를 들면, 상부 층간 절연막과 비교하여 하부 층간 절연막이 습식 식각율이 매우 큰 FOX(Flowable OXide) 등의 산화막으로 형성되는 경우에는 공정 진행중 하부 층간 절연막까지 식각이 진행되어 공정 불량이 발생할 수 있다.However, when there is a difference in etching rate between the multilayer interlayer insulating layers wet-etched by the above-described method, for example, compared to the upper interlayer insulating layer, the lower interlayer insulating layer has a very high wet etching rate, such as FOX (Flowable Oxide). In the case where the oxide layer is formed, etching may proceed to the lower interlayer insulating layer during the process, and process defects may occur.
도 1a 내지 도 1b는 종래 방법에 따른 반도체 장치의 콘택 홀 형성 공정의 문제점을 보여주기 위한 단면도들이다.1A to 1B are cross-sectional views illustrating problems of a contact hole forming process of a semiconductor device according to a conventional method.
도 1a에 있어서, 반도체 기판(100)상에 상부 층간 절연막(102d), 하부 층간 절연막(102c)을 포함하는 다층 절연막(102)을 형성한다. 상기 상부 층간 절연막(102d)은 산화막 또는 질화막으로 형성될 수 있으며, 상기 하부 층간 절연막(102c)은 상기 상부 층간 절연막(102d)에 비하여 습식 식각율이 상대적으로 높은 FOX와 같은 산화막으로 형성된다. 상기 FOX는 무기 SOG 계열의 산화막을 포함하며, 유동성이 좋은 산화막으로 널리 알려져 있다. 따라서 상기 FOX는 반도체 장치를 포함하는 구조물과 반도체 기판 사이의 단차로 인하여 발생하는 문제, 예를 들면 단차로 인한 평탄화 공정의 어려움 등을 해소하기 위하여 층간 절연막으로 널리 사용된다. 상기 상부 층간 절연막(102d)은 콘택 홀의 오프닝 부위를 습식 식각할때, 상기 하부 층간 절연막(102c)의 과도 식각을 방지하고 습식 식각량을 제어하기 위하여 두껍게 형성한다.In FIG. 1A, a multilayer insulating film 102 including an upper interlayer insulating film 102d and a lower interlayer insulating film 102c is formed on a semiconductor substrate 100. The upper interlayer insulating film 102d may be formed of an oxide film or a nitride film, and the lower interlayer insulating film 102c may be formed of an oxide film such as FOX having a higher wet etch rate than the upper interlayer insulating film 102d. The FOX includes an inorganic SOG-based oxide film and is widely known as an oxide film having good fluidity. Therefore, the FOX is widely used as an interlayer insulating film to solve a problem caused by a step between a structure including a semiconductor device and a semiconductor substrate, for example, a difficulty in planarization due to the step. The upper interlayer insulating layer 102d is formed thick to prevent excessive etching of the lower interlayer insulating layer 102c and to control the wet etching amount when the opening portion of the contact hole is wet etched.
상기 다층 절연막(102)상에 포토레지스트(photoresist, 이하 PR)을 도포하고 패터닝하여 PR 마스크(108)를 형성한다. 이때 상기 PR 마스크(108)의 오픈 영역은 후속 콘택의 폭을 결정하게 된다.A photoresist (PR) is applied and patterned on the multilayer insulating layer 102 to form a PR mask 108. The open area of the PR mask 108 then determines the width of subsequent contacts.
도 1b에 있어서, 상기 PR 마스크(108)를 식각 마스크(mask)로 하여 상기 다층 절연막(102)을 순차적으로 식각한다. 이때 상기 상부 층간 절연막(102d)의 식각은 콘택 홀의 오프닝(opening, 110) 부위 형성을 위하여 습식 식각으로 진행된다.In FIG. 1B, the multilayer insulating film 102 is sequentially etched using the PR mask 108 as an etch mask. In this case, etching of the upper interlayer insulating layer 102d is performed by wet etching to form an opening (110) of the contact hole.
그런데 상기 상부 층간 절연막(102d)을 습식 식각하여 콘택 홀의 오프닝 부위를 형성할 때, 과도한 식각을 방지하도록 식각량 제어를 위하여 상기 상부 층간 절연막(102d)을 두껍게 형성한다. 이러한 경우에 상기 다층 절연막(102)의 전체적인 두께가 증가되어 콘택의 높이가 커져서 콘택 형성을 위한 식각 공정시, 콘택 홀이 불완전하게 형성되는 등의 문제점이 발생한다.However, when the upper interlayer insulating layer 102d is wet-etched to form the opening portion of the contact hole, the upper interlayer insulating layer 102d is formed thick to control the etching amount so as to prevent excessive etching. In this case, the overall thickness of the multilayer insulating layer 102 is increased, so that the height of the contact increases, so that a contact hole is incompletely formed during an etching process for forming a contact.
또한 상기 상부 층간 절연막(102d)의 식각시 공정 조건이 불안정하거나 공정 조건이 변화되는 경우 도 1b의 Ⅰ부위에 도시된 바와 같이 원치 않는 하부 층간 절연막(102c)까지 식각되는 경우가 발생한다. 이때 상기 상부 층간 절연막(102d)에 비하여 상기 하부 층간 절연막(102c)의 습식 식각율이 큰 경우, 상기 하부 층간 절연막(102c)이 과도하게 식각되어 공정 불량이 발생하며, 이에 따라 콘택 형성이 어려워지는 문제가 발생한다.In addition, when the process conditions are unstable or the process conditions are changed during the etching of the upper interlayer insulating film 102d, the unwanted interlayer insulating film 102c may be etched as shown in part I of FIG. 1B. In this case, when the wet etch rate of the lower interlayer insulating layer 102c is larger than that of the upper interlayer insulating layer 102d, the lower interlayer insulating layer 102c is excessively etched, resulting in poor process, thereby making contact formation difficult. A problem arises.
본 발명은 상술한 종래 기술에서의 문제점을 해소하기 위하여 식각 정지막을 포함하는 다층의 층간 절연막을 통하여 습식 식각량을 제어하면서 콘택 홀을 형성할 수 있는 새로운 반도체 장치의 콘택 홀 형성 방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention provides a method for forming a contact hole in a new semiconductor device capable of forming a contact hole while controlling the wet etching amount through a multilayer interlayer insulating film including an etch stop film in order to solve the above-described problems in the related art. The purpose.
도 1a 내지 도 1b는 종래 방법에 따른 반도체 장치의 콘택 홀 형성 공정의 문제점을 보여주기 위한 단면도들이다.1A to 1B are cross-sectional views illustrating problems of a contact hole forming process of a semiconductor device according to a conventional method.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 장치의 콘택 홀 형성 공정을 순차적으로 나타내는 단면도들이다.2A through 2C are cross-sectional views sequentially illustrating a process of forming a contact hole in a semiconductor device according to an embodiment of the present invention.
*도면의 주요 부분에 대한 간단한 설명* Brief description of the main parts of the drawing
100, 300 : 반도체 기판 102c, 306 : 하부 층간 절연막100, 300: semiconductor substrate 102c, 306: lower interlayer insulating film
102d, 310 : 상부 층간 절연막 308 : 식각 정지막102d and 310: Upper interlayer insulating film 308: Etch stop film
102a, 102b, 302, 304, : 잔여 절연막102a, 102b, 302, 304,: residual insulating film
108, 312 : PR 마스크 110, 314a : 콘택 오프닝108, 312: PR mask 110, 314a: contact opening
314b : 콘택 홀314b: contact hole
상기 목적을 달성하기 위한 본 발명에 따른 반도체 메모리 장치의 콘택 홀형성 방법은, 먼저 반도체 기판상에 하부 층간 절연막, 식각 정지막 및 상부 층간 절연막을 포함하는 다층 절연막을 형성한다. 상기 다층 절연막상에 포토레지스트 마스크를 형성하고, 상기 포토레지스트 마스크를 식각 마스크로 하여 상기 식각 정지막이 노출되도록 상기 상부 층간 절연막을 포함하는 상기 다층 절연막을 식각한다. 그리고, 상기 식각 정지막, 하부 층간 절연막 및 잔여 절연막층들을 연속으로 식각하여 상기 반도체 기판이 드러나도록 콘택 홀을 형성한다.In the method of forming a contact hole in a semiconductor memory device according to the present invention for achieving the above object, first, a multilayer insulating film including a lower interlayer insulating film, an etch stop film, and an upper interlayer insulating film is formed on a semiconductor substrate. A photoresist mask is formed on the multilayer insulating film, and the multilayer insulating film including the upper interlayer insulating film is etched to expose the etch stop layer by using the photoresist mask as an etching mask. The etch stop layer, the lower interlayer insulating layer, and the remaining insulating layer are sequentially etched to form contact holes to expose the semiconductor substrate.
본 발명의 바람직한 실시예에 따르면, 상기 하부 층간 절연막은 상기 상부 층간 절연막에 비해 큰 습식 식각율을 가지는 물질로 형성하는 것이 바람직하다.According to a preferred embodiment of the present invention, the lower interlayer insulating film is preferably formed of a material having a larger wet etch rate than the upper interlayer insulating film.
본 발명의 바람직한 실시예에 따르면, 상기 식각 정지층은 실리콘 질화막으로 형성하는 것이 바람직하다.According to a preferred embodiment of the present invention, the etch stop layer is preferably formed of a silicon nitride film.
(실시예)(Example)
이하 도면을 참조하면서 본 발명의 실시예에 따른 반도체 장치의 콘택 홀 형성 방법을 상세히 살펴보기로 한다.Hereinafter, a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 장치의 콘택 홀 형성 공정을 순차적으로 나타내는 단면도들이다.2A through 2C are cross-sectional views sequentially illustrating a process of forming a contact hole in a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(300)상에 하부 층간 절연막(306), 식각 정지막(308) 및 상부 층간 절연막(310)을 포함하는 다층 절연막(314)을 형성한다. 상기 상부 층간 절연막(310)은 산화막 또는 질화막으로 형성될 수 있으며, 상기 하부 층간 절연막(306)은 상기 상부 층간 절연막(310)에 비하여 습식 식각율이 상대적으로 높은 FOX와 같은 산화막으로 형성된다. 상기 FOX는 무기 SOG 계열의 산화막을 포함하며, 유동성이 좋은 산화막으로 널리 알려져 있다. 한편 상기 상부 층간 절연막(310)은 콘택 홀 형성시에 발생하는 상술한 문제점들을 해소하기 위하여 적은 두께로 형성되는 것이 바람직하다. 본 발명에서는 상기 식각 정지막(308)을 형성함에 따라 상기 상부 층간 절연막(310)의 과도 식각을 방지할 수 있으므로, 상기 상부 층간 절연막(310)를 얇게 형성할 수 있다. 따라서 전체적인 다층 절연막(314)의 높이를 줄여 후속으로 형성되는 콘택의 높이를 줄일 수 있게 된다.Referring to FIG. 2A, a multilayer insulating layer 314 including a lower interlayer insulating layer 306, an etch stop layer 308, and an upper interlayer insulating layer 310 is formed on the semiconductor substrate 300. The upper interlayer insulating layer 310 may be formed of an oxide layer or a nitride layer, and the lower interlayer insulating layer 306 may be formed of an oxide layer such as FOX having a higher wet etching rate than the upper interlayer insulating layer 310. The FOX includes an inorganic SOG-based oxide film and is widely known as an oxide film having good fluidity. On the other hand, the upper interlayer insulating layer 310 is preferably formed with a small thickness in order to solve the above-described problems that occur when forming the contact hole. In the present invention, as the etch stop layer 308 is formed, the over-etching of the upper interlayer insulating layer 310 can be prevented, so that the upper interlayer insulating layer 310 can be formed thin. Therefore, by reducing the height of the overall multilayer insulating film 314 it is possible to reduce the height of the subsequently formed contact.
상기 식각 정지막은 실리콘 질화막(SiN)을 사용하며, 상기 실리콘 질화막은 500Å 이하의 두께로 형성한다. 상기 식각 정지막으로 실리콘 산화 질화막(SiON)을 사용할 수도 있으며, 상기 실리콘 산화 질화막의 두께는 500Å 이하의 두께로 형성할 수도 있다.The etch stop layer uses a silicon nitride layer (SiN), and the silicon nitride layer is formed to a thickness of 500 Å or less. A silicon oxynitride layer (SiON) may be used as the etch stop layer, and the silicon oxynitride layer may be formed to a thickness of 500 kPa or less.
상기 다층 절연막(314)상에 포토레지스트(photoresist, 이하 PR)을 도포하고 패터닝하여 PR 마스크(312)를 형성한다. 이때 상기 PR 마스크(312)의 오픈 영역은 후속 콘택의 폭을 결정하게 된다.A PR mask 312 is formed by applying and patterning a photoresist (PR) on the multilayer insulating layer 314. At this time, the open area of the PR mask 312 determines the width of the subsequent contact.
도 2b를 참조하면, 상기 PR 마스크(312)를 식각 마스크(mask)로 하여 상기 상부 층간 절연막(310)을 식각한다. 상기 상부 층간 절연막(310)의 식각은 콘택 홀의 오프닝(opening, 314a) 부위 형성을 위하여 습식 식각으로 진행된다. 이때 습식 식각은 불산(HF)를 에천트로 사용하며, 이 경우에 상기 상부 층간 절연막(310)과 상기 하부 층간 절연막(306) 사이에는 1:10 이상의 식각율 차이를 가지는 것이 바람직하다. 또한 상기 상부 층간 절연막(310)의 습식 식각 공정은 상기 식각 정지막(308)이 노출될 때까지 진행할 수도 있고, 상기 식각 정지막(308)이 노출되지 않도록 진행할 수도 있으므로 습식 식각량의 제어가 용이해지고 습식 식각 공정 마진을 증가시킬 수 있게 된다.Referring to FIG. 2B, the upper interlayer insulating layer 310 is etched using the PR mask 312 as an etch mask. Etching of the upper interlayer insulating layer 310 is performed by wet etching to form an opening (314a) of the contact hole. At this time, the wet etching uses hydrofluoric acid (HF) as an etchant. In this case, it is preferable to have an etching rate difference of 1:10 or more between the upper interlayer insulating layer 310 and the lower interlayer insulating layer 306. In addition, the wet etching process of the upper interlayer insulating layer 310 may proceed until the etch stop layer 308 is exposed, or the etch stop layer 308 may proceed so that the etch stop layer 308 is not exposed. And increase the wet etching process margin.
도 2c를 참조하면, 상기 콘택 홀 오프닝(314a)를 통하여 상기 식각 정지막(308), 하부 층간 절연막(306) 및 잔여 절연막층(304, 302)들을 반도체 기판의 활성 영역이 노출되도록 연속적으로 식각하여 콘택 홀(314b)을 형성한다. 이때 상기 식각 정지막(308), 하부 층간 절연막(306) 및 잔여 절연막층(304, 302)들의 식각은 건식 식각을 통하여 진행된다.Referring to FIG. 2C, the etch stop layer 308, the lower interlayer insulating layer 306, and the remaining insulating layer layers 304 and 302 are continuously etched through the contact hole opening 314a to expose the active region of the semiconductor substrate. To form a contact hole 314b. In this case, the etching of the etch stop layer 308, the lower interlayer insulating layer 306, and the remaining insulating layer layers 304 and 302 may be performed through dry etching.
본 발명에 따르면, 다층의 층간 절연막을 통하여 콘택 홀을 형성할 때, 콘택의 종횡비를 일정하게 유지하거나 감소시키는 동시에, 층간 절연막간의 식각율 차이로 인하여 발생하는 하부 층간 절연막의 과도 식각 현상을 방지할 수 있다. 또한 콘택의 위치 또는 밀도에 따라 달라지는 습식 식각량을 일정하게 유지하여 일정한 깊이의 콘택을 형성할 수 있게 되므로 공정의 신뢰성을 확보할 수 있다.According to the present invention, when forming the contact hole through the multilayer interlayer insulating film, the aspect ratio of the contact is kept constant or reduced, and at the same time, the excessive etching of the lower interlayer insulating film caused by the difference in the etch rate between the interlayer insulating films can be prevented. Can be. In addition, by maintaining a constant amount of wet etching according to the location or density of the contact to form a constant depth of contact can ensure the reliability of the process.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000001204A KR20010069008A (en) | 2000-01-11 | 2000-01-11 | The method of forming an contact hole in semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000001204A KR20010069008A (en) | 2000-01-11 | 2000-01-11 | The method of forming an contact hole in semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010069008A true KR20010069008A (en) | 2001-07-23 |
Family
ID=19637848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000001204A KR20010069008A (en) | 2000-01-11 | 2000-01-11 | The method of forming an contact hole in semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010069008A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100469345B1 (en) * | 2001-11-22 | 2005-02-02 | 엘지.필립스 엘시디 주식회사 | Method for Manufacturing Liquid crystal display panel |
-
2000
- 2000-01-11 KR KR1020000001204A patent/KR20010069008A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100469345B1 (en) * | 2001-11-22 | 2005-02-02 | 엘지.필립스 엘시디 주식회사 | Method for Manufacturing Liquid crystal display panel |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6239022B1 (en) | Method of fabricating a contact in a semiconductor device | |
| KR20010077518A (en) | Method of forming self-aligned contact structure in semiconductor integrated circuit device | |
| KR20000013720A (en) | Contact window fabrication method of semiconductor device | |
| JP2000307001A (en) | Manufacture of semiconductor device | |
| US6103608A (en) | Method of forming a contact window | |
| KR100366634B1 (en) | Method for manufacturing semiconductor device | |
| KR20010069008A (en) | The method of forming an contact hole in semiconductor devices | |
| US20080153289A1 (en) | Method for manufacturing semiconductor devices and plug | |
| KR20040038049A (en) | Method of forming contact in semiconductor device | |
| JPH10209402A (en) | Semiconductor element and its manufacturing method | |
| KR20060113264A (en) | Method for manufacturing semiconductor device | |
| KR100271660B1 (en) | Method of fabricating inter isolation film of semiconductor device | |
| KR100451989B1 (en) | A method for forming a metal line of semiconductor device | |
| KR100372770B1 (en) | A method of manufacturing self align contact of semiconductor device | |
| KR19980014993A (en) | Method of forming a contact hole in a semiconductor device | |
| KR0166031B1 (en) | Capacitor fabrication method of semiconductor device | |
| KR100265010B1 (en) | Method of forming a contact hole in a semiconductor device | |
| KR20060113271A (en) | Method for manufacturing semiconductor device | |
| KR20030058636A (en) | A method for forming of a semiconductor device | |
| KR20050116665A (en) | Method for fabricating semiconductor device | |
| KR20010045128A (en) | Forming method for self aligned contact of semiconductor device | |
| KR19990074636A (en) | Contact formation method of semiconductor device | |
| KR20030015703A (en) | Structure Of Dielectric Layer In Multilevel Interconnection And Method Of Forming The Same | |
| JPH10261714A (en) | Manufacture of semiconductor device | |
| JP2000101043A (en) | Semiconductor device and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |