KR20060113271A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20060113271A
KR20060113271A KR1020050036553A KR20050036553A KR20060113271A KR 20060113271 A KR20060113271 A KR 20060113271A KR 1020050036553 A KR1020050036553 A KR 1020050036553A KR 20050036553 A KR20050036553 A KR 20050036553A KR 20060113271 A KR20060113271 A KR 20060113271A
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spacer
gate
forming
insulating film
film
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Korean (ko)
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황창연
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to improve manufacturing yield and to stabilize process by improving etch margin of SAC(Self-Aligned Contact) etching without increasing aspect ratio. A gate line is formed on a substrate(21). An etch stop layer(25) is formed on the resultant structure. A first spacer insulating layer(26a) having overhang profile is formed on the etch stop layer. A second spacer insulating layer(27a) is formed on the first spacer insulating layer. A gate spacer(GS) is formed by etching the second and the first spacer insulating layer using different etch selectivity. An interlayer dielectric(28) is filled between the gate lines. A landing plug contact hole is formed to expose the substrate by SAC etching of the interlayer dielectric and the etch stop layer. Then, a landing plug contact(29) is filled in the landing plug contact hole.

Description

반도체장치의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도 1은 종래기술에 따른 반도체장치의 제조 방법을 간략히 도시한 도면,1 is a view briefly showing a method of manufacturing a semiconductor device according to the prior art;

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체장치의 제조 방법을 도시한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 게이트산화막21 semiconductor substrate 22 gate oxide film

23 : 게이트전극 24 : 게이트하드마스크질화막23 gate electrode 24 gate hard mask nitride film

25 : 제1질화막 26 : 제2질화막25: first nitride film 26: second nitride film

27 : 산화막 28 : 층간절연막27 oxide film 28 interlayer insulating film

29 : 랜딩플러그콘택29: Landing Plug Contact

본 발명은 반도체 제조 기술에 관한 것으로, 특히 자기정렬콘택식각공정을 이용한 반도체장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device using a self-aligned contact etching process.

일반적으로 반도체소자 제조시 트랜지스터의 소스/드레인에 연결된 콘택(contact)을 통해 캐패시터 및 비트라인과의 전기적 동작이 가능하다.In general, in the manufacture of semiconductor devices, electrical contact with a capacitor and a bit line is possible through a contact connected to a source / drain of a transistor.

최근에 반도체 소자의 집적도가 증가함에 따라 게이트라인과 같은 전도라인 간의 간극이 좁아지고 있으며, 이에 따라 콘택 공정 마진이 줄어들고 있다. 이러한 콘택 공정 마진을 확보하기 위하여 자기정렬콘택(Self Aligned Contact; SAC) 공정을 진행하고 있다. Recently, as the degree of integration of semiconductor devices increases, the gap between conductive lines such as gate lines has narrowed, and thus, contact process margins have decreased. In order to secure such a contact process margin, a self aligned contact (SAC) process is being performed.

그리고, 최근에는 반도체장치가 고집적화되면서 반도체장치 제조 공정시 종횡비(Aspect ratio)는 점점 증가하게 된다.In recent years, as semiconductor devices have been highly integrated, aspect ratios have gradually increased in the semiconductor device manufacturing process.

도 1은 종래기술에 따른 반도체장치의 제조 방법을 간략히 도시한 도면이다.1 is a view briefly illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1에 도시된 바와 같이, 반도체 기판(11) 상에 게이트산화막(12)을 형성하고, 게이트산화막(12) 상에 게이트전극(13)과 게이트하드마스크질화막(14)을 적층한 후 게이트패터닝을 진행하여 게이트전극(13)과 게이트하드마스크질화막(14)의 순서로 적층된 게이트라인을 형성한다.As shown in FIG. 1, the gate oxide film 12 is formed on the semiconductor substrate 11, the gate electrode 13 and the gate hard mask nitride film 14 are stacked on the gate oxide film 12, and then gate patterning is performed. Proceeding to form a gate line stacked in the order of the gate electrode 13 and the gate hard mask nitride film (14).

이어서, 게이트스페이서로 사용되는 LP 질화막(Low Pressure Chemical Vapor Deosition Nitride) 증착 및 스페이서식각(Spacer etch)을 진행하여 게이트라인의양측벽에 접하는 게이트스페이서(15)를 형성한다.Subsequently, an LP nitride film used as a gate spacer is deposited and spacer etched to form a gate spacer 15 that contacts both sidewalls of the gate line.

이어서, 게이트라인 사이를 채울때까지 전면에 층간절연막(16)을 형성한 후, 게이트라인의 상부가 드러날때까지 층간절연막(16)을 CMP를 통해 평탄화한다.Subsequently, the interlayer insulating film 16 is formed on the entire surface until the gate lines are filled, and then the interlayer insulating film 16 is planarized through the CMP until the upper portion of the gate line is exposed.

이어서, 자기정렬콘택식각 공정을 진행하여 게이트라인 사이의 반도체 기판 (11)의 표면을 개방시키는 랜딩플러그콘택홀(Landing Plug Contact hole)을 형성한 후, 랜딩플러그콘택홀을 채울때까지 폴리실리콘막을 증착하고, CMP 공정을 진행하여 랜딩플러그콘택(Landing Plug Contact, 17)을 형성한다.Subsequently, a self-aligning contact etching process is performed to form a landing plug contact hole for opening the surface of the semiconductor substrate 11 between the gate lines, and then the polysilicon film is formed until the landing plug contact hole is filled. After the deposition, the CMP process is performed to form a landing plug contact 17.

상술한 종래기술에서 게이트라인은 후속 랜딩플러그콘택홀을 형성하기 위한 자기정렬콘택식각 공정시 게이트하드마스크질화막(14)이 일정 두께 이상으로 남아야(즉 종횡비를 증가시켜야) 자기정렬콘택식각 마진을 증가시켜 자기정렬콘택페일(SAC Fail)을 방지할 수 있다.In the above-described prior art, the gate line increases the self-aligned contact etch margin when the gate hard mask nitride film 14 must remain above a certain thickness (that is, increase the aspect ratio) during the self-aligned contact etching process for forming subsequent landing plug contact holes. SAC Fail can be prevented.

그러나, 게이트하드마스크질화막(14)의 두께를 일정 두께 이상 증가시키는 경우에는 종횡비의 증가로 게이트패터닝시 식각마진이 감소하게 되고, 또한 층간절연막(16) 증착시 갭필마진이 감소하게 되어 보이드(Void)에 의한 페일이 발생하는 문제가 있다.However, when the thickness of the gate hard mask nitride film 14 is increased by more than a predetermined thickness, the etch margin is reduced during gate patterning due to the increase in the aspect ratio, and the gap fill margin is decreased when the interlayer insulating layer 16 is deposited. There is a problem that a failure occurs due to).

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, 자기정렬콘택식각공정의 식각마진을 증가시키면서 층간절연막의 갭필마진을 증가시킬 수 있는 반도체장치의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device which can increase the gap fill margin of an interlayer insulating film while increasing the etching margin of the self-aligned contact etching process. .

상기 목적을 달성하기 위한 본 발명의 반도체장치의 제조 방법은 반도체 기판 상부에 게이트라인을 형성하는 단계, 상기 게이트라인을 포함한 전면에 식각스 톱막을 형성하는 단계, 상기 식각스톱막 상에 게이트라인 상부에서 오버행 프로파일을 갖는 제1스페이서절연막을 형성하는 단계, 상기 제1스페이서절연막 상에 제2스페이서절연막을 형성하는 단계, 상기 제2스페이서절연막과 상기 제1스페이서절연막이 소정의 선택비를 갖는 레시피로 스페이서 식각 공정으로 식각하여 상기 게이트라인의 측면 및 상부를 덮는 게이트스페이서를 형성하는 단계, 상기 게이트스페이서 상부에 상기 게이트라인 사이를 채울때까지 층간절연막을 형성하는 단계, 상기 게이트스페이서 표면이 드러날때까지 상기 층간절연막을 평탄화시키는 단계, 상기 층간절연막과 식각스톱막을 자기정렬콘택식각으로 식각하여 상기 게이트라인 사이의 반도체기판 표면을 개방시키는 랜딩플러그콘택홀을 형성하는 단계, 및 상기 랜딩플러그콘택홀에 매립되는 랜딩플러그콘택을 형성하는 단계를 포함하는 것을 특징으로 하며, 상기 제1스페이서절연막과 상기 제2스페이서절연막은 플라즈마 화학기상증착방식으로 증착하는 것을 특징으로 하고, 상기 제1스페이서절연막은 질화막으로 형성하고, 상기 제2스페이서절연막은 USG로 형성하는 것을 특징으로 한다.In another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a gate line on an upper surface of a semiconductor substrate, forming an etch top layer on the entire surface including the gate line, and forming an upper gate line on the etch stop layer. Forming a first spacer insulating layer having an overhang profile at the step of forming a second spacer insulating layer on the first spacer insulating layer, wherein the second spacer insulating layer and the first spacer insulating layer have a predetermined selectivity. Etching through a spacer etching process to form a gate spacer covering the side and top of the gate line, forming an interlayer insulating film on the gate spacer until the gate line is filled between the gate spacers, and then revealing the gate spacer surface. Planarizing the interlayer insulating film; Etching each stop film by self-aligned contact etching to form a landing plug contact hole for opening a surface of the semiconductor substrate between the gate lines, and forming a landing plug contact embedded in the landing plug contact hole. Wherein the first spacer insulating layer and the second spacer insulating layer are deposited by a plasma chemical vapor deposition method, wherein the first spacer insulating layer is formed of a nitride film, and the second spacer insulating layer is formed of USG. It is characterized by.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체장치의 제조 방법을 도시한 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체 기판(21) 상에 게이트산화막(22)을 형성 한 후, 게이트산화막(22) 상에 게이트전극(23)과 게이트하드마스크질화막(24)을 적층한다. 여기서, 게이트전극(23)은 폴리실리콘과 텅스텐실리사이드(WSi)의 적층이며, 폴리실리콘은 200Å∼1000Å 두께이고, 텅스텐실리사이드는 500Å∼1500Å 두께이다. 그리고, 게이트하드마스크질화막(24)은 1000Å∼1500Å 두께로 형성한다.As shown in FIG. 2A, after the gate oxide film 22 is formed on the semiconductor substrate 21, the gate electrode 23 and the gate hard mask nitride film 24 are stacked on the gate oxide film 22. Here, the gate electrode 23 is a stack of polysilicon and tungsten silicide (WSi), the polysilicon is 200 GPa to 1000 GPa thick, and the tungsten silicide is 500 GPa to 1500 GPa thick. The gate hard mask nitride film 24 is formed to have a thickness of 1000 GPa to 1500 GPa.

이어서, 게이트패터닝을 진행하여 게이트전극(23)과 게이트하드마스크질화막(24)의 순서로 적층된 게이트라인을 형성한다. 이때, 게이트패터닝시 게이트산화막(22)도 식각될 수 있다. Subsequently, gate patterning is performed to form gate lines stacked in the order of the gate electrode 23 and the gate hard mask nitride film 24. In this case, the gate oxide layer 22 may also be etched during the gate patterning.

상기 게이트패터닝시 게이트하드마스크질화막(24)은 500W∼1000W의 파워, 30mtorr∼70mtorr의 압력 및 CF4/CHF3/O2/Ar의 혼합가스를 이용한 레시피로 식각한다.During the gate patterning, the gate hard mask nitride film 24 is etched with a recipe using a power of 500 W to 1000 W, a pressure of 30 mtorr to 70 mtorr, and a mixed gas of CF 4 / CHF 3 / O 2 / Ar.

그리고, 게이트전극(23)의 식각은 500W∼1000W의 파워, 4mtorr∼50mtorr의 압력 및 C2F6/NF3/Cl2/O2/N2/He/HBr의 혼합가스를 이용하여 식각한다.The gate electrode 23 is etched using a power of 500 W to 1000 W, a pressure of 4 mtorr to 50 mtorr, and a mixed gas of C 2 F 6 / NF 3 / Cl 2 / O 2 / N 2 / He / HBr. .

도 2b에 도시된 바와 같이, 게이트스페이서로 사용되는 게이트스페이서절연막을 형성하는데, 본 발명은 게이트스페이서절연막으로 삼중층의 절연막을 사용한다.As shown in FIG. 2B, a gate spacer insulating film used as a gate spacer is formed, and the present invention uses a triple layer insulating film as the gate spacer insulating film.

바람직하게, 게이트스페이서절연막은 제1질화막(25), 제2질화막(26) 및 산화막(27)의 순서로 형성하여 삼중층으로 형성하며, 제1질화막(25)은 LP 질화막(Low Pressure Chemical Vapor Deosition Nitride)이고, 제2질화막(26)은 PE 질화막(Plasma Enhanced CVD Nitride)이며, 산화막(27)은 PE USG(Plasma Enhanced CVD Undoped Silicate Glass)이다. 그리고, 제1질화막(25)은 후속 자기정렬콘택식각 공정시 스톱핑 역할을 하도록 150Å∼250Å 두께로 형성하고, 제2질화막(26)과 산화막(27)은 오버행 프로파일을 갖도록 각각 500Å∼1500Å 두께, 200Å∼800Å 두께로 형성한다. 이와 같이 오버행 프로파일을 갖는 것은 플라즈마화학기상증착방식(PE CVD)의 고유 증착 특성에 기인한 것이다.Preferably, the gate spacer insulating film is formed in the order of the first nitride film 25, the second nitride film 26, and the oxide film 27 to form a triple layer, and the first nitride film 25 is an LP nitride film (Low Pressure Chemical Vapor). Deosition Nitride), the second nitride film 26 is a PE nitride film (Plasma Enhanced CVD Nitride), and the oxide film 27 is a PE USG (Plasma Enhanced CVD Undoped Silicate Glass). In addition, the first nitride film 25 is formed to have a thickness of 150 kV to 250 kV to serve as a stopping function in a subsequent self-aligned contact etching process, and the second nitride film 26 and the oxide film 27 are 500 kW to 1500 kW, respectively, to have an overhang profile. It is formed to a thickness of 200 to 800 mm. This overhang profile is due to the inherent deposition characteristics of plasma chemical vapor deposition (PE CVD).

상기한 제1질화막(25)과 제2질화막(26)은 증착방식이 서로 다른 질화막인데, 제1질화막(25)인 LP 질화막은 LPCVD 특성상 스텝커버리지특성이 우수하여 균일한 막두께로 증착가능하지만, 제2질화막(26)인 PE 질화막은 스텝커버리지특성이 열악하여 하부 구조물의 토폴로지에 따라 증착두께가 다르게 된다.The first nitride film 25 and the second nitride film 26 are nitride films having different deposition methods. The LP nitride film, which is the first nitride film 25, has excellent step coverage characteristics due to the LPCVD characteristics, so that it can be deposited with a uniform film thickness. The PE nitride layer, which is the second nitride layer 26, has poor step coverage characteristics, and thus, the deposition thickness is different according to the topology of the underlying structure.

즉, PE 질화막은 하부의 게이트라인의 상부 모서리, 게이트라인의 측면, 반도체기판의 표면, 게이트라인의 상부면에서 서로 다른 프로파일을 갖고 증착된다.That is, the PE nitride film is deposited with different profiles on the upper edge of the lower gate line, the side of the gate line, the surface of the semiconductor substrate, and the upper surface of the gate line.

자세히 살펴보면, 게이트라인 상부면에서의 두께가 가장 두껍고, 상부모서리에서의 두께가 게이트라인의 측면 및 반도체 기판(21)의 표면 위에서의 두께보다 더 두껍다.In detail, the thickness at the top surface of the gate line is the thickest, and the thickness at the top edge is thicker than the thickness on the side of the gate line and on the surface of the semiconductor substrate 21.

결국, 위와 같은 열악한 스텝커버리지특성에 의해 제2질화막(26)인 PE 질화막은 게이트라인 상부에서 오버행(Overhang) 구조를 갖고 증착된다. 특히, 제2질화막(26)은 오버행 프로파일을 갖도록 500Å∼1500Å 두께로 형성한다.As a result, the PE nitride layer, which is the second nitride layer 26, is deposited with an overhang structure on the gate line due to the poor step coverage characteristics. In particular, the second nitride film 26 is formed to have a thickness of 500 mV to 1500 mV so as to have an overhang profile.

그리고, 산화막(27)또한 플라즈마화학기상증착 방식으로 증착하므로, 오버행 프로파일을 가지며 그 두께가 제2질화막에 비해 얇으므로 오버행 프로파일의 정도가 다소 완화된다.In addition, since the oxide film 27 is also deposited by a plasma chemical vapor deposition method, since the film has an overhang profile and its thickness is thinner than that of the second nitride film, the degree of the overhang profile is slightly alleviated.

도 2c에 도시된 바와 같이, 스페이서식각(Spacer etch)을 진행하여 게이트라인의 양측벽과 상부면을 덮는 게이트스페이서(GS)를 형성한다.As shown in FIG. 2C, spacer etching is performed to form a gate spacer GS covering both sidewalls and the top surface of the gate line.

이때, 게이트스페이서(GS)는 제1질화막(25), 제2질화막패턴(26a), 산화막패턴(27a)의 삼중층 구조로 형성된다. 즉, LP 질화막, PE 질화막 및 PE USG의 삼중층으로 형성된다.In this case, the gate spacer GS is formed in a triple layer structure of the first nitride film 25, the second nitride film pattern 26a, and the oxide film pattern 27a. That is, it is formed of a triple layer of LP nitride film, PE nitride film and PE USG.

그리고, 게이트라인 상부면에서의 게이트스페이서의 프로파일은 슬로프(Slope) 형상을 갖는데, 이처럼 슬로프 형상을 갖게 되면 후속 층간절연막 증착시 보이드없이 층간절연막을 갭필할 수 있다.In addition, the profile of the gate spacer on the upper surface of the gate line has a slope shape. If such a slope shape is provided, the interlayer insulating film may be gap-filled without voids during the subsequent deposition of the interlayer insulating film.

그리고, 오버행 구조를 갖는 제2질화막(26)은 최초 증착시 매우 두껍게 증착한 상태이므로, 게이트스페이서식각 후에도 여전히 게이트라인 상부에서 일정 두께를 갖는 제2질화막패턴(26a)으로 잔류하는데, 이로써 게이트라인에 포함되는 게이트하드마스크질화막(24) 위에 제2질화막패턴(26a)이 잔류하게 되어 전체적으로 잔류하는 질화막의 총두께가 증가한다. 이는 후속 자기정렬콘택식각시 마진을 증가시킨다.In addition, since the second nitride layer 26 having the overhang structure is deposited very thick during the initial deposition, the second nitride layer 26 still remains as a second nitride layer pattern 26a having a predetermined thickness on the gate line after etching the gate spacer. The second nitride film pattern 26a remains on the gate hard mask nitride film 24 included in the total thickness of the nitride film. This increases the margin on subsequent self-aligned contact etching.

상기한 바와 같이 슬로프 형상을 가지면서 삼중층 구조의 게이트스페이서(GS)를 형성하기 위한 스페이서 식각 공정은 제2질화막(26)과 선택비를 가지는 레시피로 진행한다. 즉, 제2질화막(26)의 식각률이 산화막(27)에 비해 더 느리게 하는 레시피로 진행하므로써 제2질화막패턴(26a)을 게이트라인 상부에서 일정 두께로 잔류시킨다. 바람직하게, 스페이서식각 공정은 PE 질화막인 제2질화막(26)과 5:1 이상의 선택비[제2질화막(26) 대 산화막(27)의 선택비가 5:1∼10:1]를 가지는 레시 피를 적용하여 진행하고, 스페이서 식각시 제2질화막(26)의 손실을 최소화하여 후속 랜딩플러그콘택홀을 위한 자기정렬콘택식각시 자기정렬콘택 마진을 증가시킨다.As described above, the spacer etching process for forming the gate spacer GS having a slope shape and having a triple layer structure proceeds to a recipe having a selectivity with the second nitride layer 26. That is, the second nitride film pattern 26a remains at a predetermined thickness above the gate line by proceeding to a recipe in which the etching rate of the second nitride film 26 is slower than that of the oxide film 27. Preferably, the spacer etching process includes a recipe having a selectivity ratio of the second nitride film 26, which is a PE nitride film, to 5: 1 or more (selection ratio of the second nitride film 26 to the oxide film 27, 5: 1 to 10: 1). Proceed by applying to minimize the loss of the second nitride film 26 during spacer etching to increase the self-aligned contact margin during the self-aligned contact etching for subsequent landing plug contact holes.

이와 같은 레시피로 스페이서식각을 진행하면, 산화막패턴(27a)은 제2질화막패턴(26a)의 측면에 부착되는 구조를 갖고, LP 질화막으로 형성한 제1질화막(25)은 PE 질화막인 제2질화막(26)에 비해 식각률이 더 느리므로 스페이서식각시 식각이 이루어지지 않는다.When the spacer is etched with such a recipe, the oxide film pattern 27a has a structure attached to the side surface of the second nitride film pattern 26a, and the first nitride film 25 formed of the LP nitride film is a second nitride film which is a PE nitride film. Since the etching rate is slower than that of (26), etching is not performed during spacer etching.

바람직하게, 스페이서 식각 공정은 1000W∼2000W의 파워, 15mtorr∼50mtorr의 압력 및 C4F8/C5F8/C4F6/CH2F2/Ar/O2/Co/N2의 혼합가스를 이용한 레시피로 진행한다. 이러한 레시피로 스페이서식각을 진행하면, PE 질화막인 제2질화막(26)과 PE USG인 산화막(27)간 선택비가 1:5 이상(1:5∼1:10)이 된다.Preferably, the spacer etching process comprises a power of 1000 W to 2000 W, a pressure of 15 mtorr to 50 mtorr, and a mixture of C 4 F 8 / C 5 F 8 / C 4 F 6 / CH 2 F 2 / Ar / O 2 / Co / N 2 Proceed to gas recipe. When the spacer is etched with such a recipe, the selectivity between the second nitride film 26, which is a PE nitride film, and the oxide film 27, which is PE USG, becomes 1: 5 or more (1: 5 to 1:10).

또한, 위와 같은 레시피로 스페이서 식각을 진행하면, 게이트라인 상부면에서의 게이트스페이서의 프로파일은 슬로프(Slope) 형상을 갖는데, 이는 제2질화막(26)과 산화막(27)간 선택비 차이 및 측벽이 먼저 손실되는 식각특성에 의한 것이다. 이와 같이, 슬로프 형상을 갖게 되면, 후속 층간절연막 증착시 보이드없이 층간절연막을 갭필할 수 있다.In addition, when the spacer is etched using the above recipe, the profile of the gate spacer on the upper surface of the gate line has a slope shape, which indicates a difference in selectivity between the second nitride layer 26 and the oxide layer 27 and a sidewall. This is first due to the loss of etching characteristics. As such, when the slope shape is formed, the interlayer insulating film can be gap-filled without voids during the subsequent deposition of the interlayer insulating film.

도 2d에 도시된 바와 같이, 게이트스페이서(GS)를 포함한 전면에 게이트라인 사이를 채울때까지 층간절연막(28)을 형성한 후, 게이트라인의 상부가 드러날때까지 층간절연막(28)을 CMP를 통해 평탄화한다. 여기서, 층간절연막(28)은 BPSG를 5000Å∼8000Å 두께로 형성한 것이며, BPSG 증착후에 습식어닐(Wet anneal)을 진 행하여 게이트라인 사이에 BPSG가 충분히 갭필되도록 한다.As shown in FIG. 2D, the interlayer dielectric layer 28 is formed on the entire surface including the gate spacer GS until the gate lines are filled with the interlayer dielectric layer 28. Then, the interlayer dielectric layer 28 is made of CMP until the upper portion of the gate line is exposed. Flatten through. Here, the interlayer insulating film 28 is formed with a BPSG having a thickness of 5000 kV to 8000 kPa, and wet anneal is performed after the BPSG deposition so that the BPSG is sufficiently gap-filled between the gate lines.

그리고, 층간절연막(28)의 CMP 공정은 게이트라인의 게이트하드마스크질화막(24) 위에서 정지하는 조건(Stop On gate hard mask nitride)으로 진행하는데, 바람직하게는, 게이트스페이서(GS)를 구성하고 있는 제2질화막패턴(26a)에서 정지하는 조건이 된다.The CMP process of the interlayer insulating film 28 proceeds to a stop on gate hard mask nitride on the gate hard mask nitride film 24 of the gate line. Preferably, the CMP process of the interlayer insulating film 28 constitutes a gate spacer GS. The condition is to stop at the second nitride film pattern 26a.

이어서, 평탄화된 층간절연막(28) 상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 랜딩플러그콘택마스크(도시 생략)를 형성한 후, 랜딩플러그콘택마스크를 식각마스크로 층간절연막(28)을 자기정렬콘택식각으로 식각하여 게이트라인 사이의 반도체 기판(21)의 표면 상부를 개방시키는 랜딩플러그콘택홀을 형성한다. 이때, 제1질화막(25)은 자기정렬콘택식각시 스톱핑 역할을 하며, 랜딩플러그콘택홀 형성후 제1질화막(25)을 식각하여 반도체기판(21)의 표면을 개방시킨다.Subsequently, a photoresist film is applied on the planarized interlayer insulating film 28 and patterned by exposure and development to form a landing plug contact mask (not shown), and then the interlayer insulating film 28 is self-aligned using the landing plug contact mask as an etch mask. Etching is performed by contact etching to form a landing plug contact hole which opens the upper surface of the semiconductor substrate 21 between the gate lines. In this case, the first nitride film 25 serves as a stopper when the self-aligned contact is etched, and after forming the landing plug contact hole, the first nitride film 25 is etched to open the surface of the semiconductor substrate 21.

그리고, 감광막을 이용한 랜딩플러그콘택마스크외에도 하드마스크질화막과 하드마스크폴리실리콘의 적층을 콘택마스크로 이용할 수도 있다.In addition to the landing plug contact mask using the photosensitive film, a stack of hard mask nitride film and hard mask polysilicon may be used as the contact mask.

그리고, 랜딩플러그콘택홀을 형성하기 위한 자기정렬콘택식각은 1000W∼2000W의 파워, 15mtorr∼50mtorr의 압력 및 C4F8/C5F8/C4F6/CH2F2/Ar/O2/Co/N2의 혼합가스를 이용한 레시피로 진행한다.In addition, the self-aligned contact etching for forming the landing plug contact hole includes a power of 1000 W to 2000 W, a pressure of 15 mtorr to 50 mtorr, and a C 4 F 8 / C 5 F 8 / C 4 F 6 / CH 2 F 2 / Ar / O Proceed to the recipe using a mixed gas of 2 / Co / N 2 .

그리고, 제1질화막(25)의 식각은 300W∼700W의 파워, 25mtorr∼50mtorr의 압력 및 CF4/CHF3/Ar의 혼합가스를 이용한 레시피로 진행한다.The etching of the first nitride film 25 proceeds to a recipe using a power of 300 W to 700 W, a pressure of 25 mtorr to 50 mtorr, and a mixed gas of CF 4 / CHF 3 / Ar.

이어서, 랜딩플러그콘택마스크를 스트립한다. 여기서, 랜딩플러그콘택마스크 를 스트립할 때, 랜딩플러그콘택홀 형성시 발생된 폴리머도 동시에 제거할 수 있다.Next, the landing plug contact mask is stripped. Here, when the landing plug contact mask is stripped, the polymer generated when the landing plug contact hole is formed may be removed at the same time.

또한, 스트립공정후에 추가로 세정(Cleaning) 공정을 진행하여 스트립공정후에 잔류하고 있는 폴리머 및 랜딩플러그콘택콘택홀의 바닥면적을 증가시킬 수도 있다. 이러한 세정 공정은 H2SO4+H2O2, 또흔 300:1 BOE를 이용하여 진행한다.In addition, the cleaning process may be further performed after the strip process to increase the bottom area of the polymer and the landing plug contact hole remaining after the strip process. This cleaning process is carried out using H 2 SO 4 + H 2 O 2 , or else 300: 1 BOE.

이어서, 랜딩플러그콘택홀을 채울때까지 폴리실리콘막을 500Å∼2000Å 두께로 증착하고, CMP 공정 또는 에치백 공정을 진행하여 랜딩플러그콘택(Landing Plug Contact, 29)을 형성한다.Subsequently, the polysilicon film is deposited to a thickness of 500 kV to 2000 kPa until the landing plug contact hole is filled, and a landing plug contact 29 is formed by performing a CMP process or an etch back process.

전술한 실시예에 따르면, 게이트스페이서를 게이트라인 상부에서 일정 두께로 잔류시키므로써 게이트하드마스크질화막(24)의 두께를 증가시키지 않으면서도 자기정렬콘택식각공정의 식각마진을 증가시킬 수 있다.According to the above-described embodiment, by leaving the gate spacer at a predetermined thickness above the gate line, the etching margin of the self-aligned contact etching process may be increased without increasing the thickness of the gate hard mask nitride layer 24.

그리고, 게이트라인 상부에서의 게이트스페이서(GS)의 프로파일을 슬로프 형상으로 형성해주므로써 층간절연막(28)을 보이드없이 갭필할 수 있다.Since the profile of the gate spacer GS in the upper portion of the gate line is formed in a slope shape, the interlayer insulating layer 28 can be gap-filled without voids.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 종횡비 증가 없이도 자기정렬콘택식각의 식각마진을 개선시키고 층간절연막의 갭필마진을 확보하므로써 반도체장치의 제조 수율을 향상시킴과 동시에 공정을 안정화시킬 수 있는 효과가 있다.The present invention described above has the effect of improving the manufacturing margin of the semiconductor device and stabilizing the process by improving the etching margin of the self-aligned contact etching and securing the gap fill margin of the interlayer insulating layer without increasing the aspect ratio.

Claims (8)

반도체 기판 상부에 게이트라인을 형성하는 단계;Forming a gate line on the semiconductor substrate; 상기 게이트라인을 포함한 전면에 식각스톱막을 형성하는 단계;Forming an etch stop layer on the entire surface including the gate line; 상기 식각스톱막 상에 게이트라인 상부에서 오버행 프로파일을 갖는 제1스페이서절연막을 형성하는 단계;Forming a first spacer insulating layer having an overhang profile on a gate line on the etch stop layer; 상기 제1스페이서절연막 상에 제2스페이서절연막을 형성하는 단계;Forming a second spacer insulating layer on the first spacer insulating layer; 상기 제2스페이서절연막과 상기 제1스페이서절연막이 소정의 선택비를 갖는 레시피로 스페이서 식각 공정으로 식각하여 상기 게이트라인의 측면 및 상부를 덮는 게이트스페이서를 형성하는 단계;Forming a gate spacer covering the side and the top of the gate line by etching the spacer spacer etching process with the second spacer insulating layer and the first spacer insulating layer having a predetermined selectivity; 상기 게이트스페이서 상부에 상기 게이트라인 사이를 채울때까지 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the gate spacer until the gate lines are interposed between the gate lines; 상기 게이트스페이서 표면이 드러날때까지 상기 층간절연막을 평탄화시키는 단계;Planarizing the interlayer insulating film until the surface of the gate spacer is exposed; 상기 층간절연막과 식각스톱막을 자기정렬콘택식각으로 식각하여 상기 게이트라인 사이의 반도체기판 표면을 개방시키는 랜딩플러그콘택홀을 형성하는 단계; 및Forming a landing plug contact hole to etch the interlayer dielectric layer and the etch stop layer by using a self-aligned contact etch to open a surface of the semiconductor substrate between the gate lines; And 상기 랜딩플러그콘택홀에 매립되는 랜딩플러그콘택을 형성하는 단계Forming a landing plug contact embedded in the landing plug contact hole 를 포함하는 반도체장치의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 제1스페이서절연막과 상기 제2스페이서절연막은,The first spacer insulating film and the second spacer insulating film, 플라즈마 화학기상증착방식으로 증착하는 것을 특징으로 하는 반도체장치의 제조 방법.A method of manufacturing a semiconductor device, characterized by depositing by plasma chemical vapor deposition. 제2항에 있어서,The method of claim 2, 상기 제1스페이서절연막은 질화막으로 형성하고, 상기 제2스페이서절연막은 USG로 형성하는 것을 특징으로 하는 반도체장치의 제조 방법.And the first spacer insulating film is formed of a nitride film, and the second spacer insulating film is formed of USG. 제3항에 있어서,The method of claim 3, 상기 질화막은 500Å∼1500Å 두께로 형성하는 것을 특징으로 하는 반도체장치의 제조 방법.The nitride film is formed in a thickness of 500 kV to 1500 kV. 제3항에 있어서,The method of claim 3, 상기 USG는, 200Å∼800Å 두께로 형성하는 것을 특징으로 하는 반도체장치의 제조 방법.The USG is formed in a thickness of 200 mW to 800 mW. 제1항 내지 제5항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 5, 상기 게이트스페이서를 형성하는 단계에서,In the forming of the gate spacer, 상기 스페이서식각공정은, 상기 제2스페이서절연막 대 상기 제1스페이서절연막의 선택비가 1:5∼1:10의 범위로 갖는 레시피를 적용하여 진행하는 것을 특징으로 하는 반도체장치의 제조 방법.The spacer etching process is performed by applying a recipe having a selectivity ratio of the second spacer insulating film to the first spacer insulating film in a range of 1: 5 to 1:10. 제6항에 있어서,The method of claim 6, 상기 스페이서식각공정은, The spacer etching process, 1000W∼2000W의 파워, 15mtorr∼50mtorr의 압력 및 C4F8/C5F8/C4F6/CH2F2/Ar/O2/Co/N2의 혼합가스를 이용한 레시피로 진행하는 것을 특징으로 하는 반도체장치의 제조 방법.Proceed to recipe using 1000W ~ 2000W power, 15mtorr ~ 50mtorr pressure and C 4 F 8 / C 5 F 8 / C 4 F 6 / CH 2 F 2 / Ar / O 2 / Co / N 2 mixed gas A method of manufacturing a semiconductor device, characterized by the above-mentioned. 제1항에 있어서,The method of claim 1, 상기 식각스톱막은,The etch stop film, 저압화학기상증착방식을 이용하여 질화막으로 형성하는 것을 특징으로 하는 반도체장치의 제조 방법.A method for manufacturing a semiconductor device, comprising forming a nitride film using a low pressure chemical vapor deposition method.
KR1020050036553A 2005-04-30 2005-04-30 Method for manufacturing semiconductor device KR20060113271A (en)

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Publication number Priority date Publication date Assignee Title
KR20150026116A (en) * 2013-08-30 2015-03-11 삼성전자주식회사 semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150026116A (en) * 2013-08-30 2015-03-11 삼성전자주식회사 semiconductor device and manufacturing method thereof

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