KR20000013720A - Contact window fabrication method of semiconductor device - Google Patents

Abstract

PURPOSE: A contact window fabrication method of semiconductor device is provided to easily extend a width of lower division for contact window and effectively prevent increase of contact surface resistance using ratio of wet etch for insulator with high density of dopant is bigger than ratio of wet etch for insulator with low density of dopant. CONSTITUTION: The contact window fabrication method of semiconductor device comprises the steps of providing a semiconductor board with a lower conduction member; forming a first insulating film using insulator which is doped with a first density of impurity on the lower conduction member; forming a second insulating film using insulator which is doped with a second density of impurity on the first insulating film; dry etching the first and second insulating film and opening a contact window to expose the lower conduction member; wet etching the first and second insulating film on the contact window and increasing an exposing area of the lower conduction member.

Description

Method for manufacturing contact window of semiconductor device

TECHNICAL FIELD This invention relates to the manufacturing method of a semiconductor device. Specifically, It is related with the manufacturing method of a contact window with a small aspect ratio.

As the degree of integration of semiconductor devices increases, it is inevitable to reduce device design rules. However, reduction of device design rules does not occur at the same rate for all dimensions. In other words, the thickness of the interlayer insulating layer and the thickness of the wiring layer in the transverse dimension must be taken into consideration because the breakdown voltage, parasitic capacitance, current capacity, and wiring resistance must be taken into account, so that it is impossible to reduce the proportionally in accordance with the change of the design rule. Because of this, the aspect ratio, which is a ratio of the size and depth of the lowermost part of the small contact window, is gradually increased.

As the aspect ratio increases, a gradient occurs in that the contact window is not completely formed during the etching process for forming the contact window or the size gradually decreases toward the bottom of the contact window. When the gradient occurs, the contact area with the lower conductive film is small, a problem in which the sheet resistance increases rapidly.

Particularly, in the case of the contact window formed to contact the lower electrode of the capacitor with the active region formed on the semiconductor substrate in the capacitor over bit line (COB) structure in which the capacitor is formed after the bit line is formed, the contact ratio is very large. The bottom end of the window is so small that the sheet resistance increases very much.

The technical problem to be achieved by the present invention is to provide a method for manufacturing a contact window that can increase the contact area by increasing the size of the lower end of the contact window.

1 to 3 are cross-sectional views of process intermediate step structures for explaining a method of manufacturing a contact window according to an embodiment of the present invention.

4 is a layout diagram of a DRAM device having a capacitor over bit line (COB) structure formed by applying a method of manufacturing a contact window according to the present invention.

5 to 12 are cross-sectional views taken along the line V-V 'of FIG. 4, and a cross-sectional view of intermediate structures in the process showing a step of forming a storage electrode of a COB structure by applying a method of manufacturing a contact window according to the present invention. admit.

According to the method for manufacturing a contact window for achieving the above technical problem, first to provide a semiconductor substrate having a lower conductive member is formed. Next, a first insulating layer is formed on the lower conductive member by using an insulator doped with a first concentration at a first concentration. Then, the impurities are doped at a second concentration lower than the first concentration on the lower insulating layer. After forming the second insulating layer using the insulator, the second insulating layer and the first insulating layer are dry etched to open a contact window for exposing the lower conductive member. Finally, the second insulating layer and the first insulating layer on which the contact window is formed are wet etched to increase the exposed area of the lower conductive member.

Preferably, an interlayer insulating film is formed on the lower conductive film before the forming of the first insulating film. Subsequently, a conductive film pattern is further formed on the interlayer insulating film, and then the first insulating film is formed on the conductive film pattern. In this case, the first insulating film is preferably formed to a thickness smaller than the thickness of the interlayer insulating film.

In the present invention, the impurities are impurities including boron and / or phosphorus, and the insulator is an oxide doped with the impurities. Therefore, BSG, PSG, or BPSG may be used as the oxide doped with the impurity.

According to the present invention, the area exposed by the contact window which is small and has a large aspect ratio can be increased. Therefore, an increase in contact sheet resistance can be effectively prevented.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. In the accompanying drawings, the thicknesses of the various films and regions are highlighted for clarity. Also, when either film is referred to as being on another film or substrate, it may be directly over the other film or substrate, or an interlayer film may be present. Like reference numerals in the drawings denote like elements.

1 through 4 are cross-sectional views of process intermediate stage structures for explaining a method of manufacturing a small size contact window in accordance with one embodiment of the present invention.

Referring to FIG. 1, a lower conductive member 110 is formed on a semiconductor substrate 100. The lower conductive member 110 may be an active region, a pad structure, or a lower wiring layer doped with impurities.

The first insulating layer 120 is formed by using an insulator doped with impurities at a first concentration on the resultant on which the lower conductive member 110 is formed. As an insulator constituting the first insulating layer 120, a material having a characteristic in which the concentration of an impurity is proportional to an etching rate is used. The higher the concentration of the impurity, the more the etching rate, in particular, the wet etch rate is an insulating material doped with boron (phosphorous). Therefore, BSG (borosilicate glass) PSG (phosphosilicate glass) or BPSG (borophosphosilicate glass) and the like can be used. After deposition, the first insulating layer 120 may be further flattened by further performing a flow process.

Subsequently, the second insulating layer 130 is formed of an insulating material doped with impurities at a second concentration lower than the first concentration on the first insulating layer 120, and then planarized similarly to the first insulating layer 120.

The first insulating layer 120 may be formed to have a thickness of 1/10 to 1/4 of the thickness of the second insulating layer 130.

Referring to FIG. 2, a photoresist pattern 140 is formed on the second insulating layer 130 to define a contact window having a small size to partially expose the conductive member 110.

Next, the second insulating layer 130 and the first insulating layer 120 are dry-etched using the photoresist pattern 140 as an etching mask to form a contact window 150A exposing the lower conductive member 110. The contact window 150A formed at this time has a narrower width W1 of the lower end of the contact window 150A than the width w1 of the center part due to the gradient phenomenon.

Referring to FIG. 3, the resultant of FIG. 2 is treated with a wet etchant to complete a contact window 150B having a smaller size W2 having a lower width W2 than the width w2 of the central portion. The width W2 of the lower portion may be larger than the width w2 of the center portion. The wet etching rate of the first insulating layer 120 having a higher concentration of impurities may be higher than that of the second insulating layer 130 having a lower concentration of impurities. Because it is high. Therefore, it is preferable to adjust the wet etching time and the thickness of the first insulating layer 120 according to the width W2 of the contact window to be formed, that is, the area exposing the lower conductive member 110.

By increasing the width W2 of the lower end portion, the contact area between the conductive material to be formed in the contact window 150B and the lower conductive member 110 may be increased. Therefore, an increase in the contact sheet resistance can be prevented.

4 is a layout diagram of a DRAM device having a capacitor over bit line (COB) structure formed by applying a method for manufacturing a small contact window according to the present invention.

Reference numeral 410 denotes an active region pattern, 420 denotes a word line pattern, 430 denotes a contact window pattern for a bit line, 440 denotes a bit line pattern, 460 denotes a contact window pattern for a storage electrode, and 470 denotes a storage electrode pattern. Indicates. Hereinafter, referring to FIGS. 5 through 12, which are cross-sectional views taken along the line V-V ′ of FIG. 4, a storage electrode of a COB structure is contacted with a source region by applying a method of manufacturing a small contact window according to the present invention. A method of forming a contact window (460 in FIG. 4) is described.

Referring to FIG. 5, a field oxide film 405 is formed on the semiconductor substrate 400 to define the active region 410 using a method such as a local oxide (LOCal oxide of Silicon) method. Next, although not shown in FIG. 5, the word line pattern 420 of FIG. 4 is formed on the active region 410. Subsequently, impurities are implanted into the entire surface of the substrate to form a conductive region such as a source region 412 and a drain region (not shown). The source region 412 and the drain region may also be formed as a lightly doped drain (LDD) structure as needed.

Subsequently, an insulating film, for example, an oxide film 415 is formed on the entire surface of the resultant and then etched to form a cell pad contact region exposing a source region 407 and a drain region (not shown). 417 is formed. The cell pad 417 is formed in the area where the contact window is to be formed in order to reduce the aspect ratio of the contact window. Therefore, the cell pad 417 may omit the forming process in consideration of the aspect ratio of the contact window.

After re-depositing the interlayer insulating film 425, for example, an oxide film, on the entire surface of the resultant cell pad 417, the bit line contact window exposing the cell pad 417 formed in the drain region by etching the interlayer insulating film 425. (See 430 of FIG. 4). Subsequently, a polycrystalline silicon film 442 filling the bit line contact window is formed on the interlayer insulating film 425. The polycrystalline silicon film is formed to a thickness of 1000 to 3000 Pa at a temperature of 500 ° C to 700 ° C by Low Pressure Chemical Vapor Deposition (LPCVD). After the polycrystalline silicon film is formed in a non-doped state, the polycrystalline silicon film may be doped with arsenic or phosphorous by ion implantation to be conductive, and the impurities may be doped by in-situ during deposition. It may be formed in the doped polycrystalline silicon film state. It is preferable to further form a tungsten film 444 on the polycrystalline silicon film 442 to improve conductivity.

Referring to FIG. 6, a tungsten film 444, a polycrystalline silicon film 442, and an interlayer insulating film 425 are etched by performing a reactive ion etching process to a polycrystalline silicon film pattern 442P and a tungsten film pattern 444P. The formed bit line 440 is completed, and an interlayer insulating layer pattern 425P is formed under the bit line 440.

Next, an anti-oxidation film 446 is formed on the entire surface of the resultant bit line 440. The antioxidant film 446 is formed by depositing a nitride film at a temperature of 500 ° C to 850 ° C by LPCVD or Plasma Enhanced Chemical Vapor Deposition (PECVD). The antioxidant film 446 is formed to prevent the bit line 440 from being oxidized by a subsequent oxidation process such as an oxidation process of the dielectric film.

Referring to FIG. 7, the first insulating layer 450 is formed on the anti-oxidation layer 446 by using an insulator doped with impurities at a first concentration. As described above, a material having a characteristic in which the concentration of the impurity is proportional to the etching rate is used as the insulator constituting the first insulating layer 450, for example, boron or phosphorous-doped oxide. Therefore, BSG, PSG or BPSG is used. For example, when the first insulating layer 450 is formed using BPSG, the first insulating layer 450 is deposited to have a thickness of 300 GPa to 2000 GPa by an atmospheric pressure chemical vapor deposition (APCVD), LPCVD, or PECVD method. At this time, the first concentration, which is the doping concentration of boron and phosphorus, is as high as possible to facilitate the flow, so that the etching rate during the wet etching process performed in the subsequent process is large.

After the deposition, the mixture was flowed at a high temperature of 750 ° C to 900 ° C under nitrogen atmosphere or nitrogen and oxygen atmosphere. The thickness of the first interlayer insulating layer 450 formed by the flow process is preferably lower than the thickness of the interlayer insulating layer 425 in which the bit line contact hole 430 of FIG. 4 is formed. The reason is that after forming the contact window in the first insulating film 450, the bit line 440 and the bit line 440 when the first insulating film 450 is excessively etched during the wet etching process performed to increase the size of the lower end of the contact window. This is to prevent the problem of short circuit between contact windows.

Referring to FIG. 7, a second insulating layer 452 is formed on the entire surface of the resultant on which the first insulating layer 450 is formed by using an insulator doped with impurities at a second concentration lower than the first concentration.

When the second insulating film 452 is formed of BPSG, the second insulating film 452 is deposited to have a thickness of 3000 kV to 9000 kV by APCVD, LPCVD, or PECVD. After deposition, the second insulating film 452 is planarized by performing a flow process, an etch-back process, or a chemical mechanical polishing process by normal high temperature heat treatment.

Referring to FIG. 8, an etch stop layer 454 is formed on the planarized second insulating layer 452. The etch stop layer 454 is formed by depositing a nitride layer 454 such as a silicon nitride layer (Si ₃ N ₄ ) or a silicon oxynitride layer (SiON) to a thickness of 50 kV to 500 kV. Subsequently, an interlayer insulating layer 456 is formed on the lower end of the storage electrode in a subsequent process to form an undercut. Undercut is to form to increase the effective surface area of the storage electrode. The interlayer insulating film 456 for forming the undercut is formed by depositing an oxide film such as a high temperature oxide film to a thickness of 500 kPa to 2000 kPa. The etch stop layer 454 may prevent the lower second insulating layer 452 from being etched when the interlayer insulating layer 456 is removed to form the undercut, and the bit line 440 may be removed during an oxidation process such as an oxidation process of the dielectric layer. It is formed to prevent oxidation.

Therefore, when the undercut process is not performed or the antioxidant film 446 is formed on the bit line, the etch stop film 454 and the undercut insulating interlayer 456 may not be formed.

Referring to FIG. 9, after forming a photoresist film on the third interlayer insulating film 456, a photo defining a contact window for exposing the cell pad 417 in contact with the source region 412 through a photolithography process is performed. The resist pattern 458 is formed. Subsequently, a dry etching process such as reactive ion etching is performed using the photoresist pattern 458 as an etching mask, thereby performing an interlayer insulating film 456, an etching blocking film 454, and a second insulating film 452 doped with impurities at a second concentration. ), The first insulating layer 450 and the anti-oxidation layer 446 doped at a first concentration higher than the second concentration are sequentially etched to form a contact window 460A exposing the cell pads 417. The contact window 460A thus formed is formed in the multi-layered insulating layers 456, 454, 452, and 450, and the width W1 of the lower end portion is narrower than the width w1 of the center portion of the contact window 460A because the aspect ratio is large. Is formed.

Referring to FIG. 10, the semiconductor substrate 400 on which the contact window 460A is formed is treated with a mixed solution of ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and pure water (DIW) or a hydrofluoric acid solution. Wet etching process is performed.

Since the first insulating layer 450 has a higher impurity doping concentration than the second insulating layer 452, the wet etch rate of the first interlayer insulating layer 450 is greater than that of the second interlayer insulating layer 452. Therefore, after performing a dry etching process for opening the contact window 460A and performing wet etching, the contact window 460B having a width W2 of the lower end portion wider than the width w2 of the center part can be completed.

That is, the contact area in contact with the lower conductive member, for example, the cell pad 417 or the source region 412, is widened. At this time, the wet etching time is adjusted so that the width W2 of the lower end of the contact window 460B becomes too wide so that a short circuit with an adjacent bit line 440 does not occur.

In addition, the wet etching is used not only for widening the bottom portion of the contact window 460B but also for cleaning the inside of the contact window 460B.

Referring to FIG. 11, after the photoresist pattern 458 is removed, an insulating film, such as a nitride film, is formed on the entire surface of the resultant in which the contact window 460B is formed, and then is etched back to form a contact window 460B. An insulating spacer 462 is formed on the side wall of the insulating spacer 462. Next, the contact window 460B is embedded and a conductive film such as a polycrystalline silicon film doped with impurities is formed on the oxide film 456 to have a predetermined thickness. The conductive film is formed to a thickness of about 5000 kPa to 12000 kPa. Next, the conductive film is patterned to form the storage electrode 470.

Referring to FIG. 12, the interlayer insulating layer 456 is selectively removed to form an undercut to complete the storage electrode structure. At this time, the etch stop layer 454 prevents the second insulating layer 452 from being damaged.

The storage electrode formed according to the present invention contacts the cell pad 417 through the contact window 460B having a large aspect ratio. However, unlike the prior art, since the width W2 of the contact surface is wide, the probability of failure of the device due to the increase of the contact surface resistance is significantly reduced.

The present invention takes advantage of the fact that the wet etch rate of the insulator doped with a high concentration of impurities is larger than the wet etch rate of the insulator doped with a low concentration. Accordingly, an insulating layer including a lower insulating layer doped with a high concentration of impurities and an upper insulating layer doped with a low concentration of impurities is etched by dry etching and wet etching to form a contact window. As a result, the width of the lower portion of the contact window can be easily widened as compared with the conventional contact window, so that an increase in contact surface resistance can be effectively prevented.

Claims (13)

Providing a semiconductor substrate having a lower conductive member formed thereon; Forming a first insulating film on the lower conductive member by using an insulating material doped with impurities at a first concentration; Forming a second insulating film on the first insulating film using the insulating material doped with a second concentration less than the first concentration; Dry etching the second insulating film and the first insulating film to open a contact window exposing the lower conductive member; And wet-etching the second insulating film and the first insulating film on which the contact window is formed to increase the exposed area of the lower conductive member. The method of claim 1, wherein the impurity comprises boron and / or phosphorus. The method of claim 2, wherein the insulator is an oxide doped with the impurity. The method of claim 2, wherein the oxide doped with impurities is BSG, PSG, or BPSG. The wet etching step of claim 1, wherein the wet etching rate of the first insulating layer is greater than that of the second insulating layer, and the width of the contact window formed in the first insulating layer is greater than the width of the contact window formed in the second insulating layer. Increasing the exposed area of the lower conductive member. Providing a semiconductor substrate having a lower conductive member formed thereon; Forming an interlayer insulating film on the semiconductor substrate; Forming a conductive film pattern on the interlayer insulating film; Forming a first insulating film using an insulating material doped with impurities at a first concentration on the entire surface of the resultant product on which the conductive film pattern is formed; Forming a second insulating film on the first insulating film using the insulating material doped with a second concentration less than the first concentration; Dry etching the second insulating film and the first insulating film to open a contact window exposing the lower conductive member; And wet-etching the second insulating film and the first insulating film on which the contact window is formed to increase the exposed area of the lower conductive member. The method of manufacturing a contact window of a semiconductor device according to claim 6, wherein said impurities comprise boron and / or phosphorus. The method of claim 6, wherein the insulator is an oxide doped with the impurity. The method of claim 8, wherein the doped oxide is BSG, PSG, or BPSG. The method of manufacturing a contact window of a semiconductor device according to claim 6, wherein the first insulating film has a thickness smaller than the thickness of the interlayer insulating film. The wet etching step of claim 6, wherein the wet etching rate of the first insulating layer is greater than that of the second insulating layer so that the width of the contact window formed in the first insulating layer is greater than the width of the contact window formed in the second insulating layer. And increasing the exposed area of the lower conductive member. The method of manufacturing a contact window of a semiconductor device according to claim 6, further comprising forming an anti-oxidation film on the entire surface of the conductive film pattern before forming the first insulating film. The method of claim 6, further comprising: forming an interlayer insulating film for forming an undercut on the second insulating film and the conductive film pattern for filling the contact window before the opening of the contact window. And the step of opening the contact window comprises dry etching the interlayer insulating film, the etch stop film, the second insulating film, and the first insulating film for forming the undercut.