KR20010065683A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
KR20010065683A
KR20010065683A KR1019990065603A KR19990065603A KR20010065683A KR 20010065683 A KR20010065683 A KR 20010065683A KR 1019990065603 A KR1019990065603 A KR 1019990065603A KR 19990065603 A KR19990065603 A KR 19990065603A KR 20010065683 A KR20010065683 A KR 20010065683A
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KR
South Korea
Prior art keywords
landing plug
plug contact
semiconductor device
contact hole
region
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KR1019990065603A
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Korean (ko)
Inventor
윤종원
김태한
류재옥
Original Assignee
박종섭
주식회사 하이닉스반도체
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Priority to KR1019990065603A priority Critical patent/KR20010065683A/en
Publication of KR20010065683A publication Critical patent/KR20010065683A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to compensate a removal ratio of a cell region and a peripheral region without changing a structure of a gate line. CONSTITUTION: A gate is formed on a semiconductor substrate(10). An interlayer dielectric(30) is deposited on a surface of the whole structure. The interlayer dielectric(30) is planarized by performing a CMP(Chemical Mechanical Polishing) process. A nitride layer is deposited on the planarized interlayer dielectric(30). A landing plug contact region is opened by performing a dry etching process for the nitride layer. The semiconductor substrate(10) is exposed and a landing plug contact hole is formed by etching the opened region. A landing plug poly(55) is buried into the landing plug contact hole. A planarization process is performed.

Description

반도체장치의 제조방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

본 발명은 반도체장치의 제조방법에 관한 것으로서, 보다 상세하게는 랜딩플러그 콘택을 형성할 때 수행하는 CMP공정시 셀지역과 페리지역의 제거율(removalrate) 차이에 의해 발생되는 페리지역의 게이트라인이 손상을 전면에 질화막을 추가로 증착하여 셀지역과 페리지역의 제거율을 보상함으로써 게이트라인의 손상을 방지할 수 있도록 한 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to damage a gate line of a ferry region caused by a difference in removal rate between a cell region and a ferry region during a CMP process performed when forming a landing plug contact. The present invention relates to a method of fabricating a semiconductor device in which a nitride film is further deposited on a front surface to compensate for removal rates of a cell region and a ferry region, thereby preventing damage to a gate line.

일반적으로, 반도체장치는 그 집적도가 증가하고 내부 회로가 복잡해지는 추세에 부응하여 다층의 배선 구조를 가지게 되며, 이러한 다층 배선간을 연결하기 위해 많은 방법이 제시되고 있다.In general, a semiconductor device has a multi-layered wiring structure in response to a trend of increasing integration and increasing complexity of internal circuits, and many methods for connecting such multi-layer wirings have been proposed.

따라서, 0.18㎛ 이상급 소자에서는 랜딩플러그 콘택 소오스/드레인영역과 커패시터를 연결하기 위한 자리에 랜딩플러그 콘택을 형성하고 플러그 폴리를 매립하여 다층 배선간을 연결하는 추세이다.Therefore, in devices having a class of 0.18 µm or more, a landing plug contact is formed at a position for connecting the landing plug contact source / drain region and a capacitor, and a plug poly is embedded to connect the multilayer wirings.

랜딩플러그 콘택은 T자형 또는 분리된 원형 콘택으로 제조되는데 콘택홀 형성후 폴리를 증착하고 게이트 라인을 경계로 분리시키게 되는데 이를 위하여 CMP 공정이나 에치백 공정을 적용하여 평탄화시키게 된다.Landing plug contacts are made of T-shaped or separated circular contacts. After forming the contact holes, poly is deposited and the gate lines are separated at the boundary. For this, the landing plug contacts are planarized by applying a CMP process or an etch back process.

그런데 일반적으로 적용되는 CMP공정에서 게이트라인 상부에 형성된 질화막이나 산화막 등의 마스크 필름을 경계로 랜딩플로그 폴리를 분리시키게 되는데 CMP공정 특성상 셀지역과 페리지역에 패턴의 조밀도에 따라 제거율(removal rate)에 차이가 발생하게 되는데 이러한 제거율의 차이는 페리지역의 게이트라인에 손상을 유발시킴으로써 후속 공정에서 소자의 페일을 발생시키게 되는 문제점이 있다.However, in general CMP process, the landing plug poly is separated by the boundary of a mask film such as a nitride film or an oxide film formed on the gate line, and according to the characteristics of the CMP process, the removal rate is determined according to the pattern density in the cell region and the ferry region. The difference in the removal rate causes a damage to the gate line of the ferry region, which causes the device to fail in a subsequent process.

따라서, 이러한 문제점을 해결하기 위해서는 셀지역과 페리지역의 제거율을 극복할 수 있을 정도로 게이트 라인 상부의 마스크층 두께를 증가시켜야 하는데 마스크층의 두께 증가는 게이트 식각과 갭필 측면 등에서 여러 가지 문제점을 유발시킨다.Therefore, in order to solve this problem, the thickness of the mask layer on the gate line should be increased to overcome the removal rate of the cell region and ferry region, and the increase of the thickness of the mask layer causes various problems in terms of gate etching and gap fill. .

본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 게이트 라인 전면에 형성된 층간절연막을 평탄화한 후 질화막을 증착한 다음 원형 랜딩플러그 콘택을 형성하는 방법이나 게이트 라인 전면에 형성된 층간절연막을 평탄화한 후 전면에 질화막을 증착한 다음 셀 오픈 마스크를 사용하여 셀지역의 질화막을 제거하고 T형 랜딩플러그 콘택 마스크를 사용하는 방법을 사용함으로써 게이트라인의 구조 변화를 시키지 않고 식각 및 갭필의 상황도 동일하게 유지하면서 셀지역과 페리지역의 제거율을 보상할 수 있도록 한 반도체장치의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to planarize an interlayer insulating film formed on the entire gate line, deposit a nitride film, and then form a circular landing plug contact or formed on the entire gate line. After the interlayer insulating film is planarized, a nitride film is deposited on the entire surface, and then the nitride film of the cell region is removed using a cell open mask, and a T-type landing plug contact mask is used to etch and gap fill without changing the structure of the gate line. The present invention provides a method of manufacturing a semiconductor device that can compensate for the removal rate of a cell region and a ferry region while maintaining the same situation.

도 1내지 도 4는 본 발명의 다른 실시예에 의한 반도체장치의 제조방법을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

도 5내지 도 8은 본 발명의 다른 실시예에 의한 반도체장치의 제조방법을 설명하기 위한 단면도들이다.5 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-

10 : 기판 20 : 게이트라인10: substrate 20: gate line

30 : 층간절연막 40 : 제 2질화막30 interlayer insulating film 40 second nitride film

50 : 랜딩플러그 콘택홀 55 : 랜딩플러그 폴리50: landing plug contact hole 55: landing plug poly

상기와 같은 목적을 실현하기 위한 본 발명은 기판상부에 게이트를 형성하는 단계와, 결과물 전면에 층간절연막을 증착한 후 CMP 공정을 수행하여 평탄화하는 단계와, 층간절연막을 평탄화한 후 전면에 질화막을 증착하는 단계와, 질화막을 원형 랜딩플러그 콘택 마스크를 사용하여 건식식각하여 랜딩플러그 콘택 영역을 오픈하는 단계와, 오픈된 영역을 계속해서 기판이 노출될때까지 건식식각하여 랜딩플러그 콘택홀을 형성하는 단계와, 랜딩플러그 콘택홀에 랜딩플러그 폴리를 매립한 후 CMP에 의한 평탄화 공정을 수행하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is a step of forming a gate on the substrate, the step of depositing an interlayer insulating film on the entire surface of the resultant to perform a planarization by performing a CMP process, the planarization of the interlayer insulating film and the nitride film on the entire surface Depositing, dry etching the nitride film using a circular landing plug contact mask to open the landing plug contact region, and dry etching the open region until the substrate is exposed to form a landing plug contact hole. And filling the landing plug poly in the landing plug contact hole and performing a planarization process by CMP.

또한, 기판상부에 게이트를 형성하는 단계와, 결과물 전면에 층간절연막을 증착한 CMP 공정을 수행하여 평탄화하는 단계와, 층간절연막을 평탄화한 후 전면에 질화막을 증착하는 단계와, 질화막을 오픈셀 마스크를 사용하여 셀지역의 질화막을 제거하는 단계와, T형 랜딩플러그 콘택 마스크를 사용하여 층간절연막을 기판이 노출될때까지 건식식각하여 랜딩플러그 콘택홀을 형성하는 단계와, 랜딩플러그 콘택홀을 랜딩플러그 폴리로 매립한 후 CMP에 의한 평탄화 공정을 수행하는 단계를 포함하여 이루어진 것을 특징으로 한다.In addition, forming a gate on the substrate, performing a planarization by performing a CMP process in which the interlayer insulating film is deposited on the entire surface of the resultant, planarizing the interlayer insulating film, and depositing a nitride film on the entire surface, the nitride film is an open cell mask Removing the nitride film in the cell region using the T-type landing plug contact mask, and dry etching the interlayer insulating film until the substrate is exposed using the T-type landing plug contact mask, and forming the landing plug contact hole, and landing landing plug contact hole. It is characterized in that it comprises a step of performing a planarization process by CMP after filling with poly.

위와 같이 이루어진 본 발명은 층간절연막 위로 질화막을 증착함으로써 랜딩플러그 폴리의 CMP에 의한 평탄화 공정시 셀지역과 페리지역의 조밀도에 따른 제거율의 차이를 보상함으로써 페리지역의 게이트라인이 손상되는 것을 방지하게 된다.The present invention made as described above compensates the difference in the removal rate according to the density of the cell region and the ferry region during the planarization process by the CMP of the landing plug poly by depositing a nitride film on the interlayer insulating film to prevent damage to the gate line of the ferry region. do.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment is not intended to limit the scope of the present invention, but is presented by way of example only.

도 1내지 도 4는 본 발명의 다른 실시예에 의한 반도체장치의 제조방법을 설명하기 위한 단면도들이다.1 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

도 1에 도시된 바와 같이 기판(10)위로 폴리층과 하드마스크로 제 1질화막(22)을 순차적으로 증착한 후 식각하여 게이트라인(20)을 형성하고 스페이서 질화막(24)을 형성한다. 그런다음 전면에 층간절연막(30)을 증착하고 CMP 공정을 수행하여 평탄화시킨다.As shown in FIG. 1, the first nitride layer 22 is sequentially deposited on the substrate 10 using a poly layer and a hard mask, and then etched to form a gate line 20 and a spacer nitride layer 24. Then, the interlayer insulating film 30 is deposited on the entire surface and planarized by performing a CMP process.

그런다음 도 2와 같이 전면에 500∼1500Å 두께의 제 2질화막(40)을 증착한다. 이렇게 제 2질화막(40)을 증착하여 제거율을 보상함으로써 게이트라인(20)의 하드마스크 두께를 줄일 수 있어 에스팩트율을 감소시켜 CD 제어 및 층간절연막(30)의 갭필이 용이하게 된다.Then, a second nitride film 40 having a thickness of 500 to 1500 500 is deposited on the entire surface as shown in FIG. 2. Thus, by depositing the second nitride film 40 to compensate for the removal rate, the thickness of the hard mask of the gate line 20 can be reduced, thereby reducing the aspect ratio, thereby facilitating the gap control of the CD control and the interlayer insulating film 30.

그런다음 도 3과 같이 원형 랜딩플러그 콘택 마스크를 사용하여 제 2질화막(40)을 건식식각하여 랜딩플러그 콘택 영역을 오픈한 후 콘택 영역을 계속해서 기판(10)이 노출될때까지 건식식각하여 랜딩플러그 콘택홀(50)을 형성한다.Then, as shown in FIG. 3, the second nitride film 40 is dry-etched using the circular landing plug contact mask to open the landing plug contact region, and the contact region is continuously etched and dry-etched until the substrate 10 is exposed. The contact hole 50 is formed.

그런다음 도 4와 같이 랜딩플러그 폴리(55)를 증착하여 콘택홀(50)을 매립한 후 평탄화 공정을 수행하여 후속 반도체장치의 제조공정을 진행한다.Next, as shown in FIG. 4, the landing plug poly 55 is deposited to fill the contact hole 50, and then the planarization process is performed to proceed to the subsequent semiconductor device manufacturing process.

도 5내지 도 8은 본 발명의 다른 실시예에 의한 반도체장치의 제조방법을 설명하기 위한 단면도들이다.5 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

도 5에 도시된 바와 같이 기판(10)위로 폴리층과 하드마스크로 제 1질화막(22)을 순차적으로 증착한 후 식각하여 게이트라인(20)을 형성하고 스페이서 질화막(24)을 형성한다. 그런다음 전면에 층간절연막(30)을 증착하고 CMP 공정을 수행하여 평탄화시킨다.As illustrated in FIG. 5, the first nitride layer 22 is sequentially deposited on the substrate 10 using a poly layer and a hard mask, and then etched to form a gate line 20 and a spacer nitride layer 24. Then, the interlayer insulating film 30 is deposited on the entire surface and planarized by performing a CMP process.

그런다음 도 6과 같이 전면에 500∼1500Å 두께의 제 2질화막(40)을 증착한다.Then, a second nitride film 40 having a thickness of 500 to 1500 Å is deposited on the entire surface as shown in FIG. 6.

그런다음 도 7과 같이 오픈셀 마스크를 사용하여 셀지역(cell)의 제 2질화막(40) 만을 제거한 후 T형 랜딩플러그 콘택 마스크를 사용하여층간절연막(30)을 기판이 노출될때까지 건식식각하여 랜딩플러그 콘택홀(50)을 형성한다.Then, as shown in FIG. 7, only the second nitride film 40 of the cell region is removed using an open cell mask, and the interlayer insulating layer 30 is dry-etched using a T-type landing plug contact mask until the substrate is exposed. The landing plug contact hole 50 is formed.

그런다음 도 8과 같이 랜딩플러그 폴리(55)를 증착하여 콘택홀(50)을 매립한 후 CMP에 의한 평탄화 공정을 수행하여 후속 반도체장치의 제조공정을 진행한다.Then, as shown in FIG. 8, the landing plug poly 55 is deposited to fill the contact hole 50, and then a planarization process using CMP is performed to proceed to a subsequent semiconductor device manufacturing process.

상기한 바와 같이 본 발명은 반도체장치에서 다층 배선간 연결을 위한 랜딩플러그 폴리의 CMP공정시 셀지역과 페리지역의 제거율에 의한 차이로 인해 페리지역의 게이트 라인이 손상되는 것을 층간절연막을 형성한 후 질화막을 증착함으로써 제거율을 보상하여 랜딩 플러그 폴리의 CMP공정시 게이트 라인의 손상을 방지하여 소자의 특성 개선 및 수율이 증가하는 이점이 있다.As described above, according to the present invention, after forming the interlayer insulating film, the gate line of the ferry region is damaged due to the difference in the removal rate of the cell region and the ferry region during the CMP process of the landing plug poly for connecting the multilayer wirings in the semiconductor device. By depositing a nitride film to compensate for the removal rate to prevent damage to the gate line during the CMP process of the landing plug poly has the advantage of improving the characteristics and yield of the device.

Claims (3)

기판상부에 게이트를 형성하는 단계와,Forming a gate over the substrate; 상기 결과물 전면에 층간절연막을 증착한 후 CMP 공정을 수행하여 평탄화하는 단계와,Depositing an interlayer insulating film on the entire surface of the resultant and performing planarization by performing a CMP process; 상기 층간절연막을 평탄화한 후 전면에 질화막을 증착하는 단계와,Depositing a nitride film on the entire surface after planarizing the interlayer insulating film; 상기 질화막을 원형 랜딩플러그 콘택 마스크를 사용하여 건식식각하여 랜딩플러그 콘택 영역을 오픈하는 단계와,Dry etching the nitride layer using a circular landing plug contact mask to open a landing plug contact region; 상기 오픈된 영역을 계속해서 상기 기판이 노출될때까지 건식식각하여 랜딩플러그 콘택홀을 형성하는 단계와,Continuously etching the open area until the substrate is exposed to form a landing plug contact hole; 상기 랜딩플러그 콘택홀에 랜딩플러그 폴리를 매립한 후 CMP에 의한 평탄화 공정을 수행하는 단계Filling a landing plug poly in the landing plug contact hole and performing a planarization process by CMP 를 포함하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.Method for manufacturing a semiconductor device, characterized in that consisting of. 기판상부에 게이트를 형성하는 단계와,Forming a gate over the substrate; 상기 결과물 전면에 층간절연막을 증착한 CMP 공정을 수행하여 평탄화하는 단계와,Performing planarization by performing a CMP process in which an interlayer insulating film is deposited on the entire surface of the resultant; 상기 층간절연막을 평탄화한 후 전면에 질화막을 증착하는 단계와,Depositing a nitride film on the entire surface after planarizing the interlayer insulating film; 상기 질화막을 오픈셀 마스크를 사용하여 셀지역 만을 제거하는 단계와,Removing only the cell region using the nitride film using an open cell mask; T형 랜딩플러그 콘택 마스크를 사용하여 상기 층간절연막을 상기 기판이 노출될때까지 건식식각하여 랜딩플러그 콘택홀을 형성하는 단계와,Dry etching the interlayer dielectric layer using a T-type landing plug contact mask until the substrate is exposed to form a landing plug contact hole; 상기 랜딩플러그 콘택홀을 랜딩플러그 폴리로 매립한 후 CMP에 의한 평탄화 공정을 수행하는 단계Filling the landing plug contact hole with a landing plug poly and performing a planarization process by CMP 를 포함하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.Method for manufacturing a semiconductor device, characterized in that consisting of. 제 1항내지 제 2항에 있어서, 상기 질화막은 500∼1500Å 두께로 증착하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the nitride film is deposited to a thickness of 500 to 1500 Å.
KR1019990065603A 1999-12-30 1999-12-30 Method for manufacturing semiconductor device KR20010065683A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100382541B1 (en) * 2000-09-21 2003-05-01 주식회사 하이닉스반도체 Method for forming plug of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100382541B1 (en) * 2000-09-21 2003-05-01 주식회사 하이닉스반도체 Method for forming plug of semiconductor device

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