KR20010063192A - Hoffman code decoding apparatus - Google Patents

Abstract

PURPOSE: A Huffman code decoding device is provided to reduce a chip size and increase the degree of freedom by decoding the Huffman code by moving in combination with a software which operates in a DSP(Digital Signal Processor). CONSTITUTION: A bit stream input register(10) stores an input bit stream. A barrel shifter(11) shifts the input bit stream by using control values. A code book selection register(12) stores the bit stream shifted from the barrel shifter(11). A programmable logic array section(14) receives values of the code book selection register(12) and the Huffman code register(13), and outputs an indexes and a Huffman code length corresponding to the values. An index register(15) stores the indexes outputted from the programmable logic array section(14), while a Huffman code length register(16) stores the Huffman code length outputted from the programmable logic array section(14).

Description

Huffman Code Decoder {HOFFMAN CODE DECODING APPARATUS}

The present invention relates to a Huffman code decoding apparatus, and more particularly, to a Huffman code decoding apparatus capable of recognizing index and Huffman code length information by inputting a Huffman code extracted from a bit stream.

In general, Huffman codes are generated through a series of inverse pruning, starting with finding the probabilities for a given sign and arranging each symbol at the end of the branch according to the order of the obtained probabilities.

For example, the end of a branch is placed on the left and some of the branches are combined to create a new branch, so that only one branch is left on the right.

In more detail, one branch comes from each end symbol, which has a weight equal to a given probability.

At this time, the two branches with the lowest weights are combined with each other, and the weights are summed together, and the sum is compared with the remaining non-summed weights, and the branches are arranged again according to the order of the values. .

After performing the above operation, all the branches participate in the summation and repeat this process until only one branch remains.

Then, the right end of the branch comes out, and from this point onwards to the left end, a new value of '0' or '1' is assigned to each branch.

As you progress from the end of the right side to each symbol on the left and collect all the assigned values of '0' or '1', you get one sign, which is the Huffman sign.

Normally, digital audio algorithms such as MP-3 and AAC use Huffman codes to compress data, which is a variable length code that can have the smallest code length for a given symbol.

The important thing in such an audio algorithm is to decode each audio unit at a given time. This decoding process is mainly done by DSP, and if too much time is spent decoding the Huffman code, The unit may not be decoded, and the complexity and verification of the Huffman code decoder may occur when the DSP and the designed Huffman code decoder are used as part of another large system.

In other words, the prior art as described above should have a Huffman codebook that stores the Huffman code in order to decode the Huffman code. To decode such a code, the binary branches are searched by analyzing the respective Huffman code bits. Therefore, not only it takes a lot of time, but there is a problem that the complexity of the circuit increases.

In order to solve this problem, conventionally, a decoded result corresponding to each Huffman code is stored in the PLA in advance, thereby obtaining a decoded result in a short time. In this case, input values and output values inputted to the PLA must be controlled. There was a complicated problem with the circuit.

Accordingly, an object of the present invention is to provide a Huffman code decoding apparatus having a high degree of freedom while reducing chip area by decoding a Huffman code in conjunction with software operating on a DS.

Figure 1 is a block diagram showing the configuration of the Huffman code decoding apparatus of the present invention.

***** Description of the symbols for the main parts of the drawings *****

10: Bit Stream Input Register 11: Barrel Shifter

12: codebook select register 13: Huffman code register

14: programmable logic array section 15: index register

16: Huffman code length register

The present invention for achieving the above object is a bit stream input register for storing an input bit stream; A barrel shifter for receiving a bit stream from the bit stream input register and shifting the bit stream by a value of a Huffman code register and a Huffman code length register to be described later; A codebook selection register for selecting a codebook of a programmable logic array unit to be described later; A Huffman code register for storing an input bit stream shifted by the barrel shifter; A programmable logic array unit for receiving values of the codebook selection register and the Huffman code register and outputting corresponding index and hubman code lengths; An index register for receiving an index output from the program logic array unit and storing the index; And a hub only code length register for storing the Huffman code length output from the program logic array.

Hereinafter, operations and effects on the Huffman code decoding apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a configuration of a Huffman code decoding apparatus according to the present invention, comprising: a bit stream input register 10 for storing an input bit stream as shown therein; A barrel shifter (11) which receives the bit stream from the bit stream input register (10) and shifts it by the values of the Huffman code register (13) and Huffman code length register (16) which will be described later; A codebook selection register 12 for selecting a codebook of the programmable logic array unit 14 to be described later; A Huffman code register (13) for storing the input bit stream shifted by the barrel shifter (11); A programmable logic array unit 14 for receiving values of the codebook selection register 12 and the Huffman code register 13 and outputting corresponding index and hubman code lengths; An index register 15 for receiving an index output from the programmable logic array unit 14 and storing the index; A hub only code length register 16, which stores the Huffman code length output from the programmable logic array unit 14, describes the operation of the present invention.

First, DS can write data to bit stream input register 10, codebook selection register 12 and Huffman code register 13 via an output data bus, which first in the first stage of Huffman decoding The register 12 and the Huffman code register 13 are initialized.

At this time, the value initialized in the codebook selection register 12 is a desired codebook number among the codebooks stored in the programmable logic array unit 14, and the value initialized in the Huffman code register 13 is the first Huffman code.

When the codebook selection register 12 and the Huffman sign register 13 are initialized, these values enter the input of the programmable logic array 14, whereby the programmable logic array 14 is indexed and the Huffman code. Create a length.

Then, the index register 15 receives and stores the index, and the Huffman code length register 16 also receives and stores the Huffman code length.

At this time, the Huffman code length value is applied to the barrel shifter 11 to adjust the shift amount of the input bit stream.

In other words, the software developer stores the new Huffman code in the bit stream input register 10 to decode the new Huffman code, i.e., the bit stream input register 10 reads the input bit stream from the DSP. The barrel shifter 11 receives an input bit stream of the bit stream input register 10 and shifts the input bit stream by the Huffman code length value, and converts the shifted input bit stream into a Huffman code register. 13) generate a new Huffman code by performing an OR operation with the Huffman code previously stored in 13), and store the new Huffman code in the Huffman code register 13, i.e., the barrel shifter 11 sets the input bit stream to the left by the Huffman code length value. Shift by a value, and use this Huffman sign to shift this shifted input bit stream. The Huffman code pre-operated with the Huffman code previously stored in the register 13, and the operation value is stored in the Huffman code register 13 as a new Huffman code value.

At this time, a predetermined selection value of the codebook selection register 12 is input to the programmable logic array unit 14.

Then, the programmable logic array unit 14 receives the values of the codebook selection register 12 and the Huffman code register 13, generates corresponding index and hub only code lengths, and generates the index register 15 and the corresponding index register 15, respectively. The Huffman code length register 16 is stored.

Here, the programmable logic array unit 14 can produce a new output by allowing the software developer to receive a new Huffman code from the bit stream and store it in the bit stream input register 10, that is, the software developer. The subsequent decoding using the value stored in the index register 15 is performed by using a program operating in the DSP, and the value stored in the Huffman code length register 16 is newly added to the bit stream input register 10. Determines the amount of bit stream to store.

As described in detail above, the present invention simplifies the control circuit by controlling the hardware control in conjunction with the software, so that the area is smaller than that of the existing circuit and has a higher degree of freedom and a faster decoding speed.

Claims (5)

A bit stream input register for storing an input bit stream; A barrel shifter for receiving a bit stream from the bit stream input register and shifting the bit stream by a value of a Huffman code register and a Huffman code length register to be described later; A codebook selection register for selecting a codebook of a programmable logic array unit to be described later; A Huffman code register for storing an input bit stream shifted by the barrel shifter; A programmable logic array unit for receiving values of the codebook selection register and the Huffman code register and outputting corresponding index and hubman code lengths; An index register for receiving an index output from the program logic array unit and storing the index; And a hubman code length register for storing a Huffman code length output from the program logic array. The Huffman code decoding apparatus of claim 1, wherein the barrel shifter shifts the value of the bit stream input register to the left by the value stored in the Huffman length register. 3. The Huffman code decoding apparatus of claim 1 or 2, wherein the barrel shifter generates a new Huffman code register value by performing an operation on the value of the shifted input register and the value previously stored in the Huffman code register. 2. The Huffman code decoding apparatus according to claim 1, wherein the Huffman code length register stores an Huffman code length that enters an input of a barrel shifter and adjusts an amount of shift of the barrel shifter. 5. The Huffman code decoding apparatus according to claim 1 or 4, wherein an amount of the bit stream to be stored in the bit stream input register is determined by the Huffman code length of the Huffman code length register.