KR19990027639A - A microprocessor having PLA (PLA) - Google Patents

Abstract

A microprocessor having a PLA, comprising: a microprocessor having an accumulator and a command decoder, the program logic array receiving and processing data output from the accumulator; And a multiplexer for selectively outputting the data output from the program logic array. In this case, when the Huffman code is decoded, it is possible to process the data in a single instruction, thereby improving the processing speed by several orders of magnitude.

Description

A microprocessor having PLA (PLA)

The present invention relates to a digital signal receiving apparatus, and more particularly to a microprocessor of a digital signal receiving apparatus.

Generally, in order to overcome the difficulty of storing a large amount of data by limiting the capacity or transmission rate of a storage medium when converting an image or voice to digital and storing or transmitting the data, the data is compressed using the nature of the data Since the amount of data can be reduced, it can be efficiently stored or transmitted.

This method is referred to as data compression. There are various compression methods depending on the usage environment.

FIG. 1 is a block diagram for explaining general image compression. Generally, JPEG, MPEG, and MPEG2 are methods of compressing image data. All of these methods are based on 2-D DCT (2-Dimensional Discrete Cosine Transform ) Unit 11, a quantization unit 12, a Huffman coder 13, and the like.

That is, the 2-D DCT unit 11 transforms input two-dimensional image data into a frequency domain by performing DCT, localizes the data into a low frequency domain, and quantizes the data through a quantization unit 12, The DCT coefficient is zero, which results in a reduction in the amount of data.

The Huffman coder 13 converts the coefficients quantized by the quantization unit 12 into Huffman codes, thereby reducing the amount of bits of codes to be output.

The Huffman code can reduce the average bit amount by converting a code of a certain bit number into a code having a bit amount in inverse proportion to the occurrence frequency of the code.

That is, for frequently generated codes, the codes are converted into short-length codes and occasionally generated codes are converted into long-length codes. As a result, the length of the output codes is variable and is called a variable length code or VLC (Variable Length Code) .

The Huffman code table has a different table depending on the generation frequency of the code to be converted.

For example, as shown in Table 1 below, in the MPEG 2 video standard, when a code of a VLC having a macro-block address is frequently seen, a code having an increment value of 1 or 2 has a 2-bit code, The code whose value corresponds to 11 is 9 bits long.

Increase macroblock address VLC code Increment value One One 011 2 010 3 0011 4 0010 5 00011 6 00010 7 0000111 8 0000110 9 ... ... 00000011000 33 00000001000 Escape macroblock

An implementation method of a decoder for decoding the coded Huffman code includes a ROM implementation and a PLA implementation.

First, if we consider how to implement the VLC with a maximum of n bits, it is not practical because the size of the ROM is increased because it is required to use a ROM having n number of capacities of 2.

In addition, decoding by the microprocessor requires a plurality of times of comparison and determination, so the decoding speed is slow.

However, the logic for decoding this code is very simple. The logic for decoding the weighted value 1 in Table 1 requires only the first bit to be compared and the logic for decoding the incremented value 2 may be configured to include logic for comparing only 3 bits. That is, it can be implemented as a simple Sum of Product (SOP) term.

If the input of the decoder is an 11-bit VLC code as shown in Table 1 and the output is 34 bits, the first bit is 1 when the input increment value is 1 as shown in Table 2 below. If the increment value is 3, The bit is 1, and the other bits are 0.

Increment value The SOP of each bit One A 2 A'BC 3 A'BC ' 4 A'B'CD 5 A'B'CD ' ... ... Escape macroblock A'B'C'D'E'F'G'HI'J'K '

Here, AB is the logical product of A and B, and A 'is NOT A.

In this case, if the logic consists of SOP, it can be composed of several NOT gates and AND gates. This can be done with a smaller number of gates than with ROM, It can be processed faster.

The basic elements constituting the logic can be any logical circuit composed of a NOT gate, an AND gate and an OR gate.

A PLA (Programmable Logic Array) is a device in which a programmable logic circuit is constructed using such a property.

FIG. 2 is a diagram for explaining the structure of a general PLA. As shown in FIG. 2, the PLA structure inverts and inverses each input to an input terminal. The inverted and non-inverted signal logic is input to an AND array. To the input signal and implement the product term.

Then, a number of product terms are input into the re-programmable OR array, and a program generates a sum term (OR) to be finally output.

FIG. 2 shows input signals I ₀ , I ₁ , and I ₂ , and outputs PLA having three outputs X, Y, and Z. For example, if you have the formula X = I ₀ 'I ₁ + I ₀ I ₁ I ₂ ' + I ₁ 'I ₂ ', you can get the desired logic value by connecting the black dot.

Such a program may be performed when the device is manufactured, and some devices may be programmed by the user several times.

Hereinafter, a conventional microprocessor will be described with reference to the accompanying drawings.

3 is a block diagram illustrating a configuration of a microprocessor according to the related art. The microprocessor includes an instruction decoder 31, an instruction register (IR) 32, a memory data register (MDR) 33, A memory address register (MAR) 38, first and second registers 34 and 35, an arithmetic logic unit (ALU) 37, and a random access memory (RAM)

In the microprocessor constructed as described above, the MDR 33 first stores the instruction in the IR 32 when the instruction is inputted from the external memory, then outputs it to the instruction decoder 31 or outputs the operation result of the ALU 37 to the external memory, The first and second registers (34) and (35) store the input data or previous calculation results.

The instruction decoder 31 controls the ALU 37 by interpreting the inputted instruction word and the ALU 37 is a circuit which can perform arithmetic operation and logical operation and is stored in the first and second registers 34 and 35 And stores the data in the RAM 365 after calculating the data according to the control of the command decoder 31. [

The RAM 365 stores various data to be stored in the microprocessor, and outputs the data to the first and second registers 34 and 35 when necessary.

The MAR 38 outputs the address of the external memory and is controlled by the command decoder 31. [

In order to decode the Huffman codes using such a microprocessor, for example, as shown in Table 1 and Table 2, a maximum of 11 comparison commands must be performed to decode the macroblock address increase code.

In order to decode a code having a code of 00010 and output a value of 7, a comparison instruction of 5 and a jump instruction should be executed. First, if the first bit is 0 or not, it is checked whether the next bit is 0 or not Five compare commands are needed to compare to the last bit.

That is, in order to decode Huffman codes using a microprocessor, several commands must be executed.

Since the microprocessor according to the related art has to perform a plurality of operations in order to decode a single Huffman code, there is a problem that a long time is required as the processing speed increases.

SUMMARY OF THE INVENTION The present invention provides a microprocessor having a PLA capable of performing fast decoding upon decoding a variable length code used in data compression by adding a PLA to a microprocessor, .

1 is a block diagram for explaining general image compression;

2 is a view for explaining the structure of a general PLA;

3 is a block diagram for explaining a configuration of a microprocessor according to the related art

4 is a block diagram for explaining a configuration of a microprocessor having a PLA according to the present invention

DESCRIPTION OF THE REFERENCE NUMERALS

41: MDR 42, 43: Register

44: IR 45: command decoder

46: RAM 47: ALU

48: PLA 49: MUX

50: MAR

A microprocessor having a PLA according to the present invention is characterized by a program logic array for receiving and processing data output from an accumulator and a program logic array for selectively outputting data output from the program logic array upon Huffman code decoding under the control of the instruction decoder It is comprised of muxes.

Another feature of the microprocessor having the PLA according to the present invention is that the program logic array is composed of programmable logic circuit capable of performing Huffman code decoding.

Hereinafter, a microprocessor having a PLA according to the present invention will be described with reference to the accompanying drawings.

FIG. 4 is a block diagram for explaining a configuration of a microprocessor having a PLA according to the present invention. The microprocessor having the PLA according to the present invention includes the MDR 41, the first and second registers 42, Which is output from the first register 42 when Huffman code decoding is performed on the configuration of the register 43, the IR 44, the command decoder 45, the RAM 46, the ALU 47 and the MAR 50, A PLA 48 for receiving and processing data and a multiplexer 49 for selectively outputting data output from the PLA 48 or the ALU 47 according to the decoding result output from the command decoder 45 .

The microprocessor having the PLA according to the present invention configured as described above includes the MDR 41, the first and second registers 42 and 43, the IR 44, the command decoder 45, the RAM 46, The operations of the ALU 47 and the MAR 50 are the same as described above, and the PLA 48 added thereto programs a logic circuit that allows the user to implement desired Huffman code decoding.

The PLA 48 receives and processes the data output from the first register 42 and the MUX 49 receives the data output from the PLA 48 upon Huffman code decoding according to the decoding result output from the command decoder 45 .

The microprocessor having the PLA according to the present invention has a separate PLA other than the ALU so that it can process the compressed data, that is, Huffman code, with a single instruction when decoded, thereby improving the processing speed by several orders of magnitude.

And, it can be widely used in various application fields using Huffman code, which has recently been spotlighted as a data compression technique.

Claims (2)

In a microprocessor having an accumulator and an instruction decoder, A program logic array for receiving and processing data output from the accumulator, And a mux for selectively outputting data output from the program logic array upon Huffman code decoding under the control of the instruction decoder. 2. The system of claim 1, wherein the program logic array And a programmable logic circuit capable of performing Huffman code decoding. ≪ Desc / Clms Page number 19 >