KR20010062611A - Dynamic threshold voltage 4t sram cell - Google Patents

Abstract

PURPOSE: A SRAM cell with dynamic threshold voltage 4T is provided to increase speed and to obtain stability at a low operating voltage. CONSTITUTION: The memory device includes a first transistor(128,112), that has a control electrode and a current passage, and a second transistor(108,130) that has the control electrode, the current passage, and a back gate/body connection part. The back gate/body connection part of the second transistor is electrically connected to the control electrode of the second transistor, and the current passage of the first transistor.

Description

DYNAMIC THRESHOLD VOLTAGE 4T SRAM CELL

TECHNICAL FIELD The present invention relates to semiconductor devices, manufacturing and processing, and more particularly, to static random access memory (SRAM) cells.

Semiconductor memories are essential components for computer bodies and personal computers, telecommunications, automotive and consumer electronics, and commercial and military avionics systems. Semiconductor memories are characterized as volatile random access memory (RAM) or nonvolatile devices. The RAMs can be either static mode (SRAM) where digital information is stored by setting the logic state of the bistable device or dynamic mode (DRAM) where digital information is stored through the periodic charging of the capacitor. The SRAM is typically configured as a matrix of memory cells made of integrated circuit chips and the address decoding function within this chip allows access to each cell for read / write functions. SRAM memory cells use active feedback in the form of cross coupled inverters to store bits of information as logic "0" or logic "1". Active elements in memory cells require an electrostatic source to remain latched in a given state. These memory cells are often arranged in columns so that data blocks such as words or bytes can be written or read simultaneously. Address multiplexing is used to reduce the number of input and output pins. SRAM has increased significantly in density over the past few years.

Standard SRAM memory cells have many variations. The basic CMOS SRAM cell consists of two n-channel pull-down (or "drive") transistors and two p-channel load transistors in a cross-coupled inverter configuration, while two n-channel select transistors are added to form a six transistor cell. do. Polysilicon load resistors have been used in place of PMOS transistors to reduce cell size. In addition, two n-channel pull-down transistors and two leakage p-channel load / select transistors have been proposed to further reduce cell size. In addition, there are application-specific variations of the basic SRAM cell. These application-specific SRAMs contain separate logic circuitry that makes them compatible for a particular task. For example, it is useful for cache structures that are accessed through 8-transistor, dual-stage, dual-port cell transfer ports and embedded in the microprocessor's memory. Nine transistor content addressable memory cells are used in applications where both the cell content and location are known.

In each application, there is a need to reduce the total area needed to make a valid and reliable SRAM cell, as well as to increase the access speed while reducing the power consumed by the SRAM cells. Power can be reduced by lowering the supply voltage. However, both speed and stability are degraded due to the low supply voltage. Thus, there is a need for low power (low operating voltage) SRAM cells with increased access speed and good stability.

1 is a circuit diagram of an SRAM cell of one embodiment of the present invention. The cell of Figure 1 is preferred for operation at supply voltages of approximately 0.6 volts or less.

2 is a plan view of an SRAM cell of the embodiment of the present invention shown in FIG. 2 illustrates a possible cell layout in a Silicon-On-Insulator (SOI) process.

3A is a plan view of an SRAM cell of the embodiment of the present invention shown in FIG. 3B is a cross-sectional view of a partially detailed device of an embodiment of the present invention, in which FIG. 3B is along the line A′-A ′ of FIG. 3A. 3A and 3B show possible cell layouts implemented in SOI processing.

4A is a plan view of an SRAM cell of the embodiment of the present invention shown in FIG. 4B is a cross-sectional view of a partially detailed device of an embodiment of the present invention, in which FIG. 4B is taken along line A'-A 'of FIG. 4A; 4A and 4B show possible cell layouts implemented in bulk CMOS processing.

5 is a circuit diagram of an SRAM cell of another embodiment of the present invention. The cell of Figure 5 is preferred for operation at approximately 0.6 volt supply voltage.

6A is a top view of an SRAM cell of the embodiment of the present invention shown in FIG. 6B is a cross-sectional view of a partially detailed device of an embodiment of the present invention, in which FIG. 6B is taken along the line A′-A 'of FIG. 6A; 6A and 6B show possible cell layouts implemented in SOI processing.

7A is a top view of an SRAM cell of the embodiment of the present invention shown in FIG. FIG. 7B is a cross-sectional view of a partially detailed device of an embodiment of the present invention in which FIG. 7B is taken along the line A′-A ′ of FIG. 7A. 7A and 7B show possible cell layouts implemented in bulk CMOS processing.

<Explanation of symbols for the main parts of the drawings>

227: P type diffusion

228: N type diffusion

102, 224: poly

214, 202, 308, 310: Contact

301: insulation layer

304: separation area

322: P type body

320: N-type body

An embodiment of the present invention provides a first transistor having a control electrode and a current path, and a backgate / body connection of the control electrode, the current path, and the backgate / body connection-second transistor includes a control electrode of the second transistor and a first transistor. And a second transistor having an electrical connection to the current path of the transistor. In another embodiment, the memory device comprises a third transistor having a control electrode and a current path, and the backgate / body connection of the control electrode, current path and backgate / body connection-fourth transistor is a control electrode of the fourth transistor. And a fourth transistor having an electrical connection with a current path of the third transistor. In another embodiment, the third transistor has a backgate / body connection electrically connected to the backgate / body connection of the second transistor, wherein the first transistor is electrically connected to the backgate / body connection of the fourth transistor. It has a connected backgate / body connection. In another embodiment, the backgate / body connection of the second transistor electrically connected to the control electrode of the second transistor is performed by a first diode (preferably a Schottky diode), The backgate / body connection of the fourth transistor, which is electrically connected to the control electrode, is carried out by a second diode (preferably a Schottky diode).

Another embodiment of the invention is a first transistor having a gate electrode, a first source / drain region and a second source / drain region, and a gate electrode, a first source / drain region, a second source / drain region, and a backgate. / Body Connection-The backgate / body connection of the second transistor is a memory device including a second transistor having a gate electrode of the second transistor and electrically connected to the first source / drain region of the first transistor. In another embodiment, the memory device comprises a third transistor having a gate electrode, a first source / drain region and a second source / drain, and a gate electrode, a first source / drain region, a second source / drain region and a back The fourth transistor has a gate / body connection, the backgate / body connection of the fourth transistor being electrically connected to the gate electrode of the fourth transistor and the first source / drain region of the third transistor. In another embodiment, the third transistor has a backgate / body connection electrically connected to the backgate / body connection of the second transistor, and the first transistor is electrically connected to the backgate / body connection of the fourth transistor. It has a backgate / body connection. In another embodiment, the backgate / body connection of the second transistor electrically connected to the gate electrode of the second transistor is performed by a first diode (preferably a Schottky diode), The backgate / body connection of the fourth transistor, which is electrically connected to the gate electrode, is carried out by a second diode (preferably a Schottky diode).

Like reference numerals are used to denote similar or identical parts throughout the drawings. These parts are not drawn to scale. These are merely provided to illustrate the idea of the method of the present invention.

The SRAM cell of the present invention is schematically shown in FIG. The cell of Figure 1 is preferred for operation at a supply voltage of about 0.6 volts. Transistors 112 and 128 are shown as pMOS transistors and transistors 108 and 130 are shown as nMOS transistors, but these transistors may be nMOS and pMOS, respectively. By the way, if it is changed in this way, it is preferable that another biasing state is used and the diffusion region in the figure needs to be formed of the opposite conductivity type dopant. In addition, the schematics and layouts shown in FIGS. 2, 3A-3B, 4A-4B, 5, 6A-6B, and 7A-7B are provided merely as examples of possible variations of cell schematics and possible layout implementations among various cell designs. The cell of FIG. 5 has a maximum body-source voltage of supply voltage less than the diode voltage drop, and is therefore preferred for operation at supply voltages above approximately 0.6 volts. Whether more optimal or less optimal, schematics and layouts should be apparent to those skilled in the art based on this specification and drawings. Other configurations of the cell, including various body / backgate connections, should be apparent to those skilled in the art based on this description.

The SRAM cell 100 of the present invention uses a body connection (in a SOI configuration) or a well connection (in a bulk silicon configuration) to determine the threshold voltage (V _T ) of the nMOS and / or pMOS transistors of the SRAM cell 100. Adjust The backgate connection can be used for dual gate transistors. These other specific connections are called body connections in the following text. High body voltage results in low V _T for nMOS devices and high V _T for pMOS devices. Likewise, a low body voltage produces high V _T for nMOS devices and low V _T for pMOS devices. Preferably, the body-source junction is not forward biased by at least about 0.75V (or more preferably at most 0.6V). The variation in V _T due to the variation in body voltage is preferably at least about 0.1 V. For the drive transistors 108 and 130, higher drive currents are preferred during read operations because the memory cells become more stable. However, during the standby mode (or the storage mode), it is desirable that the leakage current is low so that the standby power is reduced. The body / backgate connection of the present invention allows these two states to be more easily met.

1 and 2, the SRAM cell 100 uses two input / output lines, commonly referred to as bit lines. These two lines read without an upset and allow symmetrical writing of '1' and '0'.

In order to preserve the information stored in the SRAM cell 100, the word line 102 ("WL") is at a high level (preferably 0.75 volts or less-more preferably 0.65 volts or less, even more preferably 0.6 volts or less). It becomes At the same time, a high level signal (logical "1") is applied to both BLT 106 and BLF 104. This is the precharge value applied to the BLT 106 and BLF 104 under normal operation. Because it stores '1' (node 110 high), the leakage current through transistor 112 should be greater than the leakage current through transistor 108. For the option that the body node of transistor 112 is tied to node 111, transistor 112 will be at low Vt, high leakage state (node 111 is low-logic "0"), which is a node. Facilitate storage of high voltages on 110. At the same time, a low bias applied to the body of the drive transistor 108 raises the Vt of the transistor 108, thus reducing its leakage and facilitating the storage of high voltages on the node 110. The high voltage on node 110 is applied to the gate of drive transistor 130 (which has a low V _T due to the higher bias on body / backgate 142). The low Vt on transistor 130 is effective because it is a holding node 111 to logic '0'. Since the pass transistor 128 has a relatively low leakage current due to the high voltage on its body 138, the power becomes small during its operation (referred to as a storage operation or a standby mode).

In order to read the bits from the storage cell 100 of the present invention, the BLT 106 and the BLF 104 are precharged with logic '1' and the word line WL 102 has a logic "0" value. For the stored '1' case, line 110 would be a "1" value (high value), while line 111 would be a "0" value (low value). Thus, transistors 108 and 128 will have a relatively high V _T and transistors 112 and 130 will have a relatively low V _T. Since pass transistor 128 is challenging, this will bring BLF 104 to a logic "0" level while BLT 106 will maintain a logic "1" value. The drive cell for the drive transistor 130 is increased with a new application of bias to the body / backgate connection 142 and the VT is increased for the pass transistor 128 by a new application of this bias in this cell, thus storing the cell. 100 not only has an increased read current, but also has a high bistable and high static noise margin.

In order to write a '0' bit into the storage cell 100 of the present invention, the WL 102 is in a logic "0" state, the BLF 104 is in a logic "1" state, and the BLT 106 is a logic. Transition from the "1" state to the logical "0" state. Prior to the transition of the BLT 106 from the "1" state to the "0" state, the line 110 is in the "1" state and the line 111 is in the "0" state. Transistor 112 in the low Vt state and transistor 108 in the high Vt state facilitate lowering node 110. This turns off transistor 130 and also raises Vt of transistor 130 while lowering Vt of transistor 128. This facilitates the rise of node 111 to a high value, logical '1' state.

2 shows a possible layout structure for the SRAM cell of the present invention. In this embodiment, the WL 102 is preferably doped polycrystalline silicon ("poly" or "polysilicon"), which may or may not be silicided, or having a work function similar to a medium gap material or p-type and n-type poly It is implemented using one or two metals, one of which. The following metals may be included: Ti, TiN, Ta, TaN, W, tungsten nitride, or other metals commonly used to form gate structures. WL 102 also forms a gate to pass transistor 112 and pass transistor 128, which is why the material used to form WL 102 needs to be carefully selected.

Conductor 218 forms a line 111 of FIG. 1, and conductor 234 forms a line 110 of FIG. 1. Connections 218 and 234 are preferably composed of metal (preferably copper, aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, stacks of any of the above or combinations thereof) or silicide polys. Contact 225 connects conductor 218 to underlying conductive structure 224. Preferably, conductive structure 224 is a doped poly, which may or may not be silicided (preferably by either cobalt or titanium), or among those having a work function similar to a medium gap material or p- and n-type poly. It consists of one or two metals that are one. The following metals may be included: Ti, TiN, Ta, TaN, W, tungsten nitride, or other metals commonly used to form gate structures. The conductive structure 224 forms a gate to the drive transistor 108.

The contact 235 connects the conductor 218 to the p-type diffusion region 210 (which is the drain of the pass transistor 218) and the n-type diffusion region 236 (which is the source region of the drive transistor 130). Contact 235 may be formed directly at the junction of regions 210 and 236 to form a connection on both sides (as shown in FIG. 2), or if these regions are silicided, contact 235 may be a silicided region. It can be formed anywhere along. Contact 220 connects conductor 234 to conductor 242, which forms a gate to drive transistor 130. Preferably, conductor 242 is one of doped poly, which may or may not be silicided (preferably by either cobalt or titanium), or one having a work function similar to a medium gap material or p-type and n-type poly It consists of one or two metals. The following metals may be included: Ti, TiN, Ta, TaN, W, tungsten nitride, or other metals commonly used to form gate structures. The conductive structure 224 forms a gate to the drive transistor 108. The contact 232 connects the conductor 234 to the p-type diffusion region 208 (which is the drain of the pass transistor 112) and the n-type diffusion region 228 (which is the source region of the drive transistor 108). Contact 232 may be formed directly at the junction of regions 208, 228 to form a connection on both sides (as shown in FIG. 2), or if these regions are silicided, contact 232 may be a silicided region. It can be formed anywhere along.

Contacts 214 and 216 provide connections to the V _SS supply and contacts 202 and 204 provide connections to the BLT 106 and BLF 104 respectively. Contact 220 along with diffusion regions 209 and 237 provide a body / backgate connection to drive transistor 130 and pass transistor 128 if at least these connections are formed. The SRAM cells of the present invention utilize one or both of these connections, but do not require both at the same time. Likewise, contact 225 along with diffusion regions 207 and 227 form a body / backgate connection to pass transistor 112 and drive transistor 108 if at least these connections are formed. One or both of these connections may be formed within the SRAM cell of the present invention (junction with one or both of the body / backgate for drive transistor 130 and pass transistor 128).

Portions in the embodiments of the invention shown in FIGS. 3A-3B, 4A-4B, 5, 6A-6B and 7A-7B with the same reference numerals are similar or identical parts. By the way, the backgate connections in the figures showing devices formed on and within the silicon substrate have the same reference numerals as the body connections in the figure showing a device formed of the SOI structure. Although they are not exactly the same parts, they are still given the same reference numerals. The same is true for these regions of FIGS. 6A-6B and 7A-7B where Schottky diodes are formed. One of ordinary skill in the art will be able to identify these differences based on the present quotation and drawings. The following description of the embodiments of the invention shown in FIGS. 3A-3B, 4A-4B, 5, 6A-6B, and 7A-7B will not describe these parts again unless further explanation is required.

Substrate 300 may be made from single crystal silicon, which may be doped with p-type or n-type, or with an epitaxial silicon layer (preferably doped with p-type and / or n-type) formed on the single crystal silicon substrate. It may be configured. The SOI structure of the embodiments of FIGS. 3A-3B and 6A-6B preferably consists of a silicon layer formed on the silicon dioxide layer, which is formed on the silicon substrate. This structure may be formed using any conventional SOI body forming process.

In light of the teachings and citations of the present invention, some additional embodiments should be apparent to those of ordinary skill in the art. For example, although isolation region 304 is shown as a shallow trench isolation structure, any type of isolation structure (LOCOS, field oxide region, or doped isolation structure, etc.) may be used to fabricate devices of the present invention. Can be. In addition, these doped regions and polycrystalline silicon structures are suicided (preferably using titanium silicide, cobalt silicide, tungsten silicide, or tantalum silicide), but these structures need not be silicided. This silicide not only reduces the resistance of these structures but also allows the interconnect and contacts to be positioned anywhere along the silicided structure (not necessarily at the junction of two doped regions, for example). It is preferable because it makes it easy.

Referring to the embodiment of FIGS. 3A-3B, the conductors 218, 234 have been modified from the embodiment of FIG. 2 to provide another body connection. For example, conductors 398 and 399 were connected to conductors 218 and 234, respectively, to facilitate connection to these other body connections. Further contacts 306, 308, 310, 312 are shown to interconnect the doped body connections 227 and 207, 209, and 237 to the gate lines 224, 242, respectively.

3B shows a silicon substrate 300, an insulating layer 301 and a silicon layer 303 (preferably composed of single crystal silicon or epitaxial silicon—to be doped with n-type, both p-type, or portions of each type The SOI body structure). Body regions 320 and 322 form a channel region of the gate structure. As can be seen in the preferred material list 390 (bottom of the figure), region 322 is preferably a lightly doped p-type region and region 320 is a lightly doped n-type region. Regions 320 and 322 are preferably layer 303 either at or after layer 303 is formed but before formation of gate structures (ie, gate electrodes, underlying gate insulators and insulating sidewalls). Is formed by doping.

The embodiments of the present invention shown in FIGS. 6A and 6B differ from FIGS. 3A and 3B except for the formation of Schottky diodes 502 (optional), 504, 507, 508 (optional) in the embodiment of FIGS. 6A and 6B. same. In other words, FIGS. 3A and 3B form a direct connection from the backgate / body portion to other conductive lines. By the way, in the embodiment of FIGS. 6A and 6B, these connections are formed via a Schottky diode (as shown in FIG. 5). The formation of these diodes essentially directly affects the doping level (and possibly dopant and silicide formation) of regions 207, 209, 227, 237. Another example can be seen in FIG. 6B. Contact 308, 310 is not connected to p-type diffusion 227 and n-type diffusion 207, respectively, as shown in FIG. 3B, and the embodiment of FIG. 6B is p-type to connect to form a Schottky diode Body 227 and n-type body 207 are used, respectively. The rest of these structures must be identical.

4A and 4B and 7A and 7B, where FIGS. 4A and 4B are based on the SRAM device of FIG. 1 and FIGS. 7A and 7B are the SRAM of FIG. 5 using a Schottky diode in the backgate / body connection. It is different in that it is based on the device. Thus, the difference between these two embodiments is the configuration of the regions 207, 209, 227, 237 (dopant level and possibly dopant, but not dopant type, and whether there is silicidation). This can be seen in FIG. 7B where contacts 308 and 310 connect to p-type well 406 and n-type well 402, respectively, instead of p-type diffusion 227 and n-type diffusion 207, respectively.

These two embodiments, in the embodiment of FIG. 2, doped regions 228 and 236 are adjacent to oppositely doped regions 208 and 210, respectively, but in the embodiments of FIGS. 4A-4B and 7A-7B these regions are separated. It differs from the embodiment of FIG. 2 in that it is separated by the regions 304. In order to connect these conversely doped regions in the embodiments of FIGS. 4A-4B and 7A-7B, conductors 218 and 234 are connected to additional conductive elements (conductors 333 and 337, etc.) and additional interconnections. (328, 332, 335, 336, etc.). Interconnect 308 and 310 (with 733) and 306 and 312 (with 737) provide a backgate connection to provide the desired threshold voltage control of the present invention. Preferably, using the same material, areas with similar intersecting parallel fringes are formed simultaneously. Preferred materials 390 for each structure are shown directly below FIGS. 4B and 7B. By the way, other materials and dopants may be used. Deep well regions (well regions 404, etc.) are preferably more lightly doped and then become shallower well regions (p wells 406 and n wells 402, etc.), and these shallower wells are preferably Is doped at a lower concentration and then becomes p-type diffusion (regions 208, 227, etc.) and n-type diffusion (regions 207, 228, etc.), which are preferably formed during the source / drain implantation step. The same is true for Figs. 2, 3a-3b and 6a-6b.

A silicide blocking layer is provided during processing to block the formation of silicide in region 302. This is desirable to ensure that the junction between two differently doped regions is not shorted by silicide.

In another embodiment, the backgate / body connections 114, 118 may be connected without connecting to the gate of the transistor 108. Similarly, backgate / body connections 138 and 142 may be connected without connecting to the gate of transistor 130. In another embodiment, the backgate / body connection 138 may be connected to the gate of the transistor 130 without connecting the backgate / body connection 142 to the gate of the transistor 130. Similarly, backgate / body connection 118 may be connected to the gate of transistor 108 without connecting backgate / body connection 114 to the gate of transistor 108.

According to the present invention, it was possible not only to reduce the total area required to make an effective and reliable SRAM cell, but also to increase the access speed while reducing the power consumed by the SRAM cells. Thus, a low power SRAM cell with increased access speed and good stability has been provided.

While specific embodiments of the invention have been described herein, they should not be construed as limiting the scope of the invention. Many embodiments of the invention will be apparent to those skilled in the art in light of the methods herein. It is intended that the scope of the invention only be limited by the appended claims.

Claims (16)

In a memory device, A first transistor having a control electrode and a current path; And A second transistor having a control electrode, a current path and a backgate / body connection, wherein the backgate / body connection of the second transistor is electrically connected to the control electrode of the second transistor and the current path of the first transistor being- Memory device comprising a. The method of claim 1, A third transistor having a control electrode and a current path; And A fourth transistor having a control electrode, a current path and a backgate / body connection, wherein the backgate / body connection of the fourth transistor is electrically connected to the control electrode of the fourth transistor and the current path of the third transistor being- The memory device further comprises. The method of claim 2, And the third transistor has a backgate / body connection electrically connected to the backgate / body connection of the second transistor. The method of claim 2, And the first transistor has a backgate / body connection electrically connected to a backgate / body connection of the fourth transistor. The method of claim 1, And said backgate / body connection of said second transistor electrically connected to said control electrode of said second transistor is effected by a first diode. The method of claim 5, And the first diode is a Schottky diode. The method of claim 1, And the backgate / body connection of the fourth transistor electrically connected to the control electrode of the fourth transistor is executed by a second diode. The method of claim 7, wherein And said second diode is a Schottky diode. In a memory device, A first transistor having a gate electrode, a first source / drain region and a second source / drain region; And A second transistor having a gate electrode, a first source / drain region, a second source / drain region, and a backgate / body connection, wherein the backgate / body connection of the second transistor is connected to the gate electrode of the second transistor and the Electrically connected to the first source / drain region of a first transistor Memory device comprising a. The method of claim 9, A third transistor having a gate electrode, a first source / drain region and a second source / drain; And A fourth transistor having a gate electrode, a first source / drain region, a second source / drain region, and a backgate / body connection, wherein the backgate / body connection of the fourth transistor is connected to the gate electrode of the fourth transistor and the Electrically connected to the first source / drain region of a third transistor; The memory device further comprises. The method of claim 10, And the third transistor has a backgate / body connection electrically connected to the backgate / body connection of the second transistor. The method of claim 10, And the first transistor has a backgate / body connection electrically connected to the backgate / body connection of the fourth transistor. The method of claim 9, And said backgate / body connection of said second transistor electrically connected to said gate electrode of said second transistor is effected by a first diode. The method of claim 13, And the first diode is a Schottky diode. The method of claim 9, And said backgate / body connection of said fourth transistor electrically connected to said gate electrode of said fourth transistor is effected by a second diode. The method of claim 15, And said second diode is a Schottky diode.