JP2005302124A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of guaranteeing a fast operation while soft error resistance is increased. <P>SOLUTION: This semiconductor memory device includes a memory cell formed on a silicon-on-insulator (SOI) substrate. The memory cell includes a pair of n type resistance added transistors TN5 and TN6 in which a gate is connected to a word line WL, a body is connected to the output nodes N3 and N4 of a pair of inverters INV1 and INV2, and a source and a drain interconnect the input nodes N1 and N2 and the output nodes N3 and N4 of the pair of inverters INV1 and INV2. The n type resistance added transistors TN5 and TN6 are source tie (ST) type MOS transistors, and a conductive state is set between the source and the drain in the nonaccessed state of the memory cell. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including SRAM (Static Random Access Memory) memory cells.

In recent years, with the improvement of the degree of integration of SRAM, measures for preventing soft errors have become important. As a countermeasure against such a soft error, there is one that uses a time constant to support the potential of the storage node (see Patent Document 1). However, using the time constant becomes a factor that causes a decrease in the operation speed when accessing the memory cell. In addition, with the miniaturization of semiconductor devices, it is difficult to secure a sufficient capacity, and measures combined with other elemental technologies are forced to significantly change the process, and an increase in cost is inevitable. In addition, application of SOI technology has been proposed as one of techniques for improving soft error resistance, but sufficient resistance improvement effect is not obtained only with SOI technology.
Japanese Patent Application Laid-Open No. 5-198182

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device capable of ensuring high-speed operation while improving soft error resistance.

  (1) The present invention is a semiconductor memory device including a memory cell formed on an SOI (Silicon On Insulator) substrate, the memory cell having a first conductivity type load whose source is connected to a high-potential power line. Including a transistor and a second conductivity type driving transistor whose source is connected to a low-potential power line, wherein the load transistor and the gate of the driving transistor are connected to form an input node, and the load transistor and the driving transistor A pair of inverters that constitute an output node by connecting drains of transistors, a gate is connected to a word line, a body is connected to the output node of the pair of inverters, and a source and a drain are the pair of inverters A pair of second conductors interconnecting the input node of one of the inverters and the output node of the other inverter And a pair of second conductivity type transfer transistors having a source and a drain connected between the output node of the inverter and a bit line, and a gate connected to a word line, The resistance addition transistor is an ST (Source Tie) type MOS transistor, and relates to a semiconductor memory device in which a source and a drain are electrically connected in a non-access state of the memory cell.

  According to the present invention, since the gate of the resistance-added transistor is connected to the word line, the resistance-added transistor has a low resistance when accessing the memory cell, and has a higher resistance when not accessing than when accessing. Further, since the resistance addition transistor of the second conductivity type is conductive between the source and the drain when the memory cell is not accessed, the loop of the inverter latch constituting the memory cell is not cut. For this reason, according to the present invention, the data holding operation can be surely ensured despite the provision of the resistance addition transistor having a high resistance when the memory cell is not accessed. According to the present invention, when the data holding operation is performed when the memory cell is not accessed, the resistance-added transistor has a high resistance. It is possible to prevent data reversal due to incidence such as In addition, when the memory cell is accessed, the resistance between the source and drain of the resistance-added transistor is reduced by applying a cell selection signal from the word line as compared to when the memory cell is not accessed, so that the speed of writing / reading operation is reduced. There is no.

  In the present invention, an ST (Source Tie) type MOS transistor is employed as the resistance addition transistor. In the present invention, the input node potential of the inverter can be stabilized by providing a pair of resistance addition transistors and connecting the bodies of the respective transistors to the output nodes of the pair of inverters. As a result, the unstable state of the input node potential of the inverter caused by adding the resistance addition transistor in series between the inverters can be eliminated, and an increase in current consumption during standby of the memory cell can be suppressed.

  (2) In the semiconductor memory device of the present invention, the load transistor and the drive transistor may have a body contact that connects a source and a body. In this way, the capacity can be added to the storage node by increasing the gate capacity of each transistor constituting the inverter. That is, the loop time constant for maintaining the potential of the storage node at the time of incidence of α rays or the like can be increased.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing an equivalent circuit of an SRAM memory cell (hereinafter simply referred to as a memory cell) which is a semiconductor memory device of the present embodiment.

  The memory cell of this embodiment is composed of eight MOS transistors formed using an SOI substrate. The p-type (first conductivity type) load transistor TP1 and the n-type (second conductivity type) drive transistor TN1 form a first CMOS inverter INV1. The p-type additional transistor TP2 and the n-type drive transistor TN2 form a second CMOS inverter INV2. The sources of the p-type load transistors TP1 and TP2 are connected to the high potential power supply line VDD (power supply voltage Vdd). The sources of the n-type drive transistors TN1 and TN2 are connected to the low potential power supply line VSS (power supply voltage Vss). The gates of the p-type load transistor TP1 and the n-type drive transistor TN1 are connected to each other, and the connection node forms the input node N1 of the first CMOS inverter INV1. The p-type load transistor TP1 and the n-type drive transistor TN1 have their drains connected to each other, and the connection node forms the output node N3 of the first CMOS inverter INV1. The gate of the p-type load transistor TP2 and the gate of the n-type drive transistor TN2 are connected, and the connection node forms the input node N2 of the second CMOS inverter INV2. The drain of the p-type load transistor TP2 and the drain of the n-type drive transistor TN2 are connected, and the connection node forms the output node N4 of the second CMOS inverter INV2.

  In the first and second COMS inverters INV1 and INV2, an input node N1 and an output node N4 are connected via an n-type resistance addition transistor TN6, and an output node N3 and an input node N2 are connected to an n-type resistance addition transistor TN5. To form a flip-flop. This flip-flop is connected to the bit line BL and the inverted bit line / BL by a pair of n-type transfer transistors TN3 and TN4 whose gate is connected to the word line WL and which is turned on / off by a predetermined selection potential. In addition, the first and second CMOS inverters INV1 and INV2 have their input / output nodes connected to each other, so that the potentials of the input nodes N1 and N2 of the inverters are complementary by the loop holding operation of the inverter latch. In addition, the potentials of the output nodes N3 and N4 of the inverters serving as storage nodes are also in a complementary relationship.

  In the memory cell of the present embodiment, the n-type resistance-added transistors TN5 and TN6 are provided between the input and output nodes of the first and second CMOS inverters INV1 and INV2, thereby storing memory at the time of incidence of α rays or the like. Data inversion is prevented. The n-type resistance addition transistors TN5 and TN6 are STMOS transistors in which the source and the body are connected. Specifically, when the gate voltage is the low-potential-side power supply voltage Vss and the body potential is the high-potential-side power supply voltage Vdd, a MOS current flows from several tens of nA to several μA between the source and drain. Any transistor may be used. The n-type resistance-added transistors TN5 and TN6 have a gate connected to the word line WL, so that the resistance between the source and the drain becomes low when accessing the memory cell, and the operation speed is guaranteed. The resistance between the drain and the drain becomes high, and the loop time constant of the inverter latch is increased as compared with the conventional memory cell structure, so that the change of the node potential when α rays or the like are incident can be effectively delayed. In this case, the resistance value between the source and drain of the n-type resistance addition transistors TN5 and TN6 at the time of non-access can secure a loop time constant sufficient for soft error countermeasures, and the loop of the inverter latch It can be set within a range (eg, several tens of kΩ to several tens of MΩ) that is reliably maintained and does not undesirably affect the data holding operation.

  The n-type resistance addition transistors TN5 and TN6 are ST (Source Tie) type MOS transistors in which the source 12a and the body 11 shown in FIG. 2 are connected. The n-type resistance addition transistors TN5 and TN6 include a body 11 made of a p-type semiconductor layer, a source 12a made of an n-type semiconductor layer provided on both sides of the body 11, and a drain 12b on an insulating film 10 constituting an SOI substrate. Is formed. A gate 14 made of polysilicon or the like is formed on the body 11 via a gate insulating film 13. In the n-type resistance addition transistors TN5 and TN6, the body 11 and the source 12a are connected, and the threshold voltage Vt can be changed by controlling the body potential. Each transistor is isolated by STI 16. The n-type resistance addition transistors TN5 and TN6 are formed so as to have a threshold voltage Vt lower than that of other transistors constituting the memory cell, and the source even when the memory cell is not accessed due to a leakage current at the time of off. A current-carrying region for conducting between the drains is secured. For example, the threshold value can be lowered by introducing an n-type impurity into the channel formation region of the body 11 immediately below the gate insulating film 13 and adjusting the impurity concentration.

  The bodies of the n-type resistance addition transistors TN5 and TN6 are connected to the output nodes N3 and N4 of the first and second CMOS inverters INV1 and INV2. That is, the body potentials of the n-type resistance addition transistors TN5 and TN6 are controlled by the potentials of the output nodes N3 and N4, and as a result, the threshold voltage Vt is controlled. Then, in the standby state of the memory cell, the resistance addition transistor TN5 (TN6) connected to the output node N3 (N4) on the high potential side is controlled so that the threshold voltage Vt decreases. Therefore, in the memory cell of this embodiment, the input node potential on the high potential side is not significantly lowered, and an increase in current consumption during standby can be suppressed. In order to sufficiently lower the threshold voltage Vt of the n-type resistance addition transistors TN5 and TN6 to such an extent that a drop in the input node potential does not become a problem, a method of introducing a large amount of n-type impurities into the body may be adopted. Conceivable. However, it is difficult to precisely control the impurity concentration distribution in the body. In contrast, STMOS is excellent in controllability of the threshold voltage Vt, so that a semiconductor memory device can be produced with a high yield. Hereinafter, the effect of suppressing the consumption current due to the adoption of STMOS as the n-type resistance addition transistors TN5 and TN6 will be described in detail.

  First, when the memory cell is not accessed, in each of the first and second CMOS inverters INV1 and INV2, the inverters INV1 and INV2 perform a latch operation, and the potentials of the input nodes N1 and N2 become complementary and stable. It will be in the standby state. Specifically, one node potential of the input nodes N1 and N2 becomes the high potential HIGH (voltage Vdd), and the other node potential becomes the low potential LOW (voltage Vss).

  However, in the memory cell of this embodiment, the n-type resistance addition transistors TN5 and TN6 are connected in series between the input nodes N1 and N2 and the output nodes N3 and N4 of the first and second CMOS inverters INV1 and INV2. It is connected. When the n-type resistance addition transistors TN5 and TN6 are normal MOS transistors, the potentials of the input nodes N1 and N2 of the inverters INV1 and INV2 are the n-type resistance addition transistors TN5 and TN6 when accessing the memory cell. Attempts to stabilize in a state where the voltage drops by the threshold value Vt. That is, the voltage Vdd−Vt, which is a voltage drop from the high potential HIGH by the threshold voltage Vt, is applied to the gate of the p-type load transistor TP1 (TP2) of the inverter whose input node potential should be the high potential HIGH. Since the p-type load transistor TP1 (TP2) is not completely turned off, a through current flows between the p-type load transistor TP1 (TP2) and the n-type load transistor TN1 (TN2). Become. When a large number of memory cells in which such a through current always flows until the standby state is integrated in a large amount, a great increase in current consumption is caused.

  Therefore, in the memory cell of the present embodiment, STMOS is employed as the n-type resistance addition transistors TN5 and TN6, and the body is connected to the output nodes N3 and N4 so that the potentials of the input nodes N1 and N2 are complementary. While maintaining the relationship, the influence of the voltage drop of the input node potential on the high potential HIGH side is reduced.

  Specifically, in the n-type resistance-added transistor TN5 (TN6) whose body is connected to the output node N3 (N4) to be the high potential HIGH, the threshold voltage Vt is controlled by the output node potential in a decreasing direction. The input node potential on the high potential HIGH side to which the source or drain is connected is hardly lowered. For this reason, the p-type load transistor TP1 (TP2) on the high potential HIGH side can be reliably turned off.

  For example, the input node N1 of the first CMOS inverter INV1 and the output node N4 of the second CMOS inverter INV2 are high potential HIGH, and the input node N2 of the second CMOS inverter INV2 and the output of the first CMOS inverter INV1 Consider a case where the node N3 is at a low potential LOW. In this case, the body potential of the n-type resistance addition transistor TN6 increases to near the voltage Vdd due to the potential of the output node N4, and the threshold voltage Vt decreases. In addition, a current flows directly from the body to the input node N1 through the pn junction. For this reason, the input node N1 on the high potential HIGH side to which the source or drain of the n-type resistance addition transistor TN6 is connected hardly drops in voltage, and the p-type load transistor TP1 can be reliably turned off. . As a result, the logical states of the input nodes N1 and N2 of the first and second CMOS inverters are appropriately maintained, so that the current consumption during standby can be effectively reduced without affecting the storage operation of the stored data. Can be suppressed.

  From the standpoint of suppressing current consumption during standby, the thresholds of the p-type load transistors TP1 and TP2 are increased to further influence the voltage drop at the input nodes N1 and N2 by the n-type resistance addition transistors TN5 and TN6. It can be reduced.

  Next, the effect of the soft error countermeasure in the memory cell of this embodiment will be described with reference to FIG.

  The solid line in FIG. 3 indicates the potential change of the output node N3 (or N4) in the memory cell when the α ray or the like is incident in a single shot. When the node potential is HIGH (voltage Vdd) and α rays or the like are incident on the transistor in a single shot, it changes to LOW (voltage Vss) for a very short time (about several ns). Thereafter, the generated charges disappear rapidly due to recombination or the like, but once the node potential is reversed, the data stored in the memory cell may be reversed. Such a phenomenon becomes more prominent as the power supply voltage is lowered.

  However, in the memory cell of the present embodiment, when the data holding operation is performed at the time of non-access, the transistor on the side where the source / drain voltage becomes LOW among the n-type resistance addition transistors TN5 and TN6 is in the high resistance state. It has become. For this reason, as shown by the broken line in FIG. 3, the loop time constant of the inverter latch is increased by the source-drain resistance of the n-type resistance addition transistors TN5, TN6, and the output nodes N3, N4 are The time for the node potential to change to the power supply voltage Vss side on the low potential side can be delayed. Further, in the memory cell of the present embodiment, the threshold value of the n-type resistance-added transistor on the side where the source / drain voltage becomes HIGH also increases as the input node potential, that is, the body potential falls, and the LOW pulse is transmitted. Can be prevented. Therefore, the inversion of stored data can be prevented more effectively.

  In addition, according to the memory cell of the present embodiment, the n-type resistance addition transistors TN5 and TN6 are electrically connected between the source and the drain when the memory cell is not accessed. There is no cutting. Therefore, according to the memory cell of the present embodiment, the data holding operation can be surely ensured despite the provision of the n-type resistance addition transistors TN5 and TN6 that have a high resistance when not accessed. Furthermore, in the memory cell of the present embodiment, the cell-select signal from the word line WL is applied at the time of access, so that the resistance between the source and drain of the n-type resistance addition transistors TN5 and TN6 is significantly lower than that at the time of non-access. Therefore, the speed of the writing / reading operation does not decrease.

  In the first and second CMOS inverters INV1 and INV2 of the memory cell of the present embodiment, the p-type load transistors TP1 and TP2 and the n-type drive transistors TN1 and TN2 are body contacts in which the body and the source are connected. Can have. In this way, by increasing the gate capacitance of each transistor, it is possible to add capacitance to the output nodes N1 and N2 serving as storage nodes. That is, the loop time constant for maintaining the potentials of the output nodes N1 and N2 at the time of incidence of α rays or the like can be increased. In this case, it is desirable that the n-type transfer transistors TN3 and TN4 also have a body contact that connects the body to the low-potential power supply line VSS. However, the n-type transfer transistors TN3 and TN4 have pass gate leaks and n-type transfer transistors TN3 and TN4. When the current amplification factor ratio in relation to the drive transistors TN1 and TN2 does not matter, the bodies of the n-type transfer transistors TN3 and TN4 may be in a floating state.

  Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the invention.

FIG. 3 is an equivalent circuit diagram showing the SRAM memory cell of the present embodiment. FIG. 3 is a cross-sectional view of a resistance addition transistor constituting the SRAM memory cell of the present embodiment. The characteristic view which shows the node potential in the SRAM memory cell at the time of alpha ray incidence.

Explanation of symbols

TP1, TP2 p-type load transistor, TN1, TN2 n-type drive transistor, TN3, TN4 n-type transfer transistor, TN5, TN6 n-type resistance addition transistor, INV1 first CMOS inverter, INV2 second CMOS inverter, N1, N2 Input node, N3, N4 output node

Claims (2)

A semiconductor memory device including a memory cell formed on an SOI (Silicon On Insulator) substrate,
The memory cell is
A first conductivity type load transistor having a source connected to a high potential power line; and a second conductivity type drive transistor having a source connected to a low potential power line, wherein the load transistor and the gate of the drive transistor are connected to each other. Are connected to form an input node, and a drain of the load transistor and the drive transistor are connected to each other to form an output node;
A gate is connected to a word line, a body is connected to the output node of the pair of inverters, and a source and a drain are connected to the input node of one inverter of the pair of inverters and the output node of the other inverter. A pair of second conductivity type resistance-added transistors connected to
A pair of second conductivity type transfer transistors having a source and a drain connected between the output node of the inverter and a bit line and a gate connected to a word line;
Including
The resistance-added transistor is an ST (Source Tie) type MOS transistor, and is electrically connected between a source and a drain in a non-access state of the memory cell. In claim 1,
The load transistor and the drive transistor have a body contact that connects a source and a body.

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