JP4339169B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including an SRAM (Static Random Access Memory).

In recent years, with the improvement of the degree of integration of SRAM, measures for preventing soft errors have become important. As a countermeasure against such a soft error, there is one that uses a time constant to support the potential of the storage node (see Patent Document 1). However, using the time constant becomes a factor that causes a decrease in the operation speed when accessing the memory cell. In addition, with the miniaturization of semiconductor devices, it is difficult to secure a sufficient capacity, and measures combined with other elemental technologies are forced to make significant process changes, and cost increases cannot be avoided. In addition, application of SOI technology has been proposed as one of techniques for improving soft error resistance, but sufficient resistance improvement effect has not been obtained with SOI technology alone.
Japanese Patent Application Laid-Open No. 5-198182

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device capable of ensuring high-speed operation while improving soft error resistance.

  (1) In the present invention, a pair of inverters connected to each other via a pair of storage nodes, a source and a drain are connected between the storage node of the inverter and a bit line, and a gate is a word line A semiconductor memory device in which a memory cell including a pair of connected first conductivity type transfer transistors is formed on an SOI (Silicon On Insulator) substrate, wherein the inverter has a source connected to a high potential power supply line A second conductivity type load transistor, a first conductivity type drive transistor whose source is connected to the low-potential power line, a source and a drain connected between the storage node and the drain of the drive transistor, And a first conductivity type resistance addition transistor having a gate connected to the word line, wherein the first conductivity type resistance addition transistor has a gate voltage of the low potential. The present invention relates to a semiconductor memory device in which a source and a drain are electrically connected in the case of a predetermined power supply voltage supplied to a power supply line.

  According to the present invention, since the gate of the resistance-added transistor is connected to the word line, the resistance-added transistor has a low resistance when accessing the memory cell, and has a higher resistance when not accessing than when accessing. In addition, the first conductivity type resistance addition transistor is conductive between the source and the drain when the gate voltage is a predetermined power supply voltage supplied to the low potential power supply line (when the memory cell is not accessed). The loop of the inverter latch constituting the memory cell is not cut. Therefore, according to the present invention, the data holding operation can be reliably ensured despite the provision of the resistance-added transistor that has a high resistance when the memory cell is not accessed. According to the present invention, when the data holding operation is performed when the memory cell is not accessed, the resistance-added transistor has a high resistance. It is possible to prevent data reversal due to incidence such as. In addition, when the memory cell is accessed, the resistance between the source and drain of the resistance-added transistor is reduced by applying a cell selection signal from the word line as compared to when the memory cell is not accessed, so that the speed of writing / reading operation is reduced. There is no.

  (2) In the present invention, a pair of inverters connected to each other via a pair of storage nodes, a source and a drain are connected between the storage node and the bit line, and a gate is a first word line And a pair of first-conductivity-type transfer transistors connected to a semiconductor memory device having a memory cell formed on an SOI (Silicon On Insulator) substrate, the source of the inverter being a high-potential power line A second conductivity type load transistor connected to the source, a first conductivity type drive transistor whose source is connected to the low-potential power line, and a source and a drain connected between the drain of the load transistor and the storage node And a second conductivity type resistance addition transistor connected to a second word line different from the first word line, wherein the second conductivity type resistance addition transistor comprises: The present invention relates to a semiconductor memory device in which a source and a drain are conductive when a gate voltage is a predetermined power supply voltage supplied to the high potential power supply line.

  In the present invention, a signal obtained by logically inverting the cell selection signal of the first word line is supplied to the second word line. Further, the potential of the second word line may be fixed to the power supply voltage to be supplied to the high potential power supply line.

  According to the present invention, since the gate of the resistance-added transistor is connected to the word line, the resistance-added transistor has a low resistance when accessing the memory cell, and has a higher resistance when not accessing than when accessing. Further, the second conductivity type resistance-added transistor is electrically connected between the source and the drain when the gate voltage is a predetermined power supply voltage supplied to the high potential power supply line (when the memory cell is not accessed). The loop of the inverter latch constituting the cell is not cut. Therefore, according to the present invention, the data holding operation can be reliably ensured despite the provision of the resistance-added transistor that has a high resistance when the memory cell is not accessed. According to the present invention, when the data holding operation is performed when the memory cell is not accessed, the resistance-added transistor has a high resistance. It is possible to prevent data reversal due to incidence such as. Further, at the time of access, the resistance between the source and drain of the resistance addition transistor becomes lower than that at the time of non-access due to the application of the cell selection signal from the word line, so that the speed of the write / read operation does not decrease.

  In the present invention, a resistance addition transistor is provided on the load transistor side with respect to the storage node. For this reason, it is possible to take measures to prevent the inversion of stored data upon incidence of α rays or the like on the memory cell without affecting the ratio of the current amplification factor between the transfer transistor and the drive transistor that determines the drive balance of the element. it can.

  (3) In the present invention, a pair of inverters connected to each other via a pair of storage nodes, a source and a drain are connected between the storage node and the bit line, and a gate is a first word line And a pair of first-conductivity-type transfer transistors connected to a semiconductor memory device having a memory cell formed on an SOI (Silicon On Insulator) substrate, the source of the inverter being a high-potential power line A load transistor of the second conductivity type connected to the first transistor, a drive transistor of the first conductivity type whose source is connected to the low-potential power line, and a source and a drain connected between the storage node and the drain of the drive transistor A resistance addition transistor of a first conductivity type whose gate is connected to the first word line, and a source and a drain of the drain of the load transistor and the storage node A resistance addition transistor of a second conductivity type connected between the first word line and a second word line different from the first word line, wherein the resistance addition transistor of the first conductivity type is a gate When the voltage is a predetermined power supply voltage supplied to the low-potential power supply line, the source and the drain are conductive, and the second conductivity type resistance addition transistor has a gate voltage supplied to the high-potential power supply line. The present invention relates to a semiconductor memory device in which a source and a drain are electrically connected at a predetermined power supply voltage.

  By providing resistance addition transistors on the load transistor side in addition to the drive transistor side as in the present invention, soft error countermeasures for all the transistors constituting the memory cell are completed, and alpha rays etc. are secured while ensuring the operation speed. Inversion of stored data at the time of the incident can be more reliably prevented.

  (4) In the semiconductor memory device of the present invention, the resistance-added transistor may have a body potential in a floating state. In this way, the body potential changes to near the drain voltage during standby, so that the memory cell can be operated at high speed during access.

  (5) In the semiconductor memory device of the present invention, the load transistor and the driving transistor may have a body contact that connects a source and a body. In this way, the capacity can be added to the storage node by increasing the gate capacity of each transistor constituting the inverter. That is, the loop time constant for maintaining the potential of the storage node at the time of incidence of α rays or the like can be increased.

  (6) In the semiconductor memory device of the present invention, the resistance addition transistor may have an impurity region in which impurities having the same conductivity type as the source and drain are introduced in the body. In this way, it is possible to secure a current-carrying region for conducting between the source and the drain when the memory cell is not accessed in the resistance-added transistor. In this case, the impurity region can be provided in the channel forming region of the body or the bottom of the body (near the insulating layer of the SOI substrate).

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing an equivalent circuit of an SRAM memory cell (hereinafter simply referred to as a memory cell) which is a semiconductor memory device of the present embodiment.

  The memory cell of this embodiment is composed of eight MOS transistors formed using an SOI substrate. The p-type (second conductivity type) load transistor TP1, the n-type (first conductivity type) resistance addition transistor TD1, and the n-type drive transistor TN1 form a first CMOS inverter INV1. The p-type additional transistor TP2, the n-type resistance addition transistor TD2, and the n-type drive transistor TN2 form a second CMOS inverter INV2. The sources of the p-type load transistors TP1 and TP2 are connected to the high potential power supply line VDD (power supply voltage Vdd). The sources of the n-type drive transistors TN1 and TN2 are connected to the low potential power supply line VSS (power supply voltage Vss). The first and second CMOS inverters INV1 and INV2 are connected to input / output nodes via storage nodes N1 and N2 to form a flip-flop. This flip-flop has a gate connected to the word line WL, and is connected to the bit line BL and the inverted bit line / BL by a pair of n-type transfer transistors TN3 and TN4 which are turned on / off by a predetermined selection potential. The first and second CMOS inverters INV1 and INV2 are connected to each other via the storage nodes N1 and N2, so that the storage nodes N1 and N2 are connected by the loop holding operation of the inverter latch. Are in a complementary relationship.

  In the memory cell of the present embodiment, the first and second CMOS inverters INV1 and INV2 are provided with n-type resistance addition transistors TD1 and TD2, thereby preventing inversion of stored data at the time of incidence of α rays or the like. Yes. The n-type resistance addition transistors TD1 and TD2 are MOS transistors in which the source and the drain are conductive when the gate voltage is the voltage Vss. Specifically, it may be a MOS transistor in which a current of about several tens of nA to several μA flows between the source and drain when the gate voltage is the low-potential power supply voltage Vss. The n-type resistance addition transistors TD1 and TD2 have drains connected to the storage nodes N1 and N2, and sources connected to the n-type drive transistors TN1 and TN2. The n-type resistance-added transistors TD1 and TD2 have a gate connected to the word line WL, so that the resistance between the source and the drain is low when accessing the memory cell, and the operation speed is guaranteed. The resistance between the drain and the drain becomes high, and the loop time constant of the inverter latch can be increased as compared with the conventional memory cell structure. Since the n-type resistance addition transistors TD1 and TD2 are provided on the n-type drive transistors TN1 and TN2 side with respect to the storage nodes N1 and N2, the n-type drive transistors TN1 and TN2 that are dominant in the storage operation of the memory cell. It is possible to effectively delay the change in node potential when α rays or the like are incident on. In this case, the resistance value between the source and drain of the n-type resistance addition transistors TD1 and TD2 at the time of non-access can secure a loop time constant sufficient for soft error countermeasures, and the loop of the inverter latch can be secured. It can be set within a range (eg, several tens of kΩ to several tens of MΩ) that is reliably maintained and does not undesirably affect the data holding operation.

  Next, the n-type resistance addition transistors TD1 and TD2 will be described in more detail with reference to the cross-sectional view shown in FIG. In the n-type resistance addition transistors TD1 and TD2, a body 11 made of a p-type semiconductor layer and a source / drain 12 made of an n-type semiconductor layer provided on both sides of the body 11 are formed on an insulating film 10 constituting an SOI substrate. Is formed. A gate 14 made of polysilicon or the like is formed on the body 11 via a gate insulating film 13. Each transistor is isolated by STI 16. Further, the n-type resistance addition transistors TD1 and TD2 are provided with an impurity region 15 in which an n-type impurity is introduced into a channel formation region immediately below the gate insulating film 13 of the body 11. As shown in FIG. 2A, the impurity region 15 may be provided in a region where a channel is formed in the body 11, or as shown in FIG. 2B, the bottom of the body (of the SOI substrate). It may be provided in the vicinity of the insulating film 10). Thereby, in the memory cell of the present embodiment, it is possible to secure an energization region for conducting between the source and the drain in the n-type resistance addition transistors TD1 and TD2 at the time of non-access.

  Further, the resistance addition transistors TD1 and TD2 are formed on the SOI substrate, and as shown in FIGS. 2A and 2B, the floating body type MOS in which the potential of the body 11 is in a floating state. It becomes a transistor. In this way, if floating body type MOS transistors are employed as the resistance addition transistors TD1 and TD2, the potential of the body 11 changes to near the drain voltage during standby, so that the n-type drive transistors TN1 and TN2 side during access Since the current can be rapidly drawn into the memory cell, the memory cell can be operated at high speed.

  The n-type resistance addition transistors TD1 and TD2 may have a body contact that connects the source and the body. When such a body contact is provided, the potential of the body 11 of the n-type resistance addition transistors TD1 and TD2 can be stabilized regardless of the switching operation. For this reason, by providing the n-type resistance addition transistors TD1 and TD2, the influence on the ratio of the current amplification factors of the n-type drive transistors TN1 and TN2 and the n-type transfer transistors TN3 and TN4 that determine the drive balance of the elements is reduced. Can do.

  Further, in the memory cell of the present embodiment, in the first and second CMOS inverters INV1 and INV2, the p-type load transistors TP1 and TP2 and the n-type drive transistors TN1 and TN2 have a body and a source connected to each other. You can have contacts. In this way, it is possible to add capacity to the storage nodes N1 and N2 by increasing the gate capacity of each transistor. That is, it is possible to increase the loop time constant for maintaining the potentials of storage nodes N1 and N2 at the time of incidence of α rays or the like. In this case, it is desirable that the n-type transfer transistors TN3 and TN4 also have a body contact that connects the body to the low-potential power supply line VSS. When the current amplification factor ratio in relation to the drive transistors TN1 and TN2 does not matter, the bodies of the n-type transfer transistors TN3 and TN4 may be in a floating state.

  Next, the effect of the soft error countermeasure in the memory cell of this embodiment will be described with reference to FIG.

  The solid line in FIG. 3 shows the potential change of the storage node N1 (or N2) in the memory cell when the α ray is incident in a single shot. When the node potential is HIGH (voltage Vdd), when α rays or the like are incident on the n-type drive transistor TN1 (TN2) in a single shot, the voltage changes to LOW (voltage Vss) for a very short time. Thereafter, the generated charges disappear rapidly due to recombination or the like, but once the node potential is reversed, the data stored in the memory cell may be reversed. Such a phenomenon becomes more prominent as the power supply voltage is lowered.

  However, in the memory cell of the present embodiment, the n-type resistance addition transistors TD1 and TD2 have high resistance when the data holding operation is performed at the time of non-access. Therefore, as shown by the broken line in FIG. 3, the loop time constant of the inverter latch is increased by the source-drain resistance of the n-type resistance addition transistors TD1 and TD2, and the storage nodes N1 and N2 are The time for the node potential to change to the power supply voltage Vss side on the low potential side can be delayed. That is, it is possible to effectively prevent the stored data from being inverted.

  Further, according to the memory cell of the present embodiment, since the gates of the n-type resistance addition transistors TD1 and TD2 are connected to the word line WL, the resistance is low when accessing the memory cell, and the access is performed when not accessing. High resistance compared to sometimes. The n-type resistance-added transistors TD1 and TD2 are connected to each other between the source and the drain when the gate voltage is the low-potential power supply voltage Vss (when the memory cell is not accessed). Does not break the latch loop. Therefore, according to the memory cell of the present embodiment, the data holding operation can be surely ensured despite the provision of the n-type resistance addition transistors TD1 and TD2 that have high resistance when not accessed. Further, in the memory cell according to the present embodiment, the resistance between the source and drain of the n-type resistance addition transistors TD1 and TD2 is significantly lower than that in the non-access state due to the application of the cell selection signal from the word line WL during access. Therefore, the speed of the write / read operation does not decrease. Further, in the memory cell of the present embodiment, the n-type drive transistors TN1 and TN2 and the n-type resistance addition transistors TD1 and TD2 have a stack configuration, thereby suppressing an increase in the amount of wiring and ensuring flexibility in layout design. can do.

  In the memory cell of the present embodiment, the n-type resistance addition transistors TD1 and TD2 are provided on the n-type drive transistors TN1 and TN2 side with respect to the storage nodes N1 and N2, thereby increasing the loop time constant of the inverter latch. As shown in FIG. 4, p-type resistance addition transistors TD11 and TD12 whose gates are connected to the inverted word line / WL are provided on the p-type load transistors TP1 and TP2 side with respect to the storage nodes N1 and N2. May be adopted. In this case, it is possible to effectively delay the change in node potential when α rays or the like enter the p-type load transistors TP1 and TP2. In this case, the inverted word line / WL is supplied with a voltage signal having a potential logically inverted from the selection potential of the word line WL. Further, the potential of the inverted word line / WL may be fixed to the power supply voltage Vdd on the high potential side. The p-type resistance addition transistors TD11 and TD12 are required to be electrically connected between the source and the drain when the gate voltage is the power supply voltage Vdd on the high potential side. Other characteristics can be the same as those of the n-type resistance addition transistors TD1 and TD2 shown in FIG. Therefore, in this memory cell, the same soft error countermeasure effect as that in the memory cell shown in FIG. 1 can be obtained. Further, since the p-type resistance addition transistors TD11 and TD12 are provided on the p-type load transistor side with respect to the storage nodes N1 and N2, the ratio of the current amplification factor between the transfer transistor and the drive transistor that determines the drive balance of the elements is affected. Therefore, it is possible to take measures to prevent inversion of stored data when α rays or the like enter the memory cell.

  As a modification of the present embodiment, as shown in FIG. 5, p-type resistance addition transistors TD11 and TD12 are provided on the p-type load transistors TP1 and TP2 side with respect to the storage nodes N1 and N2, and the storage node N1 is provided. , N2 may be configured such that n-type resistance addition transistors TD1 and TD2 are provided on the n-type drive transistors TN1 and TN2 side. As described above, by providing the resistance addition transistors TD1, TD2, TD11, and TD12 on both the n-type drive transistors TN1 and TN2 side and the p-type load transistors TP1 and TP2 side with respect to the storage nodes N1 and N2, a p-type load is provided. Even if α rays or the like are incident on any of the transistors TP1 and TP2 and the n-type drive transistors TN1 and TN2, the inversion of stored data can be reliably prevented.

  Although the preferred embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the invention.

FIG. 3 is an equivalent circuit diagram showing the SRAM memory cell of the present embodiment. FIG. 3 is a cross-sectional view of a resistance addition transistor constituting the SRAM memory cell of the present embodiment. The characteristic view which shows the node potential in the SRAM memory cell at the time of alpha ray incidence. The equivalent circuit diagram which shows the modification of the SRAM memory cell of this Embodiment. The equivalent circuit diagram which shows the modification of the SRAM memory cell of this Embodiment.

Explanation of symbols

TP1, TP2 p-type load transistor, TN1, TN2 n-type drive transistor, TN3, TN4 n-type transfer transistor, TD1, TD2 n-type resistance addition transistor, INV1 first CMOS inverter, INV2 second CMOS inverter

Claims (8)

A pair of inverters connected to each other via a pair of storage nodes, a pair of first inverters whose sources and drains are connected between the storage nodes of the inverter and the bit lines, and whose gates are connected to the word lines A semiconductor memory device in which a memory cell including a transfer transistor of one conductivity type is formed on an SOI (Silicon On Insulator) substrate,
The inverter is
A second conductivity type load transistor whose source is connected to the high potential power supply line;
A first conductivity type driving transistor whose source is connected to the low-potential power line;
A first conductivity type resistance-added transistor having a source and a drain connected between the storage node and the drain of the driving transistor, and a gate connected to the word line;
Including
The first conductivity type resistance-added transistor is a semiconductor memory device in which a source and a drain are conductive when a gate voltage is a predetermined power supply voltage supplied to the low potential power supply line. A pair of inverters connected to each other via a pair of storage nodes, a pair of inverters having a source and a drain connected between the storage node and the bit line, and a gate connected to a first word line A semiconductor memory device in which a memory cell including a transfer transistor of a first conductivity type is formed on an SOI (Silicon On Insulator) substrate,
The inverter is
A second conductivity type load transistor whose source is connected to the high potential power supply line;
A first conductivity type driving transistor whose source is connected to the low-potential power line;
A resistance addition transistor of a second conductivity type having a source and a drain connected between the drain of the load transistor and the storage node, and a gate connected to a second word line different from the first word line;
Including
The second conductivity type resistance-added transistor is a semiconductor memory device in which a source and a drain are conductive when a gate voltage is a predetermined power supply voltage supplied to the high potential power supply line. A pair of inverters connected to each other via a pair of storage nodes, a pair of inverters having a source and a drain connected between the storage node and the bit line, and a gate connected to a first word line A semiconductor memory device in which a memory cell including a transfer transistor of a first conductivity type is formed on an SOI (Silicon On Insulator) substrate,
The inverter is
A second conductivity type load transistor whose source is connected to the high potential power supply line;
A first conductivity type driving transistor whose source is connected to the low-potential power line;
A resistance addition transistor of a first conductivity type having a source and a drain connected between the storage node and a drain of the driving transistor, and a gate connected to the first word line;
A resistance addition transistor of a second conductivity type having a source and a drain connected between the drain of the load transistor and the storage node, and a gate connected to a second word line different from the first word line;
Including
The resistance addition transistor of the first conductivity type is conductive between a source and a drain when a gate voltage is a predetermined power supply voltage supplied to the low potential power supply line,
The second conductivity type resistance-added transistor is a semiconductor memory device in which a source and a drain are conductive when a gate voltage is a predetermined power supply voltage supplied to the high potential power supply line. In any one of Claims 1-3,
The resistance addition transistor is a semiconductor memory device in which a body potential is in a floating state. In any one of Claims 1-4,
The load transistor and the drive transistor have a body contact that connects a source and a body. In any one of Claims 1-5,
The resistance-added transistor is a semiconductor memory device having an impurity region in which an impurity having the same conductivity type as the source and drain is introduced in the body. In claim 6,
The semiconductor memory device, wherein the impurity region is provided in a channel formation region of the body. In claim 6,
The semiconductor memory device, wherein the impurity region is provided at a bottom portion of the body.

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