JPH11144469A - Three device sram memory cell circuit and two device latching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low cost SRAM whose memory cell circuit can be composed of three transistors and whose latching circuit can be composed of two transistors. SOLUTION: N-type MOS-FET's 11 and 13 whose gates are connected to a substrate in order to utilize a backgate bias effect are connected to a positive electrode power supply and a P-type MOS-FET 12 with the same construction is connected to a negative electrode power supply and, further, all the respective gate electrodes and drain electrodes are connected to each other to compose a latching circuit 15 which is used as the latching circuit 15 of an SRAM. Further, the MOS FET 13 is used as a transmission gate 14 for word selection. An SOI substrate is used as the substrate of the SRAM memory cell circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device using a static random access memory (hereinafter abbreviated as SRAM), which has a high degree of integration and high element efficiency.
The present invention also relates to a circuit configuration of a memory cell suitable for high-speed operation or a configuration of a latch circuit having a small number of elements in a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A conventional SRAM memory cell circuit is shown in FIG.
Insulated gate field effect transistor (hereinafter referred to as MO
Latch circuit 315 composed of four elements and N-type (or P-type) MOSFETs from both ends thereof
In this configuration, a signal stored in the latch circuit and its inverted signal are output to two bit lines 318 and 319 via 313 and 314. Then, as shown in the circuit diagram showing the entire arrangement and configuration of FIG.
20 to determine the signal stored in the memory cell.

Further, a general latch circuit using a MOSFET has a circuit configuration of a latch circuit 315 shown in FIG.

[0004]

In the above-described conventional memory cell configuration, four MOS transistors are provided in one latch circuit.
Using FETs and two MOSFETs as transmission gates, a total of six MOSFETs
Is used. That all depends on the storage capacity. In the SRAM, generally and as a large capacity is required year by year, six MOSFETs are provided in one memory cell circuit.
Is very expensive to manufacture,
There is a problem that the cost is about four times that of a dynamic ram (DRAM) having the same capacity.

Further, the conventional latch circuit has a problem that the number of elements is large for its function, as described above, using four MOSFETs.

Accordingly, an object of the present invention is to provide a memory cell circuit with a small number of elements and to provide an SRAM with a low manufacturing cost in order to solve or alleviate such problems.

Another object of the present invention is to provide a latch circuit having a small number of elements.

[0008]

SUMMARY OF THE INVENTION A three-element SRAM according to the present invention.
The memory cell circuit includes an N-type MOSFET in which a first electrode is connected to a positive power supply and a gate electrode and a substrate are connected, and a P-type MOSFET in which a first electrode is connected to a negative power supply and a gate electrode and a substrate are connected. It is characterized by comprising a two-element latch circuit in which each second electrode and gate electrode are all connected to each other, and a transmission gate of MOSFET.

[0009]

According to the above construction of the present invention, P-type and N-type MOs constituting a latch circuit and a transmission gate are provided.
In the SFET, since the gate electrode and the substrate are connected to each other, the threshold voltage when the gate potential is turned on (ON) is reduced (easy to conduct) by the back gate bias effect, and when the gate potential is turned off (OFF). Are high (easy to cut off) due to the back gate effect. An N-type MOSFET is used for the positive power supply and a P-type MOSFET is used for the negative power supply. Both gate electrodes and the second electrode are all connected to each other.
ET turns on, the P-type MOSFET turns off, and a positive potential is supplied from a power supply and held. When the input signal is at a negative potential, the reverse is maintained. Then, the threshold voltage changes due to the back gate effect, making it easier to hold and preventing leakage current. Also, MOSFET
The transmission gate serves to transmit a signal when reading a signal from the latch circuit and when writing data to the latch circuit, and can function as a memory cell as a whole.

[0010]

The present invention will be described below in detail with reference to examples. FIG. 1 is a circuit diagram of a three-element SRAM memory cell showing a first embodiment of the present invention. FIG. 1 uses an SOI (silicon-on-insulator) wafer substrate having a buried oxide film, and the substrates between the MOSFETs are separated in principle. In FIG. 1, a circuit surrounded by a broken line 15 functions as a latch circuit, and a circuit surrounded by a broken line 14 functions as a transmission gate.
The circuit surrounded by 0 corresponds to the three-element SRAM memory cell circuit of the present invention. In the broken line 15, 11 is N
Type MOSFET, and the first electrode is a positive power supply +
_VDD , and the gate electrode and the substrate are connected. Further, 12 is a P-type MOSFET, the first electrode is connected to the -V _SS a power supply of the negative electrode, the gate electrode and the substrate are connected. Also, N-type MOSFE
Second electrode and gate electrode of T11, and P-type MOSFET
The second electrode and the gate electrode of T12 are all connected to each other to form an input / output terminal 16.

In the case of a MOSFET, a source electrode is usually connected to the power supply side and a drain electrode is connected to the output side, and the terms are usually written as such. N-type M for positive electrode + V _DD
OSFET, relationship between the source and drain are reversed so using P-type MOSFET to the negative pole of _{-V SS,} first electrode closer to the power source so misleading, denoted the output side and the second electrode.

The N-type MOSFET 11 is turned on (conducting) when the gate electrode has a positive potential, and the positive potential of + V _DD
Flows into the second electrode and is fed back to the gate electrode, and thus has a function of stably maintaining a positive potential. Since the substrate of the N-type MOSFET 11 is connected to the gate electrode, if the gate potential is positive, the threshold voltage of the normal N-type MOSFET whose source and substrate are negative is higher than the threshold voltage.
The threshold voltage is set so that the threshold voltage becomes low (in a direction in which conduction becomes easier) due to the reverse of the back gate bias effect, and in effect, the threshold voltage is set so as to be in a depletion state. Voltage drop, and the positive potential of the power supply + V
_DD is transmitted through the gate. When the gate electrode has a negative potential, the gate electrode is off (non-conductive). Then, at this time, a negative potential is transmitted to the substrate, and the threshold voltage is increased by the back gate effect. At the same time, there is no leakage current. In addition, P type M
OSFET12 is on (conductive) when the gate electrode of a negative potential, _{-V SS} is a negative potential is crowded flows to the second electrode,
In addition, since it is fed back to the gate electrode, it has a function of stably maintaining a negative potential.

Since the substrate of the P-type MOSFET 12 is also connected to the gate electrode, the threshold voltage changes between ON and OFF due to the back gate bias effect, as described above, so that conduction and cutoff are more clearly defined. Acts in the direction of Therefore, the circuit 15 composed of the N-type MOSFET 11 and the P-type MOSFET 12 is a latch circuit that stably holds either the positive potential (+ V _DD ) or the negative potential (−V _SS ) and has no leakage current. I understand. Reference numeral 13 denotes an N-type MOSFET. Two terminals serving as a source electrode or a drain electrode serve as a first terminal and a second terminal of the transmission gate 14, and the gate electrode is connected to a word line 17.
A second terminal of the transmission gate 14 represented by a broken line 14 is composed of an N-type MOSFET 13
8, and the first terminal is connected to the input / output terminal 16 of the latch circuit 15. The N-type MOSFET 13 turns on when the word line 17 has a positive potential, and turns off when the word line 17 has a negative potential. Since the SOI system is used, subthreshold leakage can be easily controlled and the threshold voltage can be set lower. Therefore, not only a signal of a negative potential but also a signal of a positive potential is transmitted within a range of potential change which does not hinder.

With the above configuration, when the word line 17 becomes positive potential, data can be written from the bit line 18 to the latch circuit 15, and data held in the latch circuit 15 can be taken out to the bit line 18. . When the word line 17 has a negative potential, the latch circuit 15
8 and retains data.

FIG. 2 shows a configuration in which it is easier to understand how the three-element SRAM memory cell circuit (hereinafter abbreviated as memory cell) described in FIG. 1 is used in the entire SRAM device. In FIG. 2, all the blocks indicated by a broken line 10 are the memory cells described in FIG. 1 line from the top in FIG. 2 (actually the L-th row) enter the L-th word line W _L is the group of memory cells are arranged laterally to, N-type MOSFET of the transmission gate in each memory cell Is controlled. The second line from the top (actually L
(L--1)
The 1) th word line WL _-1 is input, and similarly controls each memory cell. The first column from the left M-th bit line B _M in the memory cell group are arranged vertically in (actually M-th column) is connected to the second terminal of each transmission gate. The (M-1) th bit line _BM-1 is connected to the second terminal of each transmission gate in the memory cell group vertically arranged in the second column (actually the M-1 column) from the left. ing.

A write circuit 21 is controlled by a composite signal WC of a write signal and a column signal.
Is a read circuit controlled by a combined signal RC of the read signal and the column signal. The bit line _BM is connected to the output terminal of the write circuit 21 and the input terminal of the read circuit 22. A column read / write circuit 20 including a write circuit 21 and a read circuit 22 is provided for each bit line. To read the data at the address (L, M), the L-th word line is activated, and the read circuit 22 connected to the M-th bit line is operated. Similarly, when rewriting the data at the address (L, M), the L-th word line is activated, and the write circuit 21 connected to the M-th bit line is operated. From the above, it can be seen that data at an arbitrary address can be read and written. FIGS. 1 and 2 of the present invention are shown in FIG.
Comparing FIG. 4 with FIG. 4, it can be seen that three transistors are fewer per memory cell and one bit line is less per column of memory cells. This is a reduction in components that are very large for an integrated circuit device as an SRAM, and contributes to cost reduction, miniaturization, or low power consumption.

Although an example of an N-type MOSFET is shown in the transmission gate of the circuit of FIG. 1, a P-type MOSFET can be used if the sign of the word line signal is taken into consideration.

In addition, N serving as a transmission
The power supply voltage of the MOSFET 13 is very low,
When the threshold voltage is not negligible and the power supply voltage is lower than the contact potential between P diffusion and N diffusion (approximately 0.5 V or less), the gate electrode is connected to the substrate and the back gate bias effect is used to turn on the transistor. There is also a method of lowering the threshold voltage of.

Although the above description has been made on the assumption that the present invention is applied to an SRAM, the latch circuit 15 used in FIG. 1 is naturally useful as a latch circuit in circuits other than the SRAM. 2 is a configuration of a two-element latch circuit of the present invention.

Further, the above is an SOI having a buried oxide film.
Although the method has been described as an example, the SOS (SS) in which a silicon single crystal thin film is grown on an insulating substrate which is a kind of SOI.
Similarly, it is also possible to use a so-called ordinary bulk method if the well potential is not less than SOI and the substrate potential of each MOSFET is separated as necessary by using three or more layers.

References regarding SOI devices include “Applied Physics Vol. 64, No. 11, (1995)
P1104-P1110 Research and Development Trend of SOI Devices Yasuaki Inoue ".

References for the back gate bias effect include “Design and Application of MOS / LSI P48-P
49 Author William N. Carr Co., Ltd. Electro Digest Issue 1976 ".

[0023]

As described above, as described above, the three-element SR of the present invention is used.
According to the AM memory cell circuit, three M
Since it is composed of OSFETs, there is an effect that an efficient SRAM memory cell circuit having a smaller number of elements can be provided as compared with a conventional memory cell circuit requiring six elements.

Further, since there is one bit line per memory cell column, there is an effect that an SRAM having a smaller chip area can be provided as compared with the conventional two lines.

Accordingly, there is an effect that an inexpensive SRAM can be provided.

Further, since the number of elements is small and a differential circuit is not used at the time of data reading, there is an effect that a memory cell and an SRAM with low power consumption can be provided.

Further, the two-element latch circuit of the present invention has an SRA
M can be used in addition to M, and there is an effect that the number of elements can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a three-element SRAM memory cell circuit showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a relationship between a three-element SRAM memory cell circuit according to the first embodiment of the present invention and peripheral circuits in the SRAM circuit;

FIG. 3 is a circuit diagram of an SRAM memory cell circuit of a conventional circuit example.

FIG. 4 is a circuit diagram showing a relationship with peripheral circuits in an SRAM circuit of a conventional circuit example.

[Explanation of symbols]

10 3 element SRAM memory cell circuit 11, 13, 313, 314 ... N-type MOSFET 12 ... P-type MOSFET 14 ... transmission gate 15, 315 ... latch circuit 16 ... input / output sharing terminal _{17, W L, W} L _over 1, W _{L over} 2 _{18, B M, B} M _over 1, B _{M over} 2, B _M-3 20 ... column read-write circuit 21 ... write circuit 22 ... Read circuit 310 ... Memory cell circuit 317 ... Word line 318,319 ... Bit line 320 ... Differential sense amplifier circuit WC ... Combined signal of write signal and column signal RC ... and reading signal and a column signal synthesis signal + _{V DD} ··· power supply potential -V _SS ··· negative electrode of the power supply potential of the positive electrode of

Claims (5)

[Claims] A) a semiconductor integrated circuit device equipped with a static random access memory; b) a first N-type insulated gate field effect transistor and a second P-type insulated gate field effect transistor;
The first electrode of the first N-type insulated gate field effect transistor is connected to a positive power supply, the gate electrode and the substrate are connected to each other, and the first electrode of the second P-type insulated gate field effect transistor is A negative electrode power supply, a gate electrode and a substrate connected to each other, and a gate electrode and a second electrode of the first N-type insulated gate field effect transistor; and a second P-type insulated gate field effect transistor A) a latch circuit comprising a gate electrode and a second electrode all connected to each other to form an input terminal and an output terminal; and c) a transmission gate comprising a third insulated gate field effect transistor; An input terminal and an output terminal of the circuit are connected to a second terminal of the transmission gate, and a first terminal of the transmission gate. Is connected to the bit line as a memory, the third three-element SRAM memory cell circuit gate electrode, characterized in that connected to the word line as the memory of an insulated gate field effect transistor. 2. A three-element SRAM memory cell circuit, wherein a gate electrode of the third insulated gate field effect transistor according to claim 1 is connected to a substrate. 3. The three-element SRAM memory cell circuit according to claim 1, wherein the semiconductor integrated circuit device uses a silicon-on-insulator (SOI) wafer substrate. 4. A semiconductor integrated circuit device using an insulated gate field effect transistor, comprising: b) a first N-type insulated gate field effect transistor and a second P-type insulated gate field effect transistor;
The first electrode of the first N-type insulated gate field effect transistor is connected to a positive power supply, the gate electrode and the substrate are connected to each other, and the first electrode of the second P-type insulated gate field effect transistor is A negative electrode power supply, a gate electrode and a substrate connected to each other, and a gate electrode and a second electrode of the first N-type insulated gate field effect transistor; and a second P-type insulated gate field effect transistor Wherein the gate electrode and the second electrode are all connected to each other to serve as an input terminal and an output terminal. 5. The two-element latch circuit according to claim 4, wherein the semiconductor integrated circuit device uses a silicon-on-insulator (SOI) wafer substrate.