KR20010061094A - A method for fabricating a gate oxide of a semiconductor device - Google Patents
A method for fabricating a gate oxide of a semiconductor device Download PDFInfo
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- KR20010061094A KR20010061094A KR1019990063578A KR19990063578A KR20010061094A KR 20010061094 A KR20010061094 A KR 20010061094A KR 1019990063578 A KR1019990063578 A KR 1019990063578A KR 19990063578 A KR19990063578 A KR 19990063578A KR 20010061094 A KR20010061094 A KR 20010061094A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 Al2O3를 이용한 게이트산화막 제조시에 Al2O3증착후 박막내에 존재하는 탄소를 효과적으로 제거할 수 있도록한 반도체소자의 게이트산화막 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, the gate oxide film of a semiconductor element to effectively remove the carbon present in the Al 2 O after three films deposited at a gate oxide film produced by the Al 2 O 3 It relates to a manufacturing method.
종래 반도체소자의 디자인룰(design rule)이 점점 작아지고 소자가 고집적화됨에 따라 게이트산화막의 두께도 점점 얇아지고 있다.As the design rule of the semiconductor device becomes smaller and the device becomes more integrated, the thickness of the gate oxide film becomes thinner.
그러나, 기존에 사용되어진 열산화막으로는 FN(Fowler Nordheim)터넬링(tunnelling)과 함께 게이트산화막의 두께가 얇아질수록 직접터넬링(direct tunnelling)에 의한 누설전류가 증가하므로 소자특성에 영향을 미치게 되므로 열산화막(ε=3.9)보다 유전상수가 큰 물질(Al2O3=7.5)을 사용하므로써 물리적인 두께는 증가시키고 전기적 두께를 일정하게 유지시키는 방법이 연구중에 있다.However, as thermal oxide films used in the past, as the thickness of the gate oxide film becomes thinner with FN (Fowler Nordheim) tunneling, the leakage current by direct tunneling increases, thus affecting device characteristics. Therefore, a method of increasing the physical thickness and keeping the electrical thickness constant by using a material having a higher dielectric constant (Al 2 O 3 = 7.5) than the thermal oxide film (ε = 3.9) is under study.
그러나, 대부분의 고유전체 물질의 증착에 금속유기소스(metal organic source)가 사용되므로 증착후 박막내에 탄소가 포함되고 탄소의 효과적인 제거가 이루어져야 누설전류를 감소시킬 수 있다.However, since a metal organic source is used for the deposition of most high dielectric materials, carbon must be included in the thin film after the deposition and the effective removal of carbon can reduce the leakage current.
위와 같은 탄소를 효과적으로 제거하기 위하여 산소분위기에서 퍼니스 아닐링을 진행하거나 RTP (Rapid Thermal Process)처리를 통하여 CO2의 형태로 탄소를 제거하는 방법이 있다.In order to effectively remove the carbon as described above, there is a method of removing carbon in the form of CO 2 through furnace annealing in an oxygen atmosphere or RTP (Rapid Thermal Process) treatment.
그러나, 이 방법은 보통 높은 온도(700 ℃이상)에서 진행하므로 Si기판의 계면과 산소와의 반응으로 계면에 SiOx가 형성되어 산화막의 두께(Tox)가 증가하게 되며, 계면특성도 나빠지게 된다.However, this method usually proceeds at a high temperature (above 700 ℃), so SiO x is formed on the interface of the Si substrate and the oxygen, which increases the thickness of the oxide film (T ox ) and worsens the interfacial properties. do.
이에 본발명은 상기 종래의 문제점을 해소하기 위하여 안출한 것으로서, 게이트산화막의 누설전류특성을 개선시키고자한 반도체소자의 게이트산화막 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a method for manufacturing a gate oxide film of a semiconductor device to improve leakage current characteristics of the gate oxide film.
또한, 본 발명의 다른 목적은, 기판과 게이트산화막의 반응을 억제하여 Tox의 증가를 방지할 수 있는 반도체소자의 게이트산화막 제조방법을 제공함에 있다.In addition, another object of the present invention is to provide a method for manufacturing a gate oxide film of a semiconductor device capable of inhibiting the reaction between the substrate and the gate oxide film to prevent an increase in T ox .
도 1 내지 도 4 는 본 발명에 따른 반도체소자의 게이트산화막 제조방법을 설명하기 위한 제조공정도이다.1 to 4 are manufacturing process diagrams for explaining a method of manufacturing a gate oxide film of a semiconductor device according to the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
1 : 실리콘기판 2 : 소자분리막1: silicon substrate 2: device isolation film
3 : Al2O3박막3: Al 2 O 3 thin film
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 게이트산화막 제조방법은, 실리콘기판상에 존재하는 자연산화막 또는 열산화막을 제거하는 공정과;A method of manufacturing a gate oxide film of a semiconductor device according to the present invention for achieving the above object comprises the steps of removing a natural oxide film or a thermal oxide film present on a silicon substrate;
Al(CH3)3소오스와 H2O를 기화시켜 Al2O3박막을 형성하는 공정과;Vaporizing the Al (CH 3 ) 3 source and H 2 O to form an Al 2 O 3 thin film;
상기 Al2O3박막이 형성된 기판을 O2가스를 이용하여 급속열적 아닐링처리하는 공정과;Rapidly thermally annealing the substrate on which the Al 2 O 3 thin film is formed using O 2 gas;
상기 급속열적 아닐링처리공정후 O3가스를 플라즈마기체로 여기시켜 상기 Al2O3박막을 플라즈마처리하는 공정을 포함하여 구성되는 것을 특징으로한다.이하, 본 발명에 따른 반도체소자의 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.And plasma treatment of the Al 2 O 3 thin film by exciting the O 3 gas into the plasma gas after the rapid thermal annealing treatment. Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described. When described with reference to the accompanying drawings as follows.
도 1 내지 도 4 는 반도체소자의 게이트산화막 제조방법을 설명하기 위한 제조공정도이다.1 to 4 are manufacturing process diagrams for explaining a method for manufacturing a gate oxide film of a semiconductor device.
본 발명에 따른 반도체소자의 게이트산화막 제조방법은, 도 1 에 도시된 바와같이, 소자분리막(2)이 트렌치(trench)형태로 형성된 실리콘기판(1)상에 자연산화막 또는 열산화막을 HF 또는 BOE (Buffer Oxide Etchant)로 제거한다.In the method of manufacturing a gate oxide film of a semiconductor device according to the present invention, as shown in FIG. 1, a HF or BOE is formed on a silicon substrate 1 on which a device isolation film 2 is formed in a trench. Remove with (Buffer Oxide Etchant).
그다음, 도 2 에 도시된 바와같이, 실리콘기판(1)상에 Al2O3박막(3)을 60 ∼100 Å 두께로 증착한다.Next, as shown in FIG. 2, an Al 2 O 3 thin film 3 is deposited on the silicon substrate 1 to a thickness of 60 to 100 GPa.
이때, Al2O3의 유전상수가 7 - 9 이므로 전기적인 두께는 35 ∼ 55 Å 이 된다.At this time, since the dielectric constant of Al 2 O 3 is 7-9, the electrical thickness is 35 to 55 kW.
또한, 상기 Al2O3박막 증착조건으로는 TMA (Tri-methyl-aluminum)In addition, the Al 2 O 3 thin film deposition conditions TMA (Tri-methyl-aluminum)
(TMA=Al(CH3)3) 소스와 H2O를 기화시켜 온도는 300 ∼ 350 ℃ 정도, 압력은 400 ∼ 1000 m Torr 의 분위기하에서 Al2O3박막(3)을 증착한다.The (TMA = Al (CH 3 ) 3 ) source and H 2 O are vaporized to deposit an Al 2 O 3 thin film 3 under an atmosphere of temperature of about 300 to 350 ° C. and pressure of about 400 to 1000 m Torr.
이어서, 후속 열공정에 의해 Al2O3박막(3)은 아래와 같은 순으로 처리된다.Subsequently, the Al 2 O 3 thin film 3 is processed in the following order by the subsequent thermal process.
도 3 에 도시된 바와같이, 먼저, 500 ∼ 600 ℃에서 산소(O2)가스의 량을 1 ∼ 10 slm으로 하고, 30 ∼ 60 초간 급속열적산화공정(RTO; Rapid Thermal Oxidation)을 실시하여 Al2O3박막내에 존재하는 탄소를 제거한다.As shown in FIG. 3, first, the amount of oxygen (O 2 ) gas is 1 to 10 slm at 500 to 600 ° C., and rapid thermal oxidation (RTO; Rapid Thermal Oxidation) is performed for 30 to 60 seconds. Remove the carbon present in the 2 O 3 thin film.
통상의 RTP 공정과 같이 온도를 750 ∼ 900 ℃정도에서 진행하지 않는 이유는 O2가스에 의해 실리콘기판(1)과 Al2O3박막(3)사이에 실리콘산화막(SiOx) 성장하는 것을 막기 위한 것이다.The reason why the temperature does not proceed at about 750 to 900 ° C. as in the normal RTP process is to prevent the growth of the silicon oxide film (SiO x ) between the silicon substrate 1 and the Al 2 O 3 thin film 3 by O 2 gas. It is for.
그다음, 도 4 에 도시된 바와같이, O3가스에 플라즈마를 여기시켜 상기 Al2O3박막(3)을 처리한다.Next, as shown in FIG. 4, the Al 2 O 3 thin film 3 is treated by exciting plasma with O 3 gas.
이때, 상기 플라즈마 처리방법에 대해 설명하면 다음과 같다.In this case, the plasma processing method will be described below.
먼저, 챔버(미도시)내의 압력을 수십 ∼ 수백 Torr로 유지시킨 다음 기판히터의 온도를 300 ∼ 400 ℃ 로 유지시킨다.First, the pressure in the chamber (not shown) is maintained at several tens to several hundred Torr, and then the temperature of the substrate heater is maintained at 300 to 400 ° C.
그다음, RF 전력을 50 ∼ 400 W 로 인가하여 기판히터(미도시)를 그라운드(ground)로하고 샤워헤드(미도시)를 전극으로한다.Subsequently, RF power is applied at 50 to 400 W so that the substrate heater (not shown) is grounded and the showerhead (not shown) is the electrode.
이어서, O3처리시간은 1 ∼ 20 분으로 하고, O3농도는 10,000 ∼ 200,000 로 유지한다.Next, the O 3 treatment time is set to 1 to 20 minutes, and the O 3 concentration is maintained at 10,000 to 200,000.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 게이트산화막 제조방법에 있어서는 다음과 같은 효과가 있다.As described above, the method of manufacturing the gate oxide film of the semiconductor device according to the present invention has the following effects.
본 발명에 있어서는 Al2O3박막을 게이트산화막으로 사용할때 Al2O3박막증착후에 산소가스를 이용하여 500 ∼ 600 ℃온도에서 급속열적아닐링(RTA)처리를 하여 1차로 Al2O3박막내에 존재하는 탄소를 제거하고, 다시 300 ∼ 400 ℃의 온도에서 반응성이 좋은 오존(O3) 가스에 플라즈마를 여기시켜 Al2O3박막을 효과적으로 처리하므로써 박막내에 존재하는 탄소가 제거된다.In the present invention, when Al 2 O 3 thin film is used as a gate oxide film, Al 2 O 3 thin film is subjected to rapid thermal annealing (RTA) treatment at 500 to 600 ° C. using oxygen gas after deposition of Al 2 O 3 thin film. The carbon present in the thin film is removed by effectively removing the carbon present in the thin film and treating the Al 2 O 3 thin film by exciting the plasma with a highly reactive ozone (O 3 ) gas at a temperature of 300 to 400 ° C.
또한, O3플라즈마 처리는 낮은 온도에서 진행이 가능하므로 열적 부담(thermal budget)를 줄일 수 있고, 산화막의 두께(Tox)의 증가도 막을 수 있다.In addition, since the O 3 plasma treatment can proceed at a low temperature, the thermal budget can be reduced, and an increase in the thickness (Tox) of the oxide film can be prevented.
Claims (9)
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| KR1019990063578A KR100324822B1 (en) | 1999-12-28 | 1999-12-28 | A method for fabricating a gate oxide of a semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180216228A1 (en) * | 2016-01-26 | 2018-08-02 | Arm Ltd. | Fabrication of correlated electron material devices |
| US11450804B2 (en) | 2016-01-26 | 2022-09-20 | Cerfe Labs, Inc. | Fabricating correlated electron material (CEM) devices |
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| JPS5833841A (en) * | 1981-08-24 | 1983-02-28 | Hitachi Ltd | Semiconductor device |
| JPS5935425A (en) * | 1982-08-23 | 1984-02-27 | Toshiba Corp | Manufacture of semiconductor device |
| JPS62122133A (en) * | 1985-11-21 | 1987-06-03 | Nec Corp | Forming method for thin-film through solution coating |
| JPH0252430A (en) * | 1988-08-16 | 1990-02-22 | Fujitsu Ltd | Formation of multilayer insulating film |
| JPH0418728A (en) * | 1990-05-12 | 1992-01-22 | Oki Electric Ind Co Ltd | Insulating film formation process |
| JPH04354879A (en) * | 1991-05-30 | 1992-12-09 | Sharp Corp | Formation of metal oxide film |
| JPH0786269A (en) * | 1993-09-10 | 1995-03-31 | Fujitsu Ltd | Alumina film formation and manufacture of thin film transistor using same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180216228A1 (en) * | 2016-01-26 | 2018-08-02 | Arm Ltd. | Fabrication of correlated electron material devices |
| US11450804B2 (en) | 2016-01-26 | 2022-09-20 | Cerfe Labs, Inc. | Fabricating correlated electron material (CEM) devices |
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