KR20010060831A - Fringe field switching mode lcd - Google Patents

Abstract

PURPOSE: A fringe field switching liquid crystal display(LCD) is to decrease impedance and RC time delay and to decrease a residual direct current, thereby removing a residual image. CONSTITUTION: A lower substrate(21) faces an upper substrate(35) spaced apart by a predetermined distance. A liquid crystal layer(39) is interposed between the lower substrate and the upper substrate. A counter electrode(22) made of a transparent material is formed on the lower substrate. A pixel electrode(30) is formed on the lower substrate in an interdigital structure. The pixel electrode is made of a transparent material and is overlapped with the counter electrode to form a fringe field together with the counter electrode. An insulating layer(23,25) is interposed between the counter electrode and the pixel electrode. A lower alignment film(31) is interposed between the liquid crystal layer and the resultant lower substrate on which the counter electrode and the pixel electrode are formed. An upper alignment film(37) is interposed between the upper substrate and the liquid crystal layer.

Description

Fringe field drive liquid crystal display device {FRINGE FIELD SWITCHING MODE LCD}

The present invention relates to a liquid crystal display, and more particularly, to a fringe field switching liquid crystal display capable of reducing residual direct current (DC).

In general, a liquid crystal display device operated by a fringe field has been filed in Korean Patent Application No. 98-9243 to improve the low aperture ratio and transmittance of a general IPS mode liquid crystal display device.

In the fringe field driving liquid crystal display, the counter electrode and the pixel electrode are formed of a transparent conductor, and the gap between the counter electrode and the pixel electrode is formed to be narrower than the gap between the upper and lower substrates, and the fringe field is formed on the counter electrode and the pixel electrode. By forming the filed), all of the liquid crystal molecules present on the electrodes are operated.

1 is a cross-sectional view of a typical fringe field driving liquid crystal display device.

Referring to FIG. 1, a counter electrode 2 is formed in a plate shape in each unit pixel region of the transparent lower substrate 1 having a unit pixel region defined therein. After the first insulating film 3 made of a silicon oxide film is formed on the lower substrate 1 on which the counter electrode 2 is formed, the gate bus line 4 is formed in a predetermined region of the lower substrate. On the gate bus line 4 and the first insulating film 3, the second and third insulating films 5 and 6 and the channel layer 7 serving as the gate insulating film are sequentially stacked. In this case, silicon nitride oxide (SiON) having excellent insulating properties is used as the first and second insulating films 3 and 5, and the third insulating film 6 has a silicon nitride film having excellent adhesion property with the channel layer 7 ( SiN) is used. In addition, the total thickness of the first and second insulating films 3 and 5 is formed to about 1500 to 2000 kPa. In addition, the channel layer 7 and the third insulating film 5 are formed in an active form existing only on a predetermined portion of the gate bus line 4. Source and drain electrodes 9a and 9b are formed on both sides of the channel layer 7 around the gate bus line 4 to form a thin film transistor. Here, a doped amorphous silicon layer 8 as an ohmic layer is disposed between the source and drain electrodes 9a and 9b and the channel layer 7, respectively. The pixel electrode 10 is disposed on the second insulating layer 5 to overlap the counter electrode 2. In this case, the pixel electrode 10 is formed of an ITO layer similarly to the counter electrode, and is formed in a comb-tooth shape to be in contact with the drain electrode of the thin film transistor. The lower alignment layer 12 is formed on the resultant surface of the lower substrate 1 on which the thin film transistor and the pixel electrode 10 are formed. At this time, the lower alignment layer 10 is formed to a thickness of about 400 ~ 600Å.

On the other hand, a color filter (not shown) is formed on the inner surface of the upper substrate 15 to be bonded to the lower substrate 1, and the alignment film 17 is also formed on the color filter surface.

The liquid crystal layer 19 is interposed in the space portion between the lower substrate 1 and the upper substrate 15.

In the fringe field driving liquid crystal display device configured as described above, since the gap and width between the pixel electrode 10 and the counter electrode 2 are sufficiently narrow, a fringe field is formed to form a gap between the electrodes 10, 2 and the electrodes 10,. 2) All liquid crystal molecules on the top are operated.

However, in the conventional fringe field driving liquid crystal display, the electrode is not disposed on the upper substrate 15 side, unlike the conventional twisted nematic (TN) mode, and thus, a plurality of films are concentrated on the lower substrate 1 side. . As a result, resistance and capacitance become very large in the path in which the electric field is generated. As such, when the resistance and capacitance are increased, the impedance (total of the resistance and capacitance) of the portion where the RC time constant and the electric field are generated becomes large, so that the residual DC voltage is not easily discharged and an afterimage occurs on the screen.

In more detail, when a voltage is applied between the counter electrode 2 and the pixel electrode 10, a first electric field E1 is formed in the liquid crystal layer 19, and the first and second insulating films 3, The second electric field E2 is formed in 5).

At this time, in each layer in which the electric fields E1 and E2 are formed, the parasitic capacitance C and the parasitic resistance R exist, and the parasitic capacitance and the parasitic resistance are equivalently connected in parallel to each other.

Here, the path in which the first electric field E1 is formed is formed in an elliptic shape, so that the lower alignment layer 12, the liquid crystal layer 19, the lower alignment layer 12, the second insulating layer 5, and the 1 is formed over the insulating film 3. Accordingly, the total parasitic impedance of the first electric field (E1) band is the impedances R12 and C12 of the lower alignment layer 12 connected in series, the impedances R19 and C19 of the liquid crystal layer 19 and the lower alignment layer 12, respectively. The impedances R12 and C12, the impedances R5 and C5 of the second insulating film 5, and the impedances R3 and C3 of the first insulating film 3 are expressed in total. Meanwhile, a path in which the second electric field E2 is formed is formed between the second and first insulating layers 5 and 3. The total impedance of the fringe field driving liquid crystal display device includes the impedances Y2 of the second electric field to the impedance Y1 of the first electric field E1, that is, the impedances R5 and C5 of the second insulating film 5 connected in series. 1 Since the impedances R3 and C3 of the insulating film 3 become integer multiples (two times the number of combs) in parallel, the value is very large. As such, as the impedance is increased, the residual DC component, which is a voltage component, is correspondingly increased, resulting in severe afterimages on the screen.

Accordingly, it is an object of the present invention to provide a fringe field driving liquid crystal display device capable of reducing residual DC to eliminate afterimages on a screen.

1 is a cross-sectional view of a conventional fringe field driving liquid crystal display device.

2 is an equivalent circuit diagram for parasitic resistance and parasitic capacitance in a conventional fringe field driving liquid crystal display device.

3 is a cross-sectional view of a fringe field driving liquid crystal display device according to the present invention;

4 is an equivalent circuit diagram of parasitic resistance and parasitic capacitance in the liquid crystal display according to the present invention.

(Explanation of symbols for the main parts of the drawing)

21-Board 22-Counter Electrode

23-first insulating film 25-second insulating film

30-pixel electrode 31-lower alignment layer

39-liquid crystal layer

In order to achieve the above object of the present invention, according to an embodiment of the present invention, the upper and lower substrates facing each other at a predetermined distance; A liquid crystal layer interposed between the upper and lower substrates; A counter electrode formed on the lower substrate and formed of a transparent material; A pixel electrode made of a transparent material, overlapping the counter electrode on the lower substrate, the pixel electrode having a plurality of combs to form a fringe field with the counter electrode; An insulating film insulating between the counter electrode and the pixel electrode; A lower alignment layer interposed between the surface of the lower substrate resultant on which the counter electrode and the pixel electrode are formed and the liquid crystal layer; And an upper alignment layer interposed between the upper substrate surface and the liquid crystal layer, wherein the insulating layer is formed to a thickness of about 2500 to 15000 GPa, and the lower alignment layer is formed to a thickness of 600 to 1500 GPa.

Preferably, the insulating film is formed to a thickness of 4000 to 7000 Å, the lower alignment layer is characterized in that formed to a thickness of 700 to 900 Å.

In addition, the insulating film may be formed of at least one or more layers, and may be formed of two layers of insulating films, for example, a laminated film of a silicon oxide film and a silicon oxynitride film, or a two-layer silicon nitride film.

In addition, the counter electrode and the pixel electrode are formed of an ITO material, and the counter electrode is formed in the form of a plate or in the form of a comb.

According to the present invention, the thicknesses of the alignment film and the insulating film formed in the path in which the electric field is formed are increased as compared with the prior art, thereby reducing the parasitic capacitance in each film. Accordingly, the impedance of the field generation band and the RC time constant are reduced, so that the residual DC component proportional to the impedance is also reduced as compared with the prior art.

Therefore, as the residual DC component is reduced, a problem such as an afterimage on the screen does not occur.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view of a fringe field driving liquid crystal display according to the present invention, and FIG. 4 is an equivalent circuit diagram of parasitic resistance and parasitic capacitance in the liquid crystal display according to the present invention.

Referring to FIG. 3, an ITO layer is formed on the lower substrate 21 made of a transparent insulator by a sputtering method with a predetermined thickness by using an Ar gas, an O ₂ gas, and an ITO target. Then, the ITO layer is patterned into a predetermined shape, so that the counter electrode 22 in the form of a square plate or a comb teeth is formed. In this embodiment, the counter electrode 22 is formed in the shape of a square plate.

Then, using an SiH ₄ gas, O ₂ gas, and N ₂ gas, a silicon oxide film for insulating the counter electrode 22 on the insulating substrate 21 and the gate bus line to be formed later by APCVD. Alternatively, the first insulating film 23 made of silicon oxynitride film is formed.

Next, a MoW metal film, an Al—Nd alloy film, or a laminated film of Mo / Al is deposited over the first insulating film 23, and then patterned to a predetermined portion, thereby forming a gate bus line 24. At the same time as the process of forming the gate bus line 24, a common electrode line (not shown) for transmitting a common signal to the counter electrode 22 is formed.

On the first insulating film 23 having the gate bus line 24 formed thereon, the second insulating film 25 made of silicon nitride oxide, the third insulating film 26 made of silicon nitride film, and the amorphous silicon film for channel (a-Si: 27) ) And the doped semiconductor layer (n ⁺ a-si: 28) are sequentially deposited by plasma enhacned chemical vapor deposition (PECVD). Then, the doped semiconductor layer 18, the amorphous silicon layer 27, and the third insulating film 26 are patterned to a predetermined portion so as to surround the predetermined portion of the gate bus line 24, thereby forming an active region.

On the resulting product of the lower substrate 21, a metal film for data bus lines, for example, an opaque metal film such as Mo / Al / Mo lamination or MoW, is formed to a predetermined thickness. Then, the metal film is partially patterned so as to be disposed on both sides of the gate bus line 24 to form source, drain electrodes 29a and 29b and a data bus line (not shown).

Then, the ITO layer for the pixel electrode is deposited on the resultant by sputtering, and patterned in the shape of a comb to form the pixel electrode 30. In this case, the pixel electrode 30 overlaps the counter electrode 22 with the first and second insulating layers 23 and 25 interposed therebetween. In this case, the pixel electrode, the comb teeth 30 of the pixel electrode in the drawing, may form a fringe field and a portion of the counter electrode 22 opened through the space between the comb teeth 30 and the pixel electrode comb 30 of the pixel electrode. It is formed at a predetermined interval and a predetermined width so that it can be. The lower alignment layer 31 is coated on the resultant surface of the lower substrate 21.

On the other hand, the upper substrate 35 to be bonded to the lower substrate 21 includes a color filter (not shown) on the inner side, and the upper alignment layer 37 is also coated on the color filter surface.

The liquid crystal layer 39 is interposed in the space portion between the lower substrate 21 and the upper substrate 35.

When a predetermined voltage is applied to the counter electrode 22 and the pixel electrode 30 of the liquid crystal display device having such a configuration, as shown in FIG. 3, the first electric field may be formed in the space between the comb teeth of the pixel electrode 30. E1 is formed, and a second electric field E2 is formed under the comb teeth of the pixel electrode 30.

In each layer where the first and second electric fields E1 and E2 are formed, parasitic capacitance C and parasitic resistance R exist, and the impedance (sum of parasitic capacitance and parasitic resistance) generated in each layer is parasitic. Capacitance and parasitic resistance are shown in equivalent form in parallel with each other.

Here, since the first electric field E1 is formed in an ellipse shape as shown in the drawing, the lower alignment layer 31, the liquid crystal layer 39, the lower alignment layer 31, the second insulating layer 25, and the first insulating layer 23. Formed over. Accordingly, the overall parasitic impedance in the band in which the first electric field E1 is formed is the impedances R31 and C31 of the lower alignment layer 31, the impedances R39 and C39 of the liquid crystal layer 39 and the lower alignment layer 31. The impedances R31 and C31, the impedances R25 and C25 of the second insulating film 25, and the impedances R23 and C23 of the first insulating film 23 are represented by series connection, that is, the sum thereof. Meanwhile, the second electric field E2 is formed between the second and first insulating films 25 and 23, and the overall parasitic impedance in the band where the second electric field E2 is formed is the impedance of the second insulating film 25. This is represented by the sum of R25 and C25 and impedances R23 and C23 of the first insulating film 23. In addition, the total impedance of the first and second electric fields E1 and E2 of the fringe field driving liquid crystal display device is such that the impedance Y2 of the second electric field E is parallel to the impedance Y1 of the first electric field E1. This is an integer multiple of the concatenated value.

At this time, in the present embodiment, the insulation layers of the portion where the electric field is formed, for example, the first and the first, may be reduced so as to reduce the impedances Y1 and Y2 generated in the paths of the electric fields, thereby reducing the residual DC voltage component. 2 The thicknesses of the insulating films 23 and 25 and the thickness of the lower alignment film 31 are relatively increased.

In detail, the impedance Y is a function of the capacitance C and the resistance R, and when the capacitance C and the resistance R are decreased, the impedance Y is reduced. At this time, the capacitance (C) is inversely proportional to the film thickness, as is known, and is proportional to the dielectric constant of the film, and thus the present embodiment increases the thickness of the insulating films formed in the portion where the electric field is generated. That is, the total thickness of the first and second insulating films 23 and 25 is increased to about 2500 to 15000 GPa, more preferably 4000 to 7000 GPa, than the conventional thickness, within the range that does not change the cell gap and the operating characteristics of the liquid crystal display. In addition, the thickness of the lower alignment layer 31 is also increased to 600 to 1500 kPa, preferably 700 to 900 kPa, which is thicker than the conventional one. Then, as the thicknesses of the first and second insulating films and the lower alignment film 31 are increased than before, the capacitance is relatively reduced, and the total impedance value of the field generating portion is reduced.

As described in detail above, according to the present invention, the thicknesses of the alignment film and the insulating film formed in the path in which the electric field is formed are increased as compared with the prior art, thereby reducing the parasitic capacitance in each film. Accordingly, the impedance of the field generation band and the RC time constant are reduced, so that the residual DC component proportional to the impedance is also reduced as compared with the prior art.

Therefore, as the residual DC component is reduced, a problem such as an afterimage on the screen does not occur.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (9)

Upper and lower substrates facing each other at a predetermined distance; A liquid crystal layer interposed between the upper and lower substrates; A counter electrode formed on the lower substrate and formed of a transparent material; A pixel electrode made of a transparent material, overlapping the counter electrode on the lower substrate, the pixel electrode having a plurality of combs to form a fringe field with the counter electrode; An insulating film insulating between the counter electrode and the pixel electrode; A lower alignment layer interposed between the surface of the lower substrate resultant on which the counter electrode and the pixel electrode are formed and the liquid crystal layer; And An upper alignment layer interposed between the upper substrate surface and the liquid crystal layer; The insulating film is formed to a thickness of about 2500 to 15000Å, The lower alignment layer is fringe field driving liquid crystal display, characterized in that formed to a thickness of 600 to 1500Å. The fringe field drive liquid crystal display device according to claim 1, wherein the insulating film is formed to a thickness of 4000 to 7000 kPa. The fringe field driving liquid crystal display of claim 1, wherein the lower alignment layer is formed to have a thickness of about 700 to about 900 μs. The fringe field driving liquid crystal display device of claim 1, wherein the insulating layer is formed of at least one layer. 5. The fringe field driving liquid crystal display device according to claim 4, wherein the insulating film is formed by stacking two insulating films. 6. The fringe field driving liquid crystal display device according to claim 5, wherein the insulating film is a laminated film of a silicon oxide film and a silicon nitride oxide film. 6. The fringe field driving liquid crystal display device according to claim 5, wherein the insulating film is two layers of silicon oxynitride film. The fringe field driving liquid crystal display of claim 1, wherein the counter electrode and the pixel electrode are formed of an indium tin oxide (ITO) material. The fringe field driving liquid crystal display device of claim 1, wherein the counter electrode is formed in a plate shape or a comb tooth shape.