KR20010058966A - A method for forming a field oxide of semiconductor device - Google Patents
A method for forming a field oxide of semiconductor device Download PDFInfo
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- KR20010058966A KR20010058966A KR1019990066342A KR19990066342A KR20010058966A KR 20010058966 A KR20010058966 A KR 20010058966A KR 1019990066342 A KR1019990066342 A KR 1019990066342A KR 19990066342 A KR19990066342 A KR 19990066342A KR 20010058966 A KR20010058966 A KR 20010058966A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
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Abstract
Description
본 발명은 반도체소자의 소자분리막 형성방법에 관한 것으로, 특히 HDP 산화막을 이용할 경우 유발되는 셀 접합 누설전류 ( cell junction leakage ) 의 증가 현상을 억제하기 위하여 HDP 증착공정후 어닐 공정을 실시할 때 온도와 가스를 변화시켜 셀 접합 누설전류 특성을 개선하는 것과, HDP 증착 후의 어닐 공정 스킵시 발생되는 턱짐 ( moat ) 증가를 개선하기 위하여 라이너 옥사이드 디포지션 ( liner oxide deposition ) 후에 어닐을 실시하여 턱짐을 개선하고 HDP 산화막 어닐 공정 스킵에 따른 HDP 산화막의 습식 용액에 의한 식각비 증가시 소자분리막 높이의 공정 제어능력이 저하되는 것을 방지하기 위하여 나이트라이드 두께를 조절하므로써 소자분리막 높이를 균일하게 하여 셀 문턱 전압 변화를 억제하는 기술에 관한 것이다.The present invention relates to a method of forming a device isolation film of a semiconductor device, and in particular, in order to suppress an increase in cell junction leakage caused by using an HDP oxide film, an annealing process after an HDP deposition process is performed. Annealing is performed after liner oxide deposition to improve the cell junction leakage current characteristics by changing the gas and to increase the moat generated during the skip of the annealing process after HDP deposition. In order to prevent the process control ability of the device isolation layer from deteriorating when the etching rate of the HDP oxide layer is increased by the wet solution of the HDP oxide layer by skipping the HDP oxide annealing process, the height of the device isolation layer is uniformed to adjust the cell threshold voltage. It is about a technique to suppress.
고집적화라는 관점에서 소자의 집적도를 높이기 위해서는 각각의 소자 디맨젼 ( dimension ) 을 축소하는 것과, 소자간에 존재하는 분리영역 ( isolation region ) 의 폭과 면적을 축소하는 것이 필요하며, 이 축소정도가 셀의 크기를 좌우한다는 점에서 소자분리기술이 메모리 셀 사이즈 ( memory cell size ) 를 결정하는 기술이라고 할 수 있다.In order to increase the integration of devices from the viewpoint of high integration, it is necessary to reduce each device dimension and to reduce the width and area of isolation regions existing between devices. Device isolation technology determines the memory cell size in terms of size.
소자분리절연막을 제조하는 종래기술로는 절연물 분리방식의 로코스 ( LOCOS : LOCal Oxidation of Silicon, 이하에서 LOCOS 라 함 ) 방법, 실리콘기판상부에 산화막, 다결정실리콘층, 질화막순으로 적층한 구조의 피.비.엘. ( Poly - Buffed LOCOS, 이하에서 PBL 이라 함 ) 방법, 기판에 홈을 형성한 후에 절연물질로 매립하는 트렌치 ( trench ) 방법 등이 있다.Conventional techniques for manufacturing device isolation insulating films include LOCOS (LOCOS: LOCOS) method, an oxide film, a polysilicon layer, and a nitride film on a silicon substrate. B.L. (Poly-Buffed LOCOS, hereinafter referred to as PBL) method, a trench method of embedding an insulating material after forming a groove in the substrate, and the like.
그러나, 상기 LOCOS 방법으로 소자분리산화막을 미세화할 때 공정상 또는 전기적인 문제가 발생한다. 그중의 하나는, 소자분리절연막만으로는 전기적으로 소자를 완전히 분리할 수 없다는 것이다.However, a process or electrical problem occurs when the device isolation oxide film is miniaturized by the LOCOS method. One of them is that the device isolation insulating film alone cannot completely separate the device.
그리고, 상기 PBL 을 사용하는 경우, 필드산화시에 산소의 측면확산에 의하여 버즈빅이 발생한다. 즉, 활성영역이 작아져 활성영역을 효과적으로 활용하지 못하며, 필드산화막의 두께가 두껍기 때문에 단차가 형성되어 후속공정에 어려움을 준다. 그리고, 기판상부의 다결정실리콘층으로 인하여 필드산화시 기판내부로 형성되는 소자분리절연막이 타기법에 비하여 상대적으로 작기 때문에 타기법에 비해 신뢰성을 약화시킬 수 있다.In the case of using the above-mentioned PBL, buzz big is generated by side diffusion of oxygen during field oxidation. In other words, the active area is small, so that the active area is not effectively utilized, and because the thickness of the field oxide film is thick, a step is formed, which causes difficulty in subsequent processes. Further, due to the polysilicon layer on the substrate, the device isolation insulating film formed inside the substrate during field oxidation is relatively smaller than that of the hitting method, thereby reducing the reliability of the hitting method.
이상에서 설명한 LOCOS 방법과 PBL 방법은 반도체기판 상부로 볼록한 소자분리절연막을 형성하여 단차를 갖게 됨으로써 후속공정을 어렵게 하는 단점이 있다.The LOCOS method and the PBL method described above have a disadvantage in that a subsequent step is made difficult by forming a convex element isolation insulating film on the semiconductor substrate and having a step.
이러한 단점을 해결하기 위하여, 반도체기판을 식각하여 트렌치를 형성하고 상기 트렌치를 매립한 다음, CMP 방법을 이용하여 상부면을 평탄화시키고 후속공정을 평탄화시킴으로써 후속공정을 용이하게 실시할 수 있도록 하였다.In order to solve this disadvantage, the semiconductor substrate is etched to form a trench, and the trench is buried, and then the CMP method is used to planarize the top surface and to planarize the subsequent process so that the subsequent process can be easily performed.
도시되지않았으나, 종래기술에 따른 반도체소자의 소자분리막 형성방법을 설명하면 다음과 같다.Although not shown, a method of forming a device isolation film of a semiconductor device according to the related art will be described below.
먼저, 반도체기판 상부에 패드산화막을 형성하고, 상기 패드산화막 상부에 질화막을 형성한다.First, a pad oxide film is formed over the semiconductor substrate, and a nitride film is formed over the pad oxide film.
그리고, 소자분리마스크를 이용한 식각공정으로 상기 질화막과 패드산화막 및 일정두께의 반도체기판을 식각하여 상기 반도체기판에 트렌치를 형성한다.In addition, a trench is formed in the semiconductor substrate by etching the nitride layer, the pad oxide layer, and the semiconductor substrate having a predetermined thickness by an etching process using an element isolation mask.
그리고, 상기 트렌치를 매립하는 고밀도 플라즈마 화학기상증착 ( high density plasma chemical vapor deposition, 이하에서 HDP 라 함 ) 산화막(도시안됨)을 전체표면 상부에 형성하고 화학기계연마 ( chemical mechenical polishing, 이하에서 CMP 라 함 ) 하여 평탄화시킨다.Then, a high density plasma chemical vapor deposition (hereinafter referred to as HDP) oxide film (not shown) filling the trench is formed on the entire surface, and chemical mechanical polishing (CMP) is used. To flatten.
이때, 상기 HDP 산화막은 1050 ℃ 온도에서 30 분 동안 형성한 것이다.At this time, the HDP oxide film is formed for 30 minutes at 1050 ℃ temperature.
도 2 는 상기한 종래기술에 따라 형성된 소자분리막의 템 ( TEM ) 사진을 도시한 것으로서, 턱짐이 크게 형성된 것을 도시한다.FIG. 2 is a TEM photograph of a device isolation film formed according to the related art, and shows a large jaw.
상기한 바와같이 종래기술에 따른 반도체소자의 소자분리막 형성방법은, HDP 산화막 적용시 셀 접합 누설전류 특성이 취약하게 되어 소자의 리프레쉬 ( refresh ) 특성을 저하시켜 반도체소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.As described above, the device isolation film forming method of the semiconductor device according to the prior art has a problem in that the cell junction leakage current property becomes weak when the HDP oxide film is applied, thereby lowering the refresh characteristics of the device, thereby degrading the characteristics and reliability of the semiconductor device. There is this.
본 발명의 상기한 종래기술의 문제점을 해결하기위하여, HDP 산화막 증착공정후 낮은 온도에서 질소가스만을 이용하여 어닐링 공정을 실시하여 반도체소자의 특성 및 신뢰성을 향상시키는 반도체소자의 소자분리막 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art of the present invention, by performing an annealing process using only nitrogen gas at a low temperature after the HDP oxide film deposition process to provide a device isolation film forming method of the semiconductor device to improve the characteristics and reliability of the semiconductor device Its purpose is to.
도 1 은 HDP 산화막 덴시피케이션 ( densification ) 조건에 따른 누설전류 특성 변화를 도시한 그래프.1 is a graph illustrating changes in leakage current characteristics according to HDP oxide densification conditions.
도 2 는 종래기술에 따라 형성된 소자분리막을 도시한 템 ( TEM ) 사진.Figure 2 is a TEM photograph showing a device isolation film formed according to the prior art.
도 3 은 본 발명의 실시예에 따라 형성된 소자분리막을 도시한 템 ( TEM ) 사진.3 is a TEM photograph showing a device isolation film formed according to an embodiment of the present invention.
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 소자분리막 형성방법은,In order to achieve the above object, a device isolation film forming method of a semiconductor device according to the present invention,
반도체기판 상부에 패드산화막과 패드질화막을 적층하는 공정과,Laminating a pad oxide film and a pad nitride film on the semiconductor substrate;
상기 패드질화막, 패드산화막 및 일정두께의 반도체기판을 식각하여 트렌치를 형성하는 공정과,Forming a trench by etching the pad nitride film, the pad oxide film, and the semiconductor substrate having a predetermined thickness;
상기 트렌치 표면에 월 산화막을 형성하는 공정과,Forming a month oxide film on the trench surface;
상기 트렌치를 포함한 전체표면상부에 리니어 산화막을 일정두께 형성하는 공정과,Forming a linear oxide film at a predetermined thickness over the entire surface including the trench;
상기 리니어 산화막을 어닐링하는 공정과,Annealing the linear oxide film;
상기 트렌치를 매립하는 HDP 산화막을 전체표면상부에 형성하고 이를 덴시피케이션시킨 후 어닐링하는 공정과,Forming an HDP oxide film filling the trench on the entire surface, densifying it, and then annealing the same;
상기 HDP 산화막을 CMP 하여 평탄화시킴으로써 소자분리막을 형성하는 공정을 포함하는 것을 특징으로한다.And planarizing the HDP oxide film by CMP to form a device isolation film.
한편, 이상의 목적을 달성하기 위한 본 발명의 원리는 다음과 같다.On the other hand, the principle of the present invention for achieving the above object is as follows.
본 발명은 HDP 산화막 적용시 누설 전류 특성이 저하되는 것을 방지하기 위하여 HDP 산화막 증착 후의 어닐 온도를 낮추고, 어닐시 N2가스만을 이용함으로써 산화막과 반도체기판의 응력 발생에 기이한 전기적 특성 저하 현상을 억제하는 것이다.The present invention is to reduce the annealing temperature after the deposition of the HDP oxide film in order to prevent the leakage current characteristic is degraded when applying the HDP oxide film, and to suppress the electrical property deterioration phenomenon caused by stress generation of the oxide film and the semiconductor substrate by using only N 2 gas at the time of annealing It is.
그리고 소자분리막 프로파일 측면에서는 어닐 공정 스킵시 턱짐 ( moat ) 의 크기가 커져서 셀 문턱 전압의 변화를 초래하고 험프 ( hump ) 현상이 발생되는 것을 방지하기 위해 라이너 산화막 증착공정후 어닐 공정을 실시하여 라이너 산화막의 습식 식각선택비를 감소시켜 턱짐의 크기를 현저히 감소시킬 수 있도록 하는 것이다.In addition, in the aspect of the isolation layer profile, when the annealing process is skipped, the size of the moat increases so that the cell threshold voltage is changed and the hump phenomenon is prevented. By reducing the wet etch selectivity of the jaw to significantly reduce the size of the jaw.
그리고, HDP 어닐 온도를 낮추거나 어닐 공정을 스킵하였을 경우 발생되는 소자분리막 높이의 공정 제어 능력 저하 현상을 억제시키기 위하여 패드질화막 두께를 높이고 CMP 공정시 오버 폴리싱을 실시하여 남아있는 패드질화막의 두께로 소자분리막 높이를 조절하도록 하는 것이다.In addition, in order to suppress the process control ability degradation of the height of the device isolation film generated when the HDP annealing temperature is lowered or the annealing process is skipped, the thickness of the pad nitride film is increased by over-polishing during the CMP process, and the device is reduced to the thickness of the remaining pad nitride film. To control the height of the separator.
이하, 본 발명을 상세시 설명하기로 한다.Hereinafter, the present invention will be described in detail.
도시되지않았으나, 본 발명에 따른 반도체소자의 소자분리막 형성방법을 설명하면 다음과 같다.Although not shown, a method of forming a device isolation film of a semiconductor device according to the present invention will be described below.
먼저, 반도체기판 상부에 패드산화막과 패드질화막을 각각 60 ∼ 80 Å,1200 ∼ 1500 Å 두께로 형성한다.First, a pad oxide film and a pad nitride film are formed on the semiconductor substrate to have a thickness of 60 to 80 Å and 1200 to 1500 Å, respectively.
이때, 상기 패드질화막은 두께를 증가시켜 후속 CMP 공정시 패드질화막을 오버 폴리싱함으로써, 패드질화막 상부에 패드질화막 상부에 산화 성분이 남아 패드질화막 언스트립 ( unstrip ) 이 발생하는 것을 방지하고 폭스의 높이를 정확히 제어 할 수 있도록 한다.In this case, the pad nitride film is increased in thickness to overpolize the pad nitride film in a subsequent CMP process, so that an oxidizing component remains on the pad nitride film on the pad nitride film to prevent pad nitride film unstrip and increase the height of the fox. It allows for precise control.
그 다음, 소자분리마스크를 이용한 마스킹 작업을 통해 활성영역과 비활성영역인 소자분리영역으로 분리하는 감광막패턴을 형성하고 이를 이용하여 패드질화막과 일정두께의 일정두께의 반도체기판을 건식식각하여 트렌치를 형성한다.Next, through the masking operation using the device isolation mask to form a photoresist pattern that separates the active region and the inactive region of the device isolation region, using this to form a trench by dry etching the pad nitride film and a predetermined thickness of a semiconductor substrate. do.
그리고, 상기 트렌치 식각공정에 의한 반도체기판의 손상을 보상하기 위하여 고온에서 월 산화막 ( wall oxide ) 을 성장시킨다.And, in order to compensate for the damage of the semiconductor substrate by the trench etching process, a wall oxide film is grown at a high temperature.
그 다음, 후속공정으로 실시되는 크리닝 작업에 의해 상기 패드 산화막의 로스 ( loss ) 로 인해 유발되는 보이드 ( void ) 발생을 억제하기 위해 LPCVD 방법으로 라이너 산화막을 100 ∼ 150Å 증착한다.Then, the liner oxide film is deposited by LPCVD method to suppress the generation of voids caused by the loss of the pad oxide film by a cleaning operation performed in a subsequent step.
상기 라이너 산화막은 후속 어닐 공정 조건에 따라 습식 식각선택비가 변화하므로 턱짐의 크기를 증가시키는 원인으로 작용한다.The liner oxide layer acts as a cause of increasing the size of the jaw because the wet etching selectivity is changed according to the subsequent annealing process conditions.
그러므로 상기 라이너 산화막 증착공정후 950 ∼ 1150 ℃ 온도에서 질소가스나 아르곤 가스와 산소가스를 이용하여 20 ∼ 50 분 동안 어닐 공정을 실시하여 라이너 산화막의 식각 선택비를 낮춤으로써 턱짐의 크기를 현저히 개선시킬 수 있다.Therefore, after the liner oxide film deposition process, the annealing process is performed for 20 to 50 minutes using nitrogen gas, argon gas, and oxygen gas at a temperature of 950 to 1150 ° C. to lower the etching selectivity of the liner oxide film, thereby significantly improving the size of the jaw. Can be.
참고로, 상기 HDP 산화막 증착공정후 덴스피케이션 ( densification ) 공정을 진행하지 않았을 경우에 있어서, 라이너 증착공정후 후 어닐 공정을 적용하지않을 때가 어닐공정을 적용할때보다 턱짐 ( moat ) 이 크게 형성된다.For reference, in the case where the densification process is not performed after the HDP oxide film deposition process, when the annealing process is not applied after the liner deposition process, the moat is formed larger than when the annealing process is applied. do.
그 다음, 상기 트렌치를 매립하는 HDP 산화막을 6000Å 정도 증착한 후 HDP 덴시피케이션 공정을 실시한다.Next, after depositing about 6000 HD of the HDP oxide film filling the trench, the HDP densification process is performed.
그리고, 상기 HDP 산화막을 어닐링한다.The HDP oxide film is then annealed.
이때, 상기 HDP 산화막의 어닐링 공정은 700 ∼ 900 ℃ 온도에서 진행하고 가스는 N2만을 이용하여 20 ∼ 50 분 동안 어닐 공정으로 실시하므로써 누설 전류를 개선하다.At this time, the annealing process of the HDP oxide film is carried out at a temperature of 700 ~ 900 ℃ and the gas is performed by an annealing process for 20 to 50 minutes using only N 2 to improve the leakage current.
그 다음, CMP 공정을 실시하되, 상기 패드질화막을 오버 폴리싱하여 질화막 언스트립을 방지하한다.Thereafter, a CMP process is performed, but over-polishing the pad nitride film to prevent nitride film unstriping.
그리고, 습식 식각용액에 담구는 습식식각공정 시간을 조절하여 소자분리막의 높이를 정확히 조절한다.The height of the device isolation layer is precisely controlled by adjusting the time of the wet etching process soaked in the wet etching solution.
그 다음, 상기 패드질화막을 뜨거운 인산을 이용하여 제거함으로써 소자분리막을 형성한다.Next, the device isolation film is formed by removing the pad nitride film using hot phosphoric acid.
본 발명의 실시예에서 상기 라이너 산화막의 어닐링 공정과 상기 HDP 산화막의 어닐링 공정중 한가지를 생략할 수도 있다.In an embodiment of the present invention, one of the annealing process of the liner oxide layer and the annealing process of the HDP oxide layer may be omitted.
도 3 은 상기한 본 발명의 실시예에 따라 형성된 소자분리막의 템 ( TEM ) 사진을도시한 것으로서, 턱짐이 상기 도 2 의 종래기술에서 보다 작게 형성된 것을 도시한다.FIG. 3 illustrates a TEM picture of the device isolation film formed according to the embodiment of the present invention, wherein the jaw is smaller than that of the related art of FIG. 2.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 소자분리막 형성방법은, 트렌치형 소자분리막 형성공정이 유발될 수 있는 누설전류를 감소시키고 턱짐 ( moat )을 감소시킬 수 있어 반도체소자의 후속공정을 용이하게 하며 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬수 있는 효과를 제공한다.As described above, the device isolation film forming method of the semiconductor device according to the present invention can reduce the leakage current and the moat that can cause the trench type device isolation film forming process, thereby facilitating subsequent processing of the semiconductor device. And it provides an effect that can improve the characteristics and reliability of the semiconductor device accordingly.
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| KR100731097B1 (en) * | 2005-12-28 | 2007-06-22 | 동부일렉트로닉스 주식회사 | Isolation film of semiconductor device method for fabricating the same |
| KR100842901B1 (en) * | 2002-06-28 | 2008-07-02 | 주식회사 하이닉스반도체 | Method for forming isolation film in semiconductor device |
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| US5275965A (en) * | 1992-11-25 | 1994-01-04 | Micron Semiconductor, Inc. | Trench isolation using gated sidewalls |
| US5811315A (en) * | 1997-03-13 | 1998-09-22 | National Semiconductor Corporation | Method of forming and planarizing deep isolation trenches in a silicon-on-insulator (SOI) structure |
| KR19990010757A (en) * | 1997-07-18 | 1999-02-18 | 윤종용 | Device Separation Method of Semiconductor Device |
| KR100442852B1 (en) * | 1997-09-12 | 2004-09-18 | 삼성전자주식회사 | Method for forming trench isolation region to embody isolation region proper for high integrated semiconductor device |
| KR100257759B1 (en) * | 1997-12-27 | 2000-06-01 | 김영환 | Element isolation film manufacturing method using trench |
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| KR100731097B1 (en) * | 2005-12-28 | 2007-06-22 | 동부일렉트로닉스 주식회사 | Isolation film of semiconductor device method for fabricating the same |
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