KR20010058870A - Data processing method of a processor - Google Patents

Abstract

PURPOSE: A method for processing data of a processor is provided to increase the reliability and the efficiency of an application program including a repeat block command by removing a restriction of the number of command which the repeat block command has. CONSTITUTION: A repeat count value is set up. A repeat block command fetched from a memory is decoded. A repeat termination and a repeat start address are set up. The first command of the repeat block is fetched. The first command is decoded and executed. The second command is fetched. A memory address for fetching the second command is corresponded to the repeat termination address. It is checked whether the first command is a command for non-linearly changing an execution order of a program. In case that the first command is the command for non-linearly changing the execution order, a memory address of the second command is stored.

Description

DATA PROCESSING METHOD OF A PROCESSOR

The present invention relates to a processor, and more particularly, to a data processing method of a processor for efficiently executing a program including a repeat block (hereinafter, abbreviated as RPTB) instruction.

1 shows a conventional processor for executing a program including an RPTB instruction. As shown in FIG. 1, the processor core 100 includes the operational logic and some control logic of the processor, and fetches (F) -decodes instructions stored in the program memory 101 in a pipeline form, that is, as shown in FIG. 2. (D)-Read / Execute (R / D). The memory 101 is a general term for the memory used in the processor, and stores instructions to be decoded by the processor core 100. The program counter (PC) generation logic 106 generates a program counter (PC) value under the control of the processor core 100, and the generated PC value is stored in the program counter 108 through the multiplexer 107. .

The RPTB control logic 102, the repeat count (RC) register 103, the repeat end (RE) register 104, and the repeat start (RS) register 105 form the RPTB logic. The RPTB control logic 102 is operated by the enable signal output from the processor core 100, and the repetition count (RC) register 103, the repetition end (RE) register 104, and the repetition start when the RPTB instruction is executed. (RS) register 105 and multiplexer (MUX) 107 are controlled. The repeat count (RC) register 103 stores a repeat count value (repeat count) BRC, and the repeat end (RE) register 104 and repeat start (RS) register 105 are the repeat end address (REA). ) And repeat start address (RSA) are stored respectively.

The RPTB control logic 102 compares the memory address stored in the program counter 108 and the repetition end address REA. If the two addresses are the same, the RPTB control logic 102 controls the multiplexer 107 to store the repetition start address (stored in the RS register 105). RSA) is input to the program counter 108, and a decrease signal is output to the RC register 103 to decrease the repetition count value BRC.

The operation of the conventional processor configured as described above will be described with reference to the following execution procedure of <Program 1>.

In <Program 1>, the repeat count value (BRC) is set to "2". The repeat end address (REA) of the RPTB instruction is set to "n + 3". The RPTB instruction includes three instructions (CALL), (ADD) and (SUB) are included.

<Program 1>

STM BRC # 2 n-1

RPTB n + 3 n

CALL n + 10 n + 1

ADD n + 2

SUB n + 3

RET n + 10

NOP n + 11

NOP

3 is an example showing how each instruction of <Program 1> operates on a pipeline.

In the first cycle 60, the processor core 100 fetches from the memory 101 an instruction STM corresponding to the memory address n-1 output from the program counter 108 [F (n-1). )].

In the second cycle 61, the processor core 100 decodes the fetched instruction STM [D (n-1)] to control the control signal for storing the repetition count value BRC "2". Output to logic 102. The processor core 100 controls the PC generation logic 106 to increase the previous PC value n-1 to the next PC value n, and the memory address of the program counter 108 from the memory 101. Fetch the instruction (RPTB) corresponding to (n) [F (n)].

In the third cycle 62, the RPTB control logic 102 sets two repeat count values BRC in the RC register 103 [R / E (n-1)]. The processor core 100 decodes the fetched RPTB instruction, outputs the enable signal and the repetition end address REA to the RPTB control logic 102 [D (n)], and increases to the next PC value (n + 1). To control the PC generation logic 106. The processor core 100 also fetches an instruction CALL corresponding to the memory address n + 1 of the program counter 108 from the memory 101 [F (n + 1)].

In the fourth cycle 63, the RPTB control logic 102 is operated by the enable signal to set the repetition end address REA of " n + 3 " to the RE register 104, and the program counter 108 The memory address (n + 1) outputted from S is set as the repeat start address (RSA) of the RS register 105 [R / E (n)]. That is, the RPTB control logic 102 sets the address n + 3 of the decoded RPTB instruction to the repetition end address REA, and sets the previous memory address n + 2 of the program counter 108 to the repeat start address ( RSA).

The processor core 100 decodes the instruction CALL and then controls the PC generation logic 106 to increase the PC value to "n + 2" [D (n + 1)] and output it from the program counter 108. The memory 101 is controlled to store the stored memory address n + 2, and the PC generation logic 106 is generated to generate the decoded n + 10 address. At this time, the RPTB control logic 102 does not perform any control operation because the memory address n + 2 of the program counter 108 and the repetition end address REA are different. The processor core 100 fetches an instruction ADD corresponding to the memory address n + 2 [F (n + 2)].

In the fifth cycle 64, the memory 101 stores a memory address n + 2 [R / E (n + 1)]. The processor core 100 does not decode the fetched instruction ADD because the previous instruction is CALL [D (n + 2)] and increases the PC generated logic 106 to increase the PC value to "n + 11". To control. The processor core 100 fetches an instruction FET corresponding to the previous memory address n + 2 [F (n + 10)].

In the sixth cycle 65, the processor core 100 does not execute the instruction ADD because the instruction ADD has not been decoded [R / E (n + 2)]. Processor core 100 decodes the fetched instruction RET [D (n + 10)] and controls PC generation logic 106 to increase the PC value to " n + 11 ". However, since the command RET means return, the processor core 100 reads the memory address n + 2 previously stored in the memory 101 and then reads the read memory address n + 2. Control the PC generation logic 106 to be set back to the PC value. The processor core 100 fetches an instruction NOP corresponding to the previous memory address n + 11 [F (n + 11)].

In the seventh cycle 66, the processor core 100 does nothing because it is currently returning (R / E (n + 10)). Processor core 100 decodes the fetched instruction NOP and controls PC generation logic 106 to increase D [(n + 11)] and increase the previous PC value (n + 2) to “n + 3”. In addition, the processor core 100 fetches an instruction ADD corresponding to the previous memory address n + 2 from the memory 101 [F (n + 2)].

In the eighth cycle 67, the processor core 100 performs no execution because the instruction NOP is "No operation" [R / E (n + 11)]. The processor core 100 then decodes the fetched instruction ADD and then controls the PC generation logic 106 to generate the next PC value n + 4 [D (n + 2)]. Since the PC value (n + 2) coincides with the repetition end address (REA) (n + 2) of the RE register 104, the RPTB control logic 102 controls the RS register 105 and the multiplexer 107. The repetition start address RSA is input to the program counter 108. The RPTB control logic 102 outputs a decrement signal to the RC register 103, and the processor core 100 receives the memory 101 from the memory 101. The instruction SUB corresponding to the previous memory address n + 3 is fetched [F (n + 3)].

In the ninth cycle 68, the processor core 100 executes the instruction ADD, and the RC register 103 decreases the repetition count value BRC from 2 to 1 in accordance with the decrement signal [R / E ( n + 2)]. The processor core 100 decodes the fetched instruction SUB and fetches [D (n + 3)] and fetches the instruction CALL from the memory 101 [F (n + 1)].

Subsequently, the operation from the fourth cycle 63 to the eighth cycle 67 is performed again, and if the PC value n + 2 coincides with the repetition end address REA again, the RPTB control logic 102 receives the RC register. A decrease signal is output to (103). Accordingly, the RC register 103 decreases the repetition count value BRC to 0 according to the decrement signal, and the processor core 100 determines that the repetition count value BRC of the RC register 103 becomes 0 when the RPTB control logic ( 102 is disabled.

In addition, the data processing operation of the conventional processor will be described with reference to the following <Program 2>.

<Program 2>

STM BRC # 2 n-1

RPTB n + 2 n

CALL n + 10 n + 1

ADD n + 2

RET n + 10

NOP n + 11

In <Program 2>, the repeat count value BRC is set to "2" similarly to <Program 1>. However, unlike <Program 1>, <Program 2> has a repetition end address REA set to "n + 2", and the RPTB instruction includes only two instructions CALL and ADD.

Therefore, when executing <Program 2>, the first cycle 70 to the third cycle 72 is the same as <Program 1>.

In the fourth cycle 73, the RPTB control logic 102 sets the repetition end address REA to "n + 2" and the repetition start address RSA to "n + 1" [R / E (n) ]. The processor core 100 decodes the fetched instruction CALL and then controls the PC generation logic 106 so that the memory address n + 2 can be stored in the memory 101 [D (n + 1)]. . In addition, processor core 100 controls PC generation logic 106 such that n + 10 becomes the next PC value.

At this time, the RPTB control logic 102 outputs a reduction signal to the RC register 103 because the PC value n + 2 coincides with the repetition end address REA. The processor core 100 fetches an instruction ADD corresponding to the memory address n + 2 [F (n + 2)].

Then, in the fifth cycle 74, the memory 101 stores the memory address n + 2, and the RC register 103 decreases the repetition count value BRC from 2 to 1 in accordance with the decrement signal [R / E (n + 1)]. The processor core 100 does not decode the fetched instruction ADD because the previous instruction is CALL [D (n + 2)] and increases the PC generated logic 106 to increase the PC value to "n + 11". To control. The processor core 100 fetches an instruction FET corresponding to the previous memory address n + 2 [F (n + 10)].

The sixth cycle 75 is the same as <Program 1>.

In the seventh cycle 76, the processor core 100 does nothing because it is currently returning (R / E (n + 10)), and the processor core 100 also decodes the fetched instruction NOP. [D [(n + 11)], the instruction ADD corresponding to the memory address n + 2 stored in the memory 101 is fetched [F (n + 2)].

At this time, since the memory address n + 2 stored in the memory 101 is the same as the repetition end address REA, the RPTB control logic 102 outputs the decrease signal to the RC register 103 again, and n + 1. The RS register 105 and the multiplexer 107 are controlled so that the repetition start address RSA can be provided to the program counter 108.

Therefore, in the eighth cycle 77, the repetition count value BRC of the RC register 103 decreases from 1 to 0 according to the decrement signal, and the processor core 100 disables the RPTB control logic 102. .

Here we see that it was executed differently than originally intended in Program 2. That is, in <Program 2>, after repeating the CALL of n + 1 command, the repeat count value BRC is decreased once, and when the CALL is finished and RET is executed, the repeat count value BRC is decreased again.

As a result, the CALL actually executed once by the RPTB instruction and the ADD actually fetched but not executed are displayed in the iteration count register 103 as if executed twice. Therefore, the conventional processor has a problem that the reliability of the program is guaranteed only if there are at least three or more instructions in the RPTB instruction.

Inherently, the processor accepts an unexpected input from the outside as an interrupt. The processor receives the interrupt, saves its current state (including its address), executes a particular program, and then returns to its previous state. This is very similar to the CALL command. If a program contains an iteration block of three or more instructions and an interrupt is encountered when the processor executes the last part of the iteration block (after the control signal is output to reduce the BRC), the processor executes the interrupt and then resumes. Will not return to the state of. This is the result of the BRC being reduced again after the interrupt is executed. Therefore, in the conventional processor, when an interrupt comes in when the processor executes the last part of the iteration block, the program is not executed correctly due to the double reduction of the BRC.

Therefore, in order to solve the above problem, there is a method to disable the interrupt when the last command is executed when executing the RPTB command, but preventing the interruptable command from receiving the interrupt reduces the efficiency of the application program including the RPTB command. Dropped.

Accordingly, an object of the present invention is to provide a data processing method of a processor that can ensure the reliability of program execution regardless of the number of instructions included in the RPTB instruction.

Another object of the present invention is to provide a data processing method of a processor that can prevent a double count of a repeat count value when a CALL instruction is executed, thereby preventing the instruction not actually processed from being mistaken as being executed.

In order to achieve the above object, a data processing apparatus of a processor according to the present invention stores a processor core for processing an instruction in a pipeline form, and a memory address of a next instruction to be decoded and executed by the processor. In the processor consisting of a program counter, a program counter generation logic for increasing a program counter value under the control of the processor and outputting the program counter value to the program counter, and a memory in which a program including a repeat block command is stored, the repeat count value is set. A first process to decode, and a repeating block instruction fetched from the memory to set a repeat end and repeat start address, a second process of fetching the first instruction of the repeating block, and decode and execute the first instruction. The third process of fetching the second instruction of the second instruction, and the memory address of the second instruction is repeated A fourth step of comparing the first address with a second address; a fifth step of checking whether the first command is a nonlinear change in the execution order of the program if the two addresses match in the fourth step; and the first command is the execution of the program. In the case of non-linear order changing, the sixth process stores the memory address of the second command and does not decrease the repeat count value.

1 is a block diagram of a conventional processor for executing a program including an iterative block instruction.

FIG. 2 shows an instruction pipeline consisting of three stages: Fetch (F)-Decode (D)-Read / Execute (R / D).

FIG. 3 is a diagram illustrating an execution process of <Program 1> including an iteration block command in FIG.

4 is a diagram illustrating an execution process of <Program 2> including an iteration block command in FIG.

5 is a block diagram of a processor according to the present invention for executing a program including a repeat block instruction.

*** Explanation of symbols for the main parts of the drawing ***

100: processor core 101: memory

102: RPTB control logic 103; RC register

104: RE register 105: RS register

106: PC-generated logic 107: Multiplexer (MUX)

108: program counter (PC) 109: RPTB modified logic

4, the processor according to the present invention further includes an RPTB modification logic 109 in the conventional processor structure shown in FIG.

The RPTB modification logic 109 is an RC register from the RPTB control logic 102 when the instruction being decoded in the processor core 100 changes the execution order of the program into a nonlinear form (Branch, Call, etc.). The reduction signal input to 103 is blocked. Further, when the RPTB control logic 102 is disabled because the repetition count value BRC becomes 0, the RPTB correction logic 109 is configured to reduce the RPTB control logic 102 if the decrease in the repetition count value BRC is due to double reduction. Enable) again.

The data processing operation of the processor according to the present invention configured as described above will be described with reference to the malfunction of the above-described <Processor 2>.

In the fourth cycle, the RPTB control logic 102 sets the repetition end address REA to "n + 2" and the repetition start address RSA to "n + 1" [R / E (n)]. The processor core 100 decodes the fetched instruction CALL [D (n + 1)], and stores the memory 101 and the PC generation logic such that the memory address n + 2 can be stored in the memory 101. 106). The processor core 100 then controls the PC generation logic 106 so that n + 10 is set to the next PC value, and notifies the RPTB correction logic 109 that the instruction currently being decoded is CALL. At this time, since the PC value (n + 2) generated by the PC generation logic 106 is the same as the repetition end address (REA) (n + 2), the RPTB control logic 102 is repeated with the RPTB modification logic 109. A decrease signal for reducing the count value BRC is output. In addition, the processor core 100 fetches an instruction ADD corresponding to the memory address n + 2 from the memory 101 [F (n + 2)].

In the fifth cycle, the memory 101 stores a memory address n + 2 [R / E (n + 1)]. The processor core 100 does not decode the next instruction ADD because the previous instruction is CALL [D (n + 2)]. The processor core 100 then controls the PC generation logic 106 to increase the PC value to " n + 11 " and fetches an instruction FET corresponding to the memory address n + 2 [F ( n + 10)].

However, since the CALL instruction changes the execution order of the program into a non-linear form, the instruction following CALL is not executed. Therefore, the RPTB correction logic 109 does not output the BRC reduction signal input from the RPTB control logic 102 to the RC register 103 because it determines that it is not the end of the RPTB yet. That is, the RPTB correction logic 109 blocks the decrement signal input to the RC register 103 by recognizing that the command executed when generating the BRC reduction signal is CALL, thereby reducing the iteration count value BRC of the RC register 103. It doesn't work.

Therefore, the present invention can execute the program correctly even when there are only two instructions in the RPTB instruction, and it is possible to prevent the double reduction of the repetition count value BRC which has been a problem in the conventional processor when executing the CALL instruction. In addition, the present invention prevents double reduction of the iteration count value BRC, thereby solving the conventional problem caused by mistaken that the instruction ADD that was not actually processed is executed.

Although the present invention has been described using CALL, which is the most representative example, the present invention is not limited thereto, and the present invention can be applied to all instructions for changing the execution order of a program into a nonlinear form. The present invention can also be applied to interrupts, which are branch instructions with the highest priority.

In addition, the foregoing embodiments of the present invention are not limited to the claims by way of example only, and various alternatives, modifications, and changes will be apparent to those skilled in the art.

As described above, the processor according to the present invention has the effect of increasing the reliability and efficiency of the application program containing the iteration block instruction by removing the restriction of the number of instructions in the iteration block instruction.

The present invention prevents the double reduction of the block count value, which was a problem in the conventional processor when executing the CALL instruction, and can solve the conventional problem caused by mistaken that the instruction was not actually processed.

Claims (5)

A processor counter for processing instructions in a pipeline form, a program counter for storing memory addresses of the next instruction to be decoded and executed by the processor core, and a program counter value for increasing the program counter value under the control of the processor core. In the processor structure comprising a program counter generating logic to provide, and a memory for storing a program containing a repeat block instruction, A first step of setting a repetition count value; Decoding a repeating block instruction fetched from the memory to set a repeating end and repeating start address, and fetching a first instruction of the repeating block; A third step of decoding and executing the first instruction and fetching the next second instruction; A fourth step of comparing whether the memory address of the second command matches the repetition end address; A fifth step of checking whether the first command is a non-linear order of execution of the program if the two addresses match in the fourth step; And a sixth step of storing the memory address of the second instruction and not reducing the repetition count value if the first instruction is a non-linear instruction for changing the execution order of the program. The method of claim 1, wherein the iteration count value is loaded by a processor core before execution of the iteration block instruction. The data of the processor as claimed in claim 1, wherein the fifth process further includes providing a repetition start address to the program counter when the memory address matches the repetition end address, and executing the repetitive block command again. Treatment method. The processor of claim 1, further comprising: if the first instruction is a non-linear instruction for changing the execution order of the program, reducing the iteration count value after executing the first instruction. Data processing method. The processor of claim 6, wherein the sixth step is to reduce the repetition count value without storing the memory address of the second instruction if the first instruction is a linear change of the execution order of the program. Way.