KR20010057811A - apparatus for error controlling in parallel bus system - Google Patents

Abstract

PURPOSE: An apparatus for controlling an error of a parallel bus system is provided to prevent a system down phenomenon, and to automatically restore a master by temporarily stopping a spurious interrupt error, and by automatically resetting the master. CONSTITUTION: A slave interface unit(100) applies an interrupt request signal(SIRQ*) to a master interface unit(200), and receives an interrupt response signal(SIACK*) from the master interface unit(200). The slave interface unit(100) applies a data transmission response signal(SDTACK*) and a vector number to the master interface unit(200). The master interface unit(200) receives the request signal from the slave interface unit(100), and transmits the signal to an error control unit(300). The master interface unit(200) applies the response signal(EIACK*) to the slave interface unit(100). The error control unit(300) receives the request signal(EIRQ*) from the master interface unit(200), and applies the signal to a CPU(400). The error control unit(300) applies the response signal(IACK*) applied from the CPU(400) to the master interface unit(200). The CPU(400) applies the response signal(IACK*) to the error control unit(300). The CPU(400) applies a clock signal(CLOCK) to the error control unit(300).

Description

Apparatus for error controlling in parallel bus system}

The present invention relates to an error control apparatus for a parallel bus system, and more particularly, to an error control apparatus for a parallel bus system that can automatically recover when a spurious interrupt error occurs in a master board due to a problem such as detach / mounting.

In general, in a parallel bus system using a parallel bus such as a Versa Module Europe (VME) bus, data is exchanged through a common parallel bus. FIG. 1 shows a diagram of one master and multiple slaves connected through the VME bus. to be.

As shown in Fig. 1, one master 3 and a plurality of slaves 5-1, 5-2, ..., 5-n are conventionally connected via a VME bus. Here, each slave board 5-1, 5-2, ..., 5-n has an IPC (Inter Process) between the master board 3 and the slave boards 5-1, 5-2, ..., 5-n. Communication DPRAM is provided for communication.

As described above, the VME bus used to connect one master 3 and a plurality of slaves 5-1, 5-2, ..., 5-n includes a data bus for transmitting and receiving data and address information. And an address bus for transmitting the control signal and a control signal bus for transmitting various control signals.

As shown in FIG. 2, when the slave's CPU (not shown) writes data to be transmitted to another slave in DPRAM (not shown), the slave interface unit 10 transmits data to the other slave. An interrupt request signal (SIRQ *) is applied to the master interface unit 20, and the master interface unit 20 transmits an interrupt request signal SIRQ * received from the slave interface unit 10 to the CPU 30. The CPU 30 applies the interrupt response signal IACK * to the master interface unit 20 in accordance with the interrupt request signal IRQ *, and sends the interrupt response signal IACK * from the CPU 30 to the master interface unit 20. The master interface unit 20 is applied to apply the interrupt response signal (SIACK *) to the slave interface unit 10. In this way, the slave interface unit 10 receiving the interrupt response signal SIACK * from the master interface unit 20 gives the master interface unit 20 a vector number and a data transmission response signal SDTACK *. The master receiving the data transfer response signal DTACK * starts the interrupt service associated with it. The master accesses the DPRAM (not shown) of the slave to check the destination, the transmission destination, and the size of the data, and the parallel bus. The data recorded in the DPRAM (not shown) of the slave is moved to the DPRAM (not shown) of the other slave through the VME bus.

As described above, since the master is solely responsible for data movement between slaves when exchanging data through the VME bus, spurious interrupt errors frequently occur in the master due to noise and overcurrent due to demounting, and such spurious interrupt errors. Occurs continuously and is not recoverable, causing the system to crash.

In other words, a spurious interrupt error means that when a master sends an interrupt response signal (IACK *) to a slave, the slave must send a vector number and a data transfer response signal (DTACK *) to the master within a certain time, which is slaved within a certain time. It is caused by not sending the vector number and the data transmission response signal (DTACK *). If the cause of the spurious interrupt error is the slave problem, the system does not shut down because the master resets the slave after a certain time. If an error occurs in the master, recovery becomes difficult and the system is down.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and by configuring an error control unit in the master to temporarily prevent spurious interrupt errors and automatically reset the master, thereby preventing system down and automatically recovering the master. It is an object of the present invention to provide an error control device for a parallel bus system.

1 shows one master and multiple slave connections via a VME bus.

Figure 2 is a view showing the operation of the conventional parallel bus system.

3 is a diagram showing the configuration of an error control apparatus for a parallel bus system according to the present invention;

4 is a diagram illustrating a configuration of an error controller in FIG. 3.

5 is a diagram illustrating a configuration of a spurious controller in FIG. 4.

*** Explanation of symbols for the main parts of the drawing ***

100. slave interface unit, 200. master interface unit,

300. Error control unit, 310. Spurious control unit,

311.shift register, 312.counter,

313, 317. Logic circuit section, 314. Negative gate,

315, 316, OR circuit portion, 330. Buffer,

400. CPU

An error control apparatus for a parallel bus system of the present invention for achieving the above object includes a master interface unit receiving an interrupt request signal, a data transmission response signal, and a vector number from a slave; A control unit responsive to an interrupt request signal received from the slave through the master interface unit and starting an interrupt service based on a data transfer response signal and a vector number received from the slave; It is provided between the master interface unit and the control unit detects the occurrence of the spurious interrupt error based on the clock signal received from the control unit, and if a large number of spurious interrupt errors occur, the reset signal is applied to the master interface unit, the alarm to the control unit And an error control unit for notifying a spurious interrupt error occurrence by applying a signal.

Here, the error control unit detects the occurrence of the spurious interrupt error by receiving the interrupt response signal from the control unit and counting the clock signal applied from the control unit, and resets the reset signal to the master interface unit when a large number of spurious interrupt errors occur. A spurious controller for applying an alarm signal and applying an alarm signal to the controller; And a buffer for storing the vector number of the slave that requested the interrupt when a spurious interrupt error occurs.

The spurious control unit may include: a shift register configured to change the spurious cutoff clock signal to a high level state when the clock signal is input a predetermined number of times after receiving the inverted interrupt response signal from the control unit; A counter for receiving the spurious cutoff clock signal as an input signal of a clock terminal and initializing the spurious cutoff clock signal based on an initialization signal received from the controller; A first AND circuit unit for converting the spurious cut-off state signal into a high level state when the spurious cut-off clock signal is continuously input to the input signal of the clock terminal a predetermined number of times; A negative gate for inverting the spurious cut-off state signal and applying the reset signal to the master interface unit as a reset signal and to the control unit as an alarm signal; A first OR circuit unit for generating an interrupt request signal by ORing the spurious cut-off state signal input from the first AND circuit unit and the interrupt request signal received from the slave; A second logic sum circuit unit for generating a virtual interrupt response signal by ORing the spurious cut-off state signal inverted at the negative gate and the inverted data transmission response signal received from the master interface unit; And a second logical AND circuit unit configured to logically multiply the virtual interrupt response signal and the interrupt response signal received from the controller to generate an interrupt response signal.

The buffer uses an inverted initialization signal, a reset signal, and a data transfer response signal as a logic output signal as an input signal of a write enable terminal, and the initialization signal as an input signal of an output enable terminal. It is characterized by.

The controller, when receiving an alarm signal from the error controller, applies a initialization signal after a predetermined time to notify normal operation.

Hereinafter, an error control apparatus for a parallel bus system according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a diagram illustrating a configuration of an error control apparatus of a parallel bus system according to the present invention.

As shown in FIG. 3, the error control apparatus of the parallel bus system according to the present invention applies an interrupt request signal SIRQ * to the master interface unit 200, and receives an interrupt response signal (from the master interface unit 200). Slave interface 100 for receiving the data transmission response signal SDTACK * and the vector number to the master interface 200, and interrupt request signal SIRQ * from the slave interface 100. A data transmission response signal received from the slave interface unit 100 by applying the interrupt response signal EIACK * received from the error control unit 300 to the slave interface unit 100 by being applied to the error control unit 300. The interrupt request signal EIRQ * is applied from the master interface unit 200 to apply (SDTACK *) and the vector number to the error control unit 300. In this case, an interrupt response signal IACK * applied to the CPU 400, the interrupt response signal IACK * received from the CPU 400 is applied to the master interface unit 200, and a data transfer response signal EDACK * provided from the master interface unit 200. ) And a vector number to the CPU 400, and when a spurious interrupt error is detected and a large number of spurious interrupt errors occur, the reset signal SRESET * is applied to the master interface unit 200 and an alarm signal is sent to the CPU 400. (ALARM *) is applied, the error control unit 300 receives the initialization signal (INIT *) from the CPU 400, the interrupt response signal in response to the interrupt request signal (IRQ *) received from the error control unit 300 (IACK *) is applied to the error control unit 300, and the interrupt service is started based on the data transfer response signal DTACK * and the vector number received from the error control unit 300, and the predetermined time unit (approximately 10 ms). Error control unit ( When the clock signal CLOCK is applied to the controller 300 and the alarm signal ALARM * is received from the error controller 300, the CPU 400 that applies the initialization signal INIT * to the error controller 300 after a predetermined time is applied. It is made.

4 is a road showing the configuration of the error control unit in FIG. 3, and as shown in FIG. 4, the error control unit 300 sends the interrupt request signal EIRQ * received from the master interface unit 200 to the CPU 400. And an interrupt response signal IACK * received from the CPU 400 to the master interface unit 200, and a clock signal (applied from the CPU 400 at the same time as the interrupt response signal IACK * is received. CLOCK) is counted to detect the presence of a spurious interrupt error, and if a spurious interrupt error occurs, the reset signal SRESET is applied to the master interface unit 200 and the alarm signal ALARM * is applied to the CPU 400. And a spurious control unit 310 receiving an initialization signal INIT * from the CPU 400, and a buffer 330 for storing a vector number loaded on the data bus when a spurious interrupt error occurs. It is broken.

Here, the buffer 330 is configured to logically combine the inverted initialization signal INIT *, the reset signal SRESET *, and the data transmission response signal EDTACK * to output the input signal of the WE (Write Enable) terminal. When a spurious interrupt error occurs and the signal input to the WE terminal is activated, the vector number stored on the data bus is stored. The initialization signal INIT * output from the CPU 400 is used as an input signal to the OE (Output Enable) terminal. When the initialization signal is received from the CPU 400, the contents stored in the buffer 330 are written. The output is provided to the CPU 400.

5 is a road illustrating the configuration of the spurious controller in FIG. 4, and the spurious controller 310 receives an inverted interrupt response signal IACK * and a clock signal CLOCK (approximately 10 Hz) from the CPU 400 and is inverted. After receiving the interrupt response signal IACK *, if the clock signal CLOCK is input about three times in succession, the shift register 311 and the shift register 311 change the spurious cutoff clock signal SPBCLK to a high level and output the same. A counter 312 which receives the spurious cut-off clock signal SPBCLK output in the high level state as a clock signal CLK, and initializes it based on the initialization signal INIT * received from the CPU 400; When the spurious cut-off clock signal SPBCLK is input to the counter 312 as the clock signal CLK about five times in succession, the logical product turns the spurious cut-off state signal SPBST to a high level and outputs the result. The negative gate which inverts the furnace section 313 and the spurious cut-off state signal SPBST, applies the reset signal SRESET * to the master interface unit 200, and applies the alarm signal ALARM * to the CPU 400. 314 and an interrupt request for logically applying the spurious cut-off state signal SPBST input from the AND circuit 313 and the interrupt request signal EIRQ * received from the master interface unit 200 to the CPU 400. The OR circuit unit 315 generating the signal IRQ *, the spurious cut-off state signal SPBST inverted at the negative gate 314 and the inverted data transfer response signal EDTACK * applied from the master interface unit 200. To the OR circuit unit 316 for generating the virtual interrupt response signal VIACK * and the master interface unit by ANDing the virtual interrupt response signal VIACK * and the interrupt response signal IACK * received from the CPU 400. (200) And a logical product circuit unit 317 for generating an interrupt response signal EIACK *.

Hereinafter, an operation process of an error control apparatus of a parallel bus system according to the present invention will be described with reference to FIGS. 3 to 5.

In order for the slave to transmit data to another slave, the slave interface unit 100 interrupts the master interface unit 200 when the slave's CPU (not shown) writes data to be transmitted to the other slave in the DPRAM (not shown). The request signal Slave Interrupt Request SIRQ * is applied, and the master interface unit 200 applies the interrupt request signal SIRQ * received from the slave interface unit 100 to the error controller 300. The error controller 300 which receives the interrupt request signal EIRQ * from the master interface unit 200 transmits the interrupt request signal IRQ * to the CPU 400, and the CPU 400 transmits the interrupt request signal IRQ. The interrupt response signal IACK * is applied to the error controller 300 according to *).

In response to receiving the interrupt response signal IACK * from the CPU 400, the error control unit 300 receives the interrupt response signal IACK *, and at the same time, the data transmission response signal EDTACK * is applied to detect the occurrence of the spurious interrupt error. The applied clock signal CLOCK is counted until it is applied.

That is, the error control unit 300 receives the clock signal CLOCK input from the CPU 400 in units of about 10 Hz and applies the shift signal 311 to the shift register 311. After receiving the interrupt response signal IACK *, the shift register 300 receives the shift register 311. When the clock signal (CLOCK) is input three times in succession (usually 30 seconds pass, a spurious interrupt error occurs one time, so the clock signal input in units of 10 Hz is checked three times). When the clock signal SPBCLK is activated to a high level and applied to the clock terminal input of the counter 312, and the spurious blocking clock signal SPBCLK is input five times in succession to the clock terminal input of the counter 312, a spurious cut-off signal By activating and outputting (SPBST) to the high level state, the spurious interrupt error occurrence state is output.

As described above, the interrupt request signal EIRQ * received from the slave interface unit 100 through the master interface unit 200 is activated because the spurious interruption state signal SPBST is activated to a high level due to a large number of spurious interrupt errors. If not, the interrupt request signal IRQ * is not applied to the CPU 400.

As described above, when a large number of spurious interrupt errors occur, the error control unit 300 inverts the spurious cut-off state signal SPBST using the negative gate 314 to recover the spurious interrupt error, and transmits the spurious interrupt error signal to the master interface unit 200. The spurious interrupt status signal SPBST is applied to the CPU 400 as an alarm signal ALARM * at the same time as the reset signal SRESET, and the spurious interrupt error occurrence condition is notified.

Accordingly, the CPU 400 receiving the alarm signal ALARM * from the error control unit 300 applies the initialization signal INIT * to the error control unit 300 after a predetermined time to notify the normal operation of the CPU 400. The error control unit 300, which receives the initialization signal INIT * from FIG. 2, initializes the counter 312 based on the initialization signal INIT * received from the CPU 400.

On the other hand, even when the spurious cutoff state signal SPBST is activated at a high level, the slave does not receive the interrupt response signal SIACK * and thus does not terminate the interrupt initial routine, and continues to apply the interrupt request signal SIRQ * to the master. do. Therefore, the slave delays other tasks and waits only for the interrupt response signal IACK *. To this end, the virtual interrupt response signal VIACK * is obtained by logically combining the inverted spurious cut-off state signal SPBST at the negative gate 314 and a signal inverted from the data transfer response signal EDTACK * applied from the master interface unit 200. ) And the virtual interrupt response signal (EIACK *) generated by multiplying the generated virtual interrupt response signal (VIACK *) and the interrupt response signal (IACK *) received from the CPU 400 to the master interface unit ( 200, the master interface unit 200 applies an interrupt response signal SIACK * to the slave interface unit 100.

On the other hand, the buffer 330 is the input signal of the WE (Write Enable) terminal to output a signal that is output by ORing the inverted initialization signal INIT *, the reset signal SRESET *, and the data transmission response signal EDTACK *. When a spurious interrupt error occurs and an input signal activated to the WE terminal is applied, the vector number of the slave requesting the interrupt coming on the data bus is stored. When the initialization signal INIT * is applied to the terminal, the contents stored in the buffer 330 are immediately output to the CPU 400.

Accordingly, the CPU 400 determines the slave according to the contents received from the buffer 330, accesses the DPRAM (not shown) of the slave, checks the destination, the transmission destination, and the size of the data to which the data will move. The data recorded in the DPRAM (not shown) of the slave is moved to the DPRAM (not shown) of another slave through the VME bus, which is a parallel bus.

The error control apparatus of the parallel bus system of the present invention is not limited to the above-described embodiments, and can be implemented in various modifications within the scope of the technical idea of the present invention.

According to the error control apparatus of the parallel bus system of the present invention as described above, an error control unit for detecting the occurrence of the spurious interrupt error in the master is configured to reset the master interface unit when a large number of spurious interrupt errors occur, and the spurious interrupt to the CPU By notifying an error occurrence, there is an effect of automatically recovering a spurious interrupt error and preventing a system down phenomenon.

Claims (5)

A master interface unit receiving an interrupt request signal, a data transmission response signal, and a vector number from a slave; A control unit responsive to an interrupt request signal received from the slave through the master interface unit and starting an interrupt service based on a data transfer response signal and a vector number received from the slave; It is provided between the master interface unit and the control unit detects the occurrence of the spurious interrupt error based on the clock signal received from the control unit, and if a large number of spurious interrupt errors occur, the reset signal is applied to the master interface unit, the alarm to the control unit An error control apparatus for a parallel bus system, comprising an error control unit for applying a signal to notify the occurrence of a spurious interrupt error. The method of claim 1, wherein the error control unit, Upon receiving the interrupt response signal from the control unit, a clock signal applied from the control unit is counted to detect the occurrence of the spurious interrupt error. When a plurality of spurious interrupt errors occur, the reset signal is applied to the master interface unit. A spurious controller for applying an alarm signal; And a buffer for storing the vector number of the slave that requested the interrupt when a spurious interrupt error occurs. The method of claim 2, wherein the spurious control unit, A shift register configured to change the spurious cutoff clock signal to a high level state when the clock signal is input a predetermined number of times after receiving the inverted interrupt response signal from the controller; A counter for receiving the spurious cutoff clock signal as an input signal of a clock terminal and initializing the spurious cutoff clock signal based on an initialization signal received from the controller; A first AND circuit unit for converting the spurious cut-off state signal into a high level state when the spurious cut-off clock signal is continuously input to the input signal of the clock terminal a predetermined number of times; A negative gate for inverting the spurious cut-off state signal and applying the reset signal to the master interface unit as a reset signal and to the control unit as an alarm signal; A first OR circuit unit for generating an interrupt request signal by ORing the spurious cut-off state signal input from the first AND circuit unit and the interrupt request signal received from the slave; A second logic sum circuit unit for generating a virtual interrupt response signal by ORing the spurious cut-off state signal inverted at the negative gate and the inverted data transmission response signal received from the master interface unit; And a second AND circuit portion for generating an interrupt response signal by performing an AND operation on the virtual interrupt response signal and the interrupt response signal received from the controller. The method of claim 2, wherein the buffer, A parallel bus comprising an inverted initialization signal, a reset signal, and a signal which is output by performing a logical sum of a data transmission response signal as an input signal of a write enable terminal and an initialization signal as an input signal of an output enable terminal Error control device of the system. The method of claim 1, wherein the control unit, When the alarm signal is received from the error control unit, the error control device of the parallel bus system characterized in that the normal operation by applying an initialization signal after a predetermined time.