KR20010052206A - Synchronization method for rfid system including tags having different memory sizes - Google Patents

Abstract

The synchronization method for the RFID system 10 having the tags 40-1 to 40-n having different memory sizes is that the reading device 30 is transmitted by the tag 40-1 and that the tag memory 407 has the In order to be able to easily identify the sync word on the continuously modulated RF signal 408 by repetition of the contents, a convention is adopted that the sync word and sync bits are stored in the tag memory 407 during the data bits. After identifying the sync word, the RFID reader 30 reads out the data bits following the identified sync word until the next sync word is received, ignoring the sync bits interspersed among the data bits.

Description

SYNCHRONIZATION METHOD FOR RFID SYSTEM INCLUDING TAGS HAVING DIFFERENT MEMORY SIZES}

Radio frequency indentification (RFID) systems are known and used for a variety of applications. For example, an RFID system may allow employees to gain access to authorized areas using RFID “proximity” cards or tags, or the tags may be secured to the undercarriage of transport trucks and other types of vehicles so that they may Used for access control applications that allow access. As another example, RFID systems are used in animal identification applications where individually handled tags are located in the ears of livestock to identify each animal. In another example, RFID systems are used in container tracking applications where individually handled tags are secured in reusable containers to facilitate accurate recording of their use.

In these and other applications, RFID tags (also called "transponders" or "labels") typically transmit multiple data blocks to an RFID reader. However, the number and size of transmitted data blocks may vary from tag to tag because of differences in memory structure or application needs for storing such data within the tag. Differences in memory or data structure lead to differences in the number of bits or in the number of data blocks of each data block being transmitted. Different companies of tags or memories employed in tags are one cause of the different memory structures used for tags. Advances in manufacturing technology are another cause.

However, in conventional RFID systems, data is generally communicated in a fixed amount as defined by a particular system, and such systems are not capable of reading tags that transmit blocks of any size or number of data. Thus, such systems are incompatible for the provision of existing and future commercially available tags, and the overall cost of using these systems is increased due to their final interoperability. Industry standardization will help eliminate such problems.

Thus, there is a need for a "synchronization method for RFID systems with tags having different memory sizes."

<Summary of invention>

It is an object of the present invention to provide an RFID system capable of reading data transmitted from tags having different memory sizes, due to the different size and number of data blocks for each tag.

Another object of the present invention is to provide a synchronization method and means for facilitating the transmission and reading of data in RFID tags having different memory sizes.

The above and another object are achieved by various features of the present invention, and in brief, one aspect of the present invention is a synchronization method for an RFID system having a tag having a different memory size, the first method of a tag memory. And a step of storing a sync word in the area and storing the data bit and the sync bit in a second area of the tag memory so that the sync word cannot occur in the data bit and the sync bit.

In another aspect, a synchronization method for an RFID system having a tag having a different memory size includes transmitting a continuously modulated synchronization word on an RF signal and continuous modulation on the RF signal such that the synchronization word cannot occur in data bits and synchronization bits. Transmitting the data bits and the synchronization bits.

In still another aspect, a synchronization method for an RFID system having a tag having a different memory size includes a tag memory content storing a synchronization word, a data bit, and a synchronization bit such that a synchronization word cannot occur within the data bit and the synchronization bit. Receiving a continuously modulated RF signal by iteration, identifying one of the iterations of the continuously modulated sync word on the RF signal, and until the next one of the iterations of the sync word is continuously modulated and received on the RF signal. Reading the data bit in accordance with one of the repetitions of the continuously modulated sync word on the RF signal.

In another feature, an RFID tag for an RFID system having a tag having a different memory size includes a tag memory, a control circuit and a modulator circuit. The tag memory has a sync word stored at one end of the tag memory and data bits and sync bits stored in the rest of the tag memory so that the sync word cannot occur in the rest of the tag memory. The control circuit provides an address and a control signal to the tag memory so that the contents of the tag memory can be read. The modulator circuit generates an RF signal that is continuously modulated by the contents of the tag memory.

In yet another aspect, an RFID reading device for an RFID system having a tag having a different memory size includes a receiver circuit and a processor. The receiver circuit is coupled to the continuously modulated RF signal by repetition of the sync word, data bit and sync bit configured such that the sync word cannot occur within the data bit and the sync bit. The processor is coupled to the receiver circuit. The processor identifies by the program one of the repetitions of the sync word, reading the data bits in accordance with one of the repetitions of the sync word until the next one of the repetitions of the sync word is received, and the processor stores the memory storing the program. It is provided.

In yet another aspect, an RFID system having tags with different memory sizes includes a plurality of tags and an RFID reading device. The plurality of tags has a tag memory, a control circuit and a modulator circuit, respectively. The tag memory has a sync word and a sync bit stored in the rest of the tag memory so that a sync word and a sync word stored at one end of the tag memory cannot occur in the data bit and the sync bit. The control circuit supplies an address and a control signal to the tag memory so that the contents of the tag memory can be read. The modulator circuit generates a continuously modulated RF signal by repetition of the contents of the tag memory. On the other hand, the RFID reading device includes a receiver circuit and a processor. The receiver circuit is coupled to the RF signal and the processor. The processor may cause the processor to identify one of the iterations of the continuously modulated sync word on the RF signal to read the data bits following one of the iterations of the sync word until the next one of the iterations of the sync word is received in the RF signal. A memory for storing a program is provided.

Further objects, features and effects of various aspects of the invention will become apparent from the following description of the preferred embodiments which will be described in conjunction with the accompanying drawings.

The present invention relates generally to RFID systems, and more particularly to RFID systems with tags having different memory sizes.

1 is a block diagram of an RFID system with tags having different sizes utilizing features of the present invention.

2 is a diagram illustrating an example of a tag memory structure having a 32-bit sync word utilizing the features of the present invention.

3 is a diagram illustrating an example of a tag memory structure having a 24-bit sync word utilizing the features of the present invention.

4 is a diagram illustrating an example of a tag memory structure having a 16-bit sync word utilizing the features of the present invention.

5 is a diagram illustrating an example of a tag memory structure having a 9-bit sync word utilizing features of the present invention.

FIG. 6 is a diagram illustrating an example of a tag memory structure having 16-bit sync words starting at the head address of the tag memory using features of the present invention.

7 is a diagram showing an example of a tag memory structure having a 16-bit sync word ending at an end address of a tag memory using the features of the present invention.

8 is a diagram illustrating a first example of a conventional tag memory structure.

9 is a diagram illustrating a second example of a conventional tag memory structure.

10 is a diagram illustrating a third example of a conventional tag memory structure.

FIG. 11 is a diagram illustrating an example of repetition of the contents of any one of the first, second, and third examples of a conventional tag memory structure.

12 is a flow chart of a synchronization method for an RFID system having tags with different memory sizes utilizing features of the present invention.

1 is a block diagram of an RFID system 10 having tags with different memory sizes. The RFID system 10 includes a host computer 20, an RFID reading device 30, and a plurality of RFID tags 40-1 through 40-n having different memory sizes. The RFID tag 40-1 represents the RFID tags 40-1 to 40-n, and for the following description, it is assumed that the RFID tag 40-1 is close to the RFID reading device 30, and the RFID tag ( One or more antenna elements 401 of 40-1 receive an exciter signal 301 transmitted through one or more antenna elements 302 corresponding to those of the RFID reading device 30. The exciter circuit 303 of the RFID reading device 30 generates an exciter signal 301.

The power supply circuit 402 of the RFID tag 401 rectifies the received exciter signal 301 to generate an internal power supply voltage Vdd for another circuit in the RFID tag 401. When a command or data is superimposed or modulated to the carrier signal of the exciter signal 301, the power supply circuit 402 transmits the exciter signal 301 to the decode circuit 403. The decode circuit 403 demodulates the exciter signal 301 and performs analog-to-digital conversion to generate a digital command or data, which is supplied to the control circuit 404. The power supply circuit 402 also delivers the exciter signal 301 to the clock generator circuit 405.

The clock generator circuit 405 generates two clock signals. One clock signal has the same frequency as the exciter carrier signal and is supplied to the control circuit 404. The remaining clock signal has a different frequency than the exciter carrier signal and functions as a tag carrier signal for the RF signal 408 transmitted to the modulator circuit 406 and transmitted from the RFID tag 40-1. In a preferred embodiment, the frequency of the tag carrier signal is approximately half the frequency of the exciter carrier signal so that it can be distinguished from the exciter carrier signal.

The control circuit 404 has an address counter (not shown) that increments the address to the tag memory 407. In response to the exciter signal 301, the control circuit 404 generates an appropriate control signal to repeatedly read information from the tag memory 407 in a continuous form at the rate of the exciter carrier signal. The information is then supplied to the modulator circuit 406. The modulator circuit 406 superimposes or modulates the information on the tag carrier signal such that a continuously modulated RF signal 408 is generated by repetition of the contents of the tag memory 407. In a preferred embodiment, the RF signal 408 is continuously modulated by repetition of the sync word, data bit, and sync bit configured such that no sync word can occur within the data bit and the sync bit. The transmit antenna 409 coupled to the modulator circuit 406 transmits the RF signal 408 to the receive antenna 304 of the RFID reading device 30.

Receiver circuit 305 is coupled to RF signal 408 via receive antenna 304 to receive and amplify RF signal 408. Preferably, the receiver circuit 305 converts the frequency of the RF signal 408 to an intermediate frequency for further amplification and band filtering before it is supplied to the detector circuit 306. The detector circuit 306 detects the continuously modulated information on the RF signal 408 and provides the information to the processor 307, which generates an output in a form usable by the host computer 20. The processor 307 has a memory (not shown) that stores a program to be executed by the processor 307. The host computer 20 processes the information passed to it by the processor 307.

The tag memory 407 may vary in size due to a data structure having a different number of blocks and / or a different number of bits per block, or a case where the tag memory 407 is configured. For example, FIG. 2 shows a data structure of the tag memory 407 having seven blocks of 32 bits each, FIG. 6 shows a data structure having seven blocks of 16 bits each, and FIG. 8 respectively. A data structure is shown having three blocks of five hexadecimal characters (or 20 bits each because each hexadecimal character is 4 bits).

Since the contents of the tag memory 407 are repeatedly read so as to be continuously modulated on the RF signal 408, the RFID reading device 30 may repeat the repetitive pattern (i.e., the contents of the tag memory 407) without prior knowledge of the data structure. It will be difficult or impossible to decide. For example, in FIG. 8, the pattern "0123456789ABCDE" is stored in the first example of the conventional tag memory structure, and in FIG. 9, the pattern "56789ABCDE01234" is stored in the second example of the conventional tag memory structure, and in FIG. The pattern "ABCDE0123456789" is stored in the third example of the conventional tag memory structure. However, the problem is that since the information is read from the tag memory 407 starting from the top left to the right along each block, the blocks are read from top to bottom and ending at the bottom right, each of these patterns is identical to that shown in FIG. Generates a repetitive or cyclical pattern. As another example, in any repetitive pattern, such as all 1's, all 0's, or alternating 1's and 0's, it is practical for the RFID reader 30 to determine the length of the pattern that occurs repeatedly without prior knowledge of the data structure. impossible.

Thus, a feature of the present invention includes a sync word starting at the leading address of the tag memory 407 or ending at the ending address of the tag memory 407, so that the RFID reading device 30 has a tag memory in the RF signal 408. The content of 407 can be read as appropriate. To ensure that the sync word is not accidentally duplicated somewhere other than a recurring pattern, the sync bit is interspersed in the appropriate bit position of the recurring pattern. Thereafter, the RFID reading device 30 searches for the sync word first and then repeats it by reading the data following the sync word until the next occurrence of the sync word, ignoring, masking or striping the sync bit. Can be determined.

6, the sync word 52 is shown as " 1000000000000001 " starting at the head address of the tag memory 407, and " 01 " as the sync bit set 54 of the seventh block of the memory structure. The set of sync bits of is interspersed among data bits " x " such as data bits 56 and the like so that a sync word cannot occur within the data bits and the sync bits. The sync word and sync bit are both referred to as "system bits" and the data bits are referred to as "user data bits". Consecutive data bits between the sync word and the sync bit set or between the sync bit sets are referred to as "data words" such as the data word 58 of the second block of the tag memory 407. 7 shows another example of the data structure in which the sync word ends at the end address of the tag memory 407.

In order to easily identify the sync word, the sync word is predefined as a bit pattern with the largest number of zeros between two 1s in the content of the data structure. In order to ensure that the sync word has the largest number of zeros between two 1s, the number of bits of " 01 " A set of sync bits is periodically inserted between the data bits. It is also possible to use one sync bit "1" instead of the sync bit pair "01". In this case, the number of data bits between adjacent sync bits is less than three (3) bits smaller than the number of bits of the sync word.

Although the number of data bits between the adjacent sync bit sets " 01 " is less than 4 bits smaller than the number of bits of the sync word, the number of data bits between the adjacent sync bit sets so that the maximum number of bits is available in the data structure of the data bits. Is preferably set equal to 4 bits smaller than the number of bits of the sync word. Further, by following this rule, since the RFID reader 30 can easily determine the position of the sync bit after identifying the sync word, the RFID reader 30 continuously modulates on the RFID signal 408. It is easier to mask or strip the sync bit while reading the written data bit.

Further, by following the convention that the sync word has the entire first data block as shown in FIG. 2, the data structure of the tag memory 407 can also be easily determined by the RFID reading apparatus 30. FIG. However, this provision is not practical for data structures with relatively few blocks. Also, shorter sync words as shown in FIG. 3 sometimes make more data bits available in the tag memory 407 than sync words that use up the entire first block. However, as shown in Figs. 4 and 5, this is not a general case.

Therefore, in summary, by storing the known synchronizing word and the synchronizing bit in the memory 407, the RFID reading apparatus 30 stores the contents or repetitive patterns stored in the memory from information modulated in the received RF signal 408. Can be easily determined. The implementation of the RFID reading device 30 is simple and is within the scope of those skilled in the art.

12 is a flowchart of a synchronization method for an RFID system 100 having tags 40-1 through 40-n having different memory sizes. The first step 1201 includes storing a sync word in a first area of the tag memory. As shown in Fig. 6, the first region is preferably a continuous bit position starting at the head address of the tag memory. In this case, storing the sync word includes storing the sync word at consecutive bit positions starting at the head position of the tag memory. Further, as shown in Fig. 7, the first region may be a continuous bit position ending at the end address of the tag memory. In such case, storing the sync word includes storing the sync word at a contiguous bit position ending at an end address of the tag memory. Since the sync word is preferably defined as a bit pattern in which the largest number of zeros is inserted between two 1s in the contents of the data structure of the tag memory, the storing of the sync word is performed in the first binary state. Storing one bit, storing a plurality of bits in a second binary state, and storing one bit in the first binary state. The storage of the sync word is preferably performed by programming the tag memory by conventional methods and post-production means. However, in another method, the synchronization word can be stored with similar advantages during the manufacturing process of the tag memory or the tag by the conventional methods and means.

The second step 1202 includes storing data bits and sync bits in a second area of the tag memory such that the sync word cannot occur in the data bits and the sync bits. The second area is the remainder of the tag memory after storing the sync word in the tag memory. In a general form, sync bits are distributed between the data bits such that the sync word cannot occur in the remainder of the tag memory. More specifically, storing the data bits and the sync bits comprises organizing the data bits into data words each having at least four data bits less than the number of bits of the sync word, at least one of the first binary states. Organizing the sync bits into a set of sync bits each having bits, and storing the data word and the sync bit set in the tag memory by interleaving the sync bit set with the data word. The storage of data bits and sync bits is preferably carried out by programming the tag memory by conventional methods and post-production means. However, the storage of the data bits and the sync bits may be carried out with similar advantages during the manufacturing process of the tag memory or tag by conventional methods and means.

The third step 1203 includes transmitting a sync word that is continuously modulated to the RF signal. Advantageously, transmitting the sync word comprises transmitting one bit of a first binary state, transmitting a plurality of bits of a second binary state, and transmitting one bit of the first binary state. Steps. To carry out such steps, the control circuit 404 of the tag memory 407 generates an appropriate control signal so that the information is repeatedly read from the tag memory 407 in a continuous form and provided to the modulator circuit 406. The modulator circuit generates an RF signal 408 that is continuously modulated by the contents of the tag memory 407. A transmit antenna 409 coupled to the modulator circuit 406 transmits an RF signal 408.

A fourth step 1204 includes transmitting data bits and sync bits that are continuously modulated in the RF signal such that the sync word cannot occur in the data bits and the sync bits. Advantageously, transmitting said data bits and sync bits comprises data organized into data words each having at least four data bits less than the number of bits of said sync bits such that said set of sync bits is interleaved with said data word. Transmitting a sync bit organized into a set of sync bits, each having a bit and at least one bit of the first binary state. To carry out such steps, the control circuit 404 of the tag memory 407 generates an appropriate control signal to repeatedly read information from the tag memory 407 in a continuous form and provide it to the modulator circuit 406. The modulator circuit 406 then generates an RF signal 408 that is continuously modulated by the contents of the tag memory 407. A transmit antenna 409 coupled to the modulator circuit 406 transmits an RF signal 408.

A fifth step 1205 is for receiving an RF signal that is continuously modulated by repetition of the contents of a tag memory storing a sync word, a data bit, and a sync bit such that the sync word cannot occur within the data bit and the sync bit. Steps. To perform this step, as described with reference to FIG. 1, the receiver 305 is coupled to the receive antenna 304 to receive and amplify the RF signal 408.

A sixth step 1206 includes identifying one repetition of the sync word that has been continuously modulated with the RF signal. Advantageously, identifying one repetition of said sync word comprises finding a maximum sequence of bits of said second binary state that are continuously modulated to said RF signal. Since the sync word is organized as one bit in the first binary state, a number of bits in the second binary state and one bit in the first binary state, this is the maximum of the bits in the second binary state that are continuously modulated in the RF signal. It involves finding the sequence. In order to execute such a step, the processor 307 has a memory (not shown) for storing a program, which program is executed by the processor 307 using a conventional programming method, the maximum number of consecutive binary states. Finding a bit allows to identify one repetition of the sync word.

A seventh step 1207 reads data bits following the one of the iterations of the sync word continuously modulated to the RF signal until the next iteration of the sync word is continuously modulated to the RF signal. Steps. Advantageously, reading said data bits comprises (a) reading the number of consecutive data bits, said number being four bits less than the number of bits of said sync word, and (b) following said number of consecutive data bits. Reading the next bit, and (c) stopping if the next bit is in the first binary state, or if the next bit is in the second binary state, ignoring the bit following the next bit and going to step (a) Jumping. To execute such steps, processor 307 has a memory (not shown) for storing a program, which program causes the processor to execute such steps using conventional programming methods.

One advantage of the present invention is an RFID system that can read data sent in tags with different memory sizes, allowing compatibility between existing and future commercially available tag offerings. Another advantage is an RFID system that can read data sent in tags with different memory sizes, enabling intersystem implementation and lowering the overall cost of such a system.

While specific embodiments of the invention have been described in detail above, it will be appreciated that various modifications may be made to the preferred embodiment without departing from the scope of the invention. Accordingly, the description is not intended to limit the invention as defined in the appended claims.

Claims (9)

In an RFID tag for an RFID system having a tag having a different memory size, A tag memory having a sync word stored at one end of the tag memory, a data bit and a sync bit stored in the remaining portion of the tag memory so that the sync word cannot occur in the remaining portion of the tag memory; A control circuit which reads the contents of the tag memory by providing an address and a control signal to the tag memory; And a modulator circuit for generating an RF signal that is continuously modulated by the contents of the tag memory. The RFID tag of claim 1, wherein the sync word comprises one bit of a first binary state, a plurality of bits of a second binary state, and one bit of the first binary state. . 3. The RFID tag of claim 2, wherein the sync bit is interspersed between the data bits such that the sync word cannot occur in the remainder of the tag memory. 4. The apparatus of claim 3, wherein the data bits are organized into data words, each having four bits of data bits less than the number of bits of the sync word, wherein the sync bits are in the first binary state. And a set of sync bits having at least one bit, said set of sync bits interleaving with said data word. An RFID reading apparatus for an RFID system having a tag having a different memory size, comprising: A receiver circuit coupled to an RF signal that is continuously modulated by repetition of the sync word, data bit, and sync bit so that the sync word cannot occur within the data bit and the sync bit; A memory coupled to the receiver, the memory storing a program, the program identifying one repetition of the sync word and following the one repetition of the sync word until the next repetition of the sync word is received. And a processor for reading data bits. 6. The RFID reading device of claim 5 wherein each of said sync words comprises one bit of a first binary state, a plurality of bits of a second binary state, and one bit of said first binary state. 7. The apparatus of claim 6, wherein the data bits are organized into the data words, the data words each having a number of four bits of data less than the number of bits of the sync word, wherein the sync bits are in the first binary state. And a set of sync bits comprising at least one bit of said sync bits, said set of sync bits being interleaved with said data word. 8. The RFID reading device of claim 7, wherein said program causes the processor to identify one repetition of the sync word by finding the longest sequence of bits in the second binary state. In an RFID system having tags with different memory sizes, A plurality of tags each having a tag memory, a control circuit and a modulator circuit, An RFID reading device having a receiver circuit and a processor, The tag memory has a sync word stored at one end of the tag memory and a data bit and a sync bit stored in the remaining portion of the tag memory so that the sync word cannot occur in the data bit and the sync bit. Providing an address and a control signal to the tag memory to read the contents of the tag memory, wherein the modulator circuit generates a continuously modulated RF signal by repetition of the contents of the tag memory, The receiver circuit is coupled to the RF signal and the processor includes a memory for storing a program, the program identifying one repetition of the sync word continuously modulated according to the RF signal by the program, RFID system that reads the data bits following the one iteration of the sync word until a next iteration is received in the RF signal.