MXPA00008993A - Synchronization method for rfid system including tags having different memory sizes - Google Patents

Abstract

A synchronization method for an RFID system (10) including tags (40-1 to 40-n) having different memory sizes, employs a convention wherein sync words and sync bits are stored in tag memory (407) among data bits so that a reader (30) may readily identify the sync word on an RF signal (408) transmitted by a tag (40-1) and serially modulated by repetitions of the contents of the tag memory (407). After identifying the sync word, an RFID reader (30) reads data bits following the identified sync word until a next sync word is received, while ignoring the sync bits interspersed among the data bits.

Description

METHOD OF SYNCHRONIZATION FOR RFID SYSTEMS THAT INCLUDES HEADS THAT HAVE DIFFERENT SIZES OF MEMORY. • 5 Field of the Invention.

The present invention relates generally to RFID systems and in particular, to RFI D systems including tags having different memory sizes. • 10 Background of the Invention.

Radio frequency identification (RFID) systems are well known and have multiple uses. For example, RFID systems are used in access control applications where employees use RFID "proximity" cards or tags to have access to authorized areas, or the signs are bolted to the truck of transport trucks and other types of vehicles, for «Allow them access to a facility. As another example, RFID systems are used in animal identification applications, where individualized tags are placed in the fins of livestock to identify each animal. In yet another example, RFI D systems are used in container tracking applications, where individualized labels are affixed to the containers that are reused, to facilitate accurate records of their use.

In these and other applications, RFI D tags (also referred to as "transponders" or "tags") usually transmit multiple blocks of data to RFID readers. The number and size of the transmitted data blocks may be different among 5 labels, however due to the differences in application requirements and differences in the memory structures these data are stored within the labels. The differences in data memory structures result from the amounts of different data blocks or from the number of different bits in each data block A 10 that is being transmitted. Different manufacturers of the labels or memories, used in the labels, are a cause of the different memory structures that are being used in the labels. Advances in manufacturing techniques are another cause.

However, in conventional RFID systems, the data are generally communicated in fixed amounts, as • defined by the particular system since such systems lack the ability to read labels that transmit blocks of data of arbitrary size or number. Therefore, such systems are forced to be incompatible between the existing labels and those commercially available in the future, and their resultant lack of internal system operability tends to increase the overall cost of using. such systems. The standardization of the industry would help eliminate these problems.

Therefore, there is a need for a "Synchronization Method for RFI D System that includes Signs that Have Different Memory Sizes". • 5 Summary of the Invention. It is an object of the present invention to provide an RFID system that has the ability to read transmitted data from tags having different memory sizes, resulting from the variable size and number of data blocks between the tags.

Another object is to provide a method of synchronization and means for facilitating the transmission and reading of data from RFI tags D having different memory sizes. These and other additional objects are carried out by the different aspects of the present invention, wherein, briefly states that one aspect of the present invention is a synchronization method for an RFI D system that includes tags having different memory sizes, comprising the steps of: storing a sync word in a first area in a memory of label, and storage of data bits and bits sync in a second area in the label memory, so that the word sync can not occur in the data bits and in the sync bits. In another aspect, a synchronization method for an RFID system that includes tags that have different memory sizes, comprises the steps of: transmitting a sync word modulated in series form in an RF signal, and transmitting data bits and sync bits modulated in series form in the RF signal, so that the word sync can not occur in the data bits and the sync bits. In another aspect, a synchronization method for a system • RFI D including tags having different memory sizes, comprising the steps of: receiving an RF signal modulated in series form by repetitions of contents of a tag memory that stores a sync word, data bits, and bits sync so that the word sync can not occur within the bits of Mk 10 data and the sync bits; identification of one of the repetitions of the word sync modulated in series form in the RF signal; and reading of data bits following one of the repetitions of the word sync modulated in series form in the RF signal, until a following of the repetitions of the word sync is received modulated in series form in the RF signal. In yet another aspect, the RFI D tag is for an RFID system that includes tags that have different memory sizes, • comprises a tag memory, a control circuit and a modulator circuit. The pen memory has a sync word stored at one end of the label memory, and data bits and sync bits stored in the remaining part of the label memory, so that the word sync can not occur in the remaining part of the label memory. The control circuit provides direction and control signals for the label memory, so that they are read the contents of the label memory. The modulator circuit generates an RF signal modulated in series form by means of the contents of the tag memory. In yet another aspect, an RFID reader for an RFID system that includes tags that have different memory sizes, • 5 comprises a receiver circuit and a processor. The receiver circuit is coupled to an RF signal modulated in a serial fashion by repetitions of a sync word, data bits and sync bits arranged so that the word sync can not occur within the data bits and the sync bits. The processor is J-coupled to the receiver circuit. The processor includes a memory that stores a program originating so that the processor identifies one of the repetitions of the word sync, and reads the data bits after one of the repetitions of the word sync, until the next one of the repetitions of the word. Sync word is received. In still another aspect, the RFID system that includes tags having different memory sizes, comprises a plurality of tags and an RFID reader. The plurality of tags individually includes a tag memory, a counting circuit and a modulator circuit. The memory of the sign has a word sync stored at one end of the label memory and the data bits and sync bits stored in the remaining part of the label memory, so that the word sync can not occur in data bits or sync bits . The control circuit, provides direction and control signals to the label memory of so that the content of the label memory is read. The modulator circuit generates an RF signal modulated in series form by repeating the contents of the label memory. The RFID reader, on the other hand, includes a receiver circuit and a processor. The receiver circuit is coupled to the RF signal and the processor. The processor includes a memory that stores a program that causes the processor to identify one of the repetitions of the word sync modulated serially in the RF signal, and read the data bits after one of the repetitions of the word sync up that one of the repetitions of k 10 the word sync is received.

The characteristic objects and additional advantages of various aspects of the present invention will be appreciated from the following description of their preferred embodiments, the description of which should be taken in conjunction with the drawings that the accompany.

Brief Description of the Drawings.

Figure 1 is a block diagram of an RFID system that includes labels that have different sizes, using aspects of the present invention.

Figure 2 is an example of a tag memory organization that includes a 32-bit sync word, using aspects of the present invention.

Figure 3 is an example of a label memory organization that includes a 24-bit sync word, using aspects of the present invention.

Figure 4 is an example of a memory organization that includes a 16-bit sync word, using aspects of the present invention.

Figure 5 is an example of a tag memory organization that includes a 9-bit sync word, using aspects of the present invention.

Figure 6 is an example of a memory organization that includes a 16-bit sync word starting at a starting address of the tag memory, using aspects of the present invention.

Figure 7 is an example of a tag memory organization that includes a 16 bit sync word terminating in an end address of the tag memory, using aspects of the present invention.

Figure 8 is a first example of a label memory organization of the prior art.

Figure 9 is a second example of a label memory organization of the prior art.

Figure 10 is a third example of a label memory organization of the prior art.

Figure 11, is an example of repetitions of the contents of one of the first, second third example of a prior art label memory organization. Figure 12 is a flow chart of a synchronization method for an RFI D system that includes tags that have different memory sizes, using aspects of the present invention.

Detailed Description of the Invention. Figure 10 is a block diagram of an RFID system 10 that includes tags that have different memory sizes. Included in the RFID system 10 are a host computer 20, an RFID reader 30, a plurality of RFID tags 40-1 through 40-N that have different memory sizes. The RFID tag 40-1 is representative of the RFI D tags 40-1 to 40-N, and for the purposes of the following description, the RFID tag 40-1 is assumed to be close to the RFI reader D 30, so that its element or more elements antenna 401, receive an exciting signal 301 transmitted through one or more antenna elements 302 corresponding to the RFID reader 30. A driver circuit 303 of the RFI reader D 30 generates the driver signal 301. An energy circuit 402 of the RFI tag D 40-1 rectifies the received driver signal 301 to generate an internal supply voltage Vdd for another circuit in the RFID tag 40-1. If the If commands or data are superimposed or modulated on a conveying signal of the driving signal 301, the power circuit 402 passes the driving signal 301 to an encoder circuit 403. The encoder circuit 403 demodulates the driving signal 301 and performs a conversion Analog to digital to produce the command or • Data in digital form, which is provided by a control circuit 404. The energy circuit 402 also passes the drive signal 301 to a register generating circuit 405. The register generating circuit 405 generates two register signals. A recording signal has the same frequency as the driving conveyor signal A 10 and is provided to the control circuit 404. The other recording signal has a frequency different from that of the driving conveyor signal, and is provided to a modulator circuit 406 for serve as a sign carrier signal for an RF signal 408 transmitted from the RFID tag 40-15. In the preferred embodiment, the frequency of the sign carrier signal is about half the driving conveyor signal to distinguish the two carrier signals. The control circuit 404 includes an address counter (not shown) which increments the address to a tag memory 407. In response to the drive signal 301, the control circuit 404 generates appropriate control signals to cause the information to be read repetitively out of the memory of the tag 407 in series form in the range of the driving conveyor signal . The information is subsequently provided to the modulator circuit 406. The modulator circuit 406 superimposes or modulates the information in the carrier signal of the tag to generate the RF signal 408 modulated in series form, by repetitions of the contents of the tag memory 407. In the preferred embodiment, the signal RF 408 is modulated in series • 5 by repetitions of a sync word, data bits, and sync bits organized so that the word sync can not occur within the data bits and the sync bits. A transmitting antenna 409 coupled to the modulator circuit 406 transmits the RF signal 408 to a receiving antenna 304 in the RFID reader 30. A 10 A receiving circuit 305 is coupled to the RF signal 408, through the receiving antenna 304 for receiving and amplifying the RF signal 408. The receiver circuit 305 also preferably converts the frequency of the RF signal 408 to an intermediate frequency for further amplification and bandpass filtering. before providing it to a detector circuit 306. The detector circuit 306 detects information modulated in series form in the RF signal 408, and provides the information to a processor 307, the • which produces an output in a format usable by the host computer 20. The processor 307 includes a memory (not shown) storing a program that will be executed by the processor 307. The host computer 20 processes the information passed to it, through the processor 307. The tag memory 407 can be of different sizes, being configured in several structures of data memories what have different numbers of blocks and / or different numbers of bits per block. For example, Figure 2 illustrates a data structure for the tag memory 407 having 7 blocks of 32 bits each, Figure 6 illustrates a data structure having 7 blocks of 16 bits each, and Figure 8 shows a block of data. It shines a data structure that • 5 has 3 blocks of 5 hexadecimal characters each (or 20 bits each, since each hexadecimal character is 4 bits). Since the content of the tag memory 407 is read repetitively to be modulated in series form in the RF signal 408, it can be difficult or impossible for the RFI reader D 30 to determine the repetitive pattern (e.g., content of the tag memory 407) without prior knowledge of the data structure. For example in Figure 8, the pattern "0123456789ABCDE" is stored in a first example of a prior art label memory organization; in Figure 9, the pattern "56789ABCDE01234" is stored in a second example of a prior art label memory organization; in Figure 10, the pattern "ABCDE0123456789" is stored in a third example of a prior art label memory organization. Even in problematic form, each of these patterns generates the same pattern repetitive or resource illustrated in Figure 1 1, as the information is read from the tag memory 407 starting from the upper left corner, reading clockwise along each block, reading blocks from the top to the top bottom and ending in the lower right corner. As another For example, in certain repetitive patterns such as, all 1 's, and all O's, or alternatively 1' s and O's, it is also virtually impossible for the RFI reader D 30 to determine the length of the recurrent pattern without prior knowledge of the data structure. Therefore, it is an aspect of the present invention to include • 5 a word sync starting at the starting address of the tag memory 407 or ending at the address of the end of the tag memory 407, so that the RFI reader D 30 can correctly read the contents of the tag memory 407 from the RF signal 408. To ensure that the word sync A 10 is not inadvertently duplicated elsewhere in the recurring pattern, the sync bits are internally dispersed at appropriate bit locations in the recurring pattern. The RFID reader 30, can later determine the recurrent pattern by means of a first encounter of the word sync, later reading the data after the word sync until a next event of the word sync, even if the sync bits are ignored, covered, or removed. Referring briefly to Figure 6, there is shown a sync word 52, "1000000000000001" starting at a start address of the tag memory 407, bit sync groups of "01" of so that the group of bits sync 54 in the seventh block of the memory structure are internally dispersed between the data bits "x" such as data bits 56, so that the word sync can not occur within of data bits and sync bits. The word sync and the sync bits are also referred to as "system bits" and data bits as "user data bits". Successive data bits between the word sync and a group of sync bits, or between groups of sync bits, are referred to as "data words" such as data word 58 in the second block of the tag memory 407. FIG. , illustrates another example of a data structure where the word sync ends at the end address of the tag memory 407. In order to quickly identify the word sync, the word sync is previously defined as a bit pattern in the which the largest number of O's, are sandwiched between two 1's within the contents of the data structure. To ensure that the word sync includes the largest number of O's sandwiched between two 1 's the groups of sync bits of "01" are inserted periodically between the data bits, so that the number of data bits between the adjacent groups of sync bits is less than or equal to (4) bits, less than the number of bits in the word sync. Alternatively, a simple sync bit of "1" can be used in place of the sync bit pair "01". In this case, the number of data bits between the adjacent sync bits could be less than or equal to three (3) bits smaller than the number of bits in the word sync. Although the number of data bits between the adjacent groups of sync bits "01" may be less than four bits less than the number of bits in the word sync, namely the number of data bits between the adjacent groups of bits sync, is set equal to four bits less than the number of bits in the word sync, so that the maximum number of bits becomes available in the data structure of the data bits. Also, following this convention, the locations of the sync bits are therefore easily determinable in this way after the reader RFI D 30 has identified the word sync, making it easier for the reader RFI D 30 to cover or eliminate the sync bits, while reading the data bits modulated serially in the RF signal 408.

In addition, following a convention where the word sync includes the first complete data block, as illustrated in the • Figure 2, the data structure of the tag memory 407 is also easily determinable by the RFI reader D 30. However, this convention can not be practical for data structures that include a relatively small number of blocks. Also, a shorter sync word, as shown in Figure 3 sometimes allows more data bits to be available in the tag memory 407 than a sync word using the first complete block. However, as shown in Figure 4 and Figure 5, this is generally not the case.

Therefore, in short, by storing sync words and 20 sync bits of a known convention in memory 407, RFID reader 30 can easily determine the contents or repetitive pattern stored therein, from the information modulated in an RF signal. 408 received. The implementation of the RFID reader 30 is clear and is within the experience of an expert in the art.

Figure 12 illustrates a flowchart of a synchronization method for the RFID system 10 including tags 40-1 to 40-N that have different memory sizes. A first step 1201 comprises the step of storing a word sync in a first area in the tag memory. The first area is preferably successive to the bit locations starting at a starting address of the tag memory, as illustrated in Figure 6. In this case, the step of storing a word sync comprises the step of storing a word ^ fc 10 sync in successive bit locations, starting a starting address of said tag memory . Alternatively, the first area may be successive bit locations terminating in an end address of the tag memory, as illustrated in Figure 7. In such a case, the step of storing a word sync, comprising the step of storing a sync word in successive bit locations terminating in an end address of said tag memory. Since the word sync is pre-defined preferentially as a bit pattern in which the largest number O's is sandwiched between two 1's inside of the content of the tag memory data structure, the storage step of a sync word, comprises the steps of: storing a bit of a first binary state, storing a plurality of bit of a second binary state, and storing a bit of said first binary state.

The storage of the word sync is preferably carried out by programming the label memory through conventional means and methods after manufacture. However, the storage of the word sync can be performed alternatively with similar benefit during the manufacturing process. • 5 the label memory or the label, through conventional means and methods. A second step 1202 comprises the step of storing data bits and sync bits in a second area in said tag memory, so that said word sync can not occur in said data bits and in said sync bits. The second area is a remaining part of the tag memory after storing the word sync in the tag memory. In general terms, the sync bits that are internally dispersed between said data bits and said word sync, can not occur in said remaining part of said tag memory. More particularly, the step of storing data bits and sync bits, comprises the steps of: organizing data bits in the data words individually having a number of data bits of at least four less than a number of data bits. bit in said word sync; organizing sync bits within the sync bit groups that individually have at least one bit of said first binary state; and storing said data words and said groups of sync bits in said tag memory, interleaving said groups of sync bits in said data words. He The storage of the data bits and the sync bits is preferably carried out by programming the tag memory by means of conventional means and methods after manufacture. However, the storage of data bits and sync bits can be done alternately with a similar benefit, during • 5 the manufacturing process of the label memory or the label by conventional methods and means. A third step 1203 comprises the step of transmitting a sync word modulated in series form in an RF signal. Preferably, said step of transmitting said word sync, comprises the steps of transmitting a bit of a first binary state; transmission of a bit plurality of a second binary state; and transmitting a bit of said first binary state. In order to carry out said step, the control circuit 404 that is in the tag memory 407, generates control signals suitable for originate the information that will be read repetitively out of the tag memory 407 in a serial mode, and provided to the modulator circuit 406 which generates a RF signal 408 modulated in series form, by the content of the tag memory 407. A transmission antenna 409 coupled to the modulator circuit 406, immediately transmits the RF signal 408. A fourth step 1204 comprises the step of transmitting data bits and sync bits modulated in series fashion in said RF signal, so that said word sync can not occur in said data bits. and said sync bits. Preferably, said transmission step of data bits and sync bits, comprises the step of transmitting data bits organized into data words having individually a number of data bits of at least four less than a number of bits in said sync bits, and sync bits organized in groups of sync bits that individually have at least one bit of said first binary state, so that said groups of sync bits are interleaved with said data words. To carry out this step, the control circuit 404 which is in the tag memory 407, generates control signals suitable for generating the information that will be read repetitively out of the tag memory 407, and provided to the modulator circuit 406 which generates a RF signal 408 modulated in series form, by means of the content of the tag memory 407. A transmitting antenna 409 coupled to the modulator circuit 406, immediately transmits the RF signal 408. A fifth step 1205, comprises the receiving step of an RF signal modulated in series form by repetitions of the contents of a tag memory storing a word sync, data bits and sync bits so that said word sync can not occur within said data bits and said sync bits. To carry out this step, the receiver 305 is coupled to the receiving antenna 304, to receive and amplify the RF signal 408, as described with reference to Figure 1. A sixth step 1206 comprises the step of identifying a repetition of said word sync modulated in series form in said RF signal. Preferably, the step of identifying a repetition of said word sync comprises the step of finding a longer sequence of bits of said second binary state modulated in series form in said RF signal. Since the word sync is organized as a bit of a first binary state, a plurality of bits of a second binary state, and a bit of said first binary state, comprises the finding of the longest bit sequence of the second modulated binary state in series form in the RF signal. To carry out said step, the processor 307 includes a memory (not shown), which stores a program that causes the processor 307 to identify a repetition of said sync word, finding a maximum number of consecutive bits in the second binary state, using conventional programming methods.

A seventh step 1207, comprises the step of reading data bits following one of said repetitions of said word sync modulated in series form in said RF signal, until a following repetition of said word sync is received modulated in the form of series in said RF signal. Preferably, said step of reading data bits comprises the steps of: (a) reading a number of successive data bits, said number being four bits smaller than the number of bits of said word sync; (b) reading the next bit followed by said number of successive data bits; and (c) if said next bit is in said first binary state, then it stops or if said next bit is in said second binary state, then a bit that follows from said bit is ignored and skipped back to the step of the subsection ( to). In order to carry out these steps, the processor 307 includes a memory (not shown) that stores a program that causes the processor 307 to carry out said steps, using conventional programming methods.

An advantage of the present invention is that it is an RFID system that has the ability to read data transmitted from labels having different memory sizes, allowing compatibility between existing labels and those commercially available in the future. Another advantage is that it is an RFID system that has the ability to read data transmitted from labels that have different memory sizes, allowing the operability and reduction of the internal system in the overall cost of said system. áfc Although the particular embodiments of the present invention have been described in detail, it will be appreciated that various modifications may be made to the preferred embodiment without departing from the scope of the present invention. Therefore, the above description is not intended to limit the present invention, which is defined in the appended claims.

Claims (9)

1. R E I V I N D I C A C I O N S Having described the present invention, it is considered as l & 5 novelty and, therefore, the content of the following CLAIMS is claimed as property: 1 .- An RFI D tag for an RFID system that includes tags having different memory sizes, comprising: a tag memory having a sync word stored at one end of said tag memory, and data bits and sync bits stored in a remaining part of said tag memory, so that said word sync can not occur in said remaining part of said tag memory. 15 sign; a control circuit that provides direction and control signals for said tag memory, so as to read the contents of said tag memory; and a modulator circuit that generates a modulated RF signal 20 in series form, by said content of said tag memory.
2. 2. - The tag RFI D as described in the Claim 1, further characterized in that said word sync comprises a bit 25 of a first binary state, a plurality of bits of a second binary state and a bit of said first binary state.
3. 3. - The RFID tag as described in the Claim 2, further characterized in that said sync bits are internally dispersed between said data bits so that said word sync can not occur in said remaining part of said tag memory.
4. 4. - The tag RFI D as described in the Claim 3, further characterized in that said data bits are organized into data words having individually a number of data bits which is four bits less than a number of bits of said word sync, said sync bits are organized in groups of sync bits that include at least one bit of said first binary state, and said groups of sync bits are interleaved with said data words.
5. 5. - An RFID reader for an RFID system that includes tags that have different memory sizes, comprising: a receiver circuit coupled to an RF signal modulated in series form by repetitions of a sync word, data bits, and sync bits organized in a manner that said word sync can not occur within said data bits and said sync bits, a processor coupled to said receiver circuit, said processor including a memory that stores a program that causes said processor to identify a repetition of said word sync, and reads the data bits following said repetition of said word sync, until a subsequent repetition of said word sync is received.
6. 6. - The RFID reader as described in the Claim 5, further characterized in that each of said sync words comprises a bit of a first binary state, a plurality of bits, a second binary state, and a bit of said first binary state.
7. 7. - The RFID reader as described in the Claim 6, further characterized in that said data bits are organized into data words having individually a number of data bits which is four bits less than a number of bits of said word sync, said sync bits which are organized in groups of sync bits that include at least one bit of said first binary state, and said groups of sync bits are interleaved with said data words.
8. 8. - The RFID reader as described in the Claim 7, further characterized in that said program causes said processor to identify a repetition of said word sync, finding a longer sequence of bits of said second binary state.
9. 9. An RFID system that includes tags that have different memory sizes, comprising: a plurality of tags that individually include a tag memory, a control circuit, and a modulator circuit, said tag memory having one sync word stored at one end of said tag memory, and data bits and sync bits stored in a remaining part of said tag memory, so that said sync word can not occur in said data bits and said sync bits, 10 providing said circuit, control direction and control signals for said tag memory so that the content of said tag memory is read, and said modulator circuit generating an RF signal modulated in series form by repetitions of said content of said memory from 15 tag, and an RFID reader that includes a receiver circuit and a processor, said receiver circuit being coupled to said RF signal, and said processor including a memory that stores a program that causes said processor 20 identifies a repetition of said sync word modulated in series form in said RF signal, and to read data bits following said repetition of said word sync, until a subsequent repetition of said word sync is received in said RF signal.